JP2008117492A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which power consumption is reduced while circuit constitution is simplified more in a semiconductor device achieving both synchronous read and asynchronous read. <P>SOLUTION: In a synchcronous mode, a sense circuit 54 for synchronous mode decides a data signal based on potential relation of read signals generated at a pair of data lines DL, /DL when an input enable signal INP_Ena is driven at a "H" level. Where, the sense circuit 52 for asynchronous mode is electrically disconnected for the pair of data lines DL, /DL. In an asynchronous mode, an asynchronous enable signal ASY_Ena is held at the "H" level. Thereby, the sense circuit 52 for asynchronous mode is connected electrically to the pair of data lines DL, /DL. The read signals generated at the pair of data lines DL, /DL is differentially-amplified, and data output Dout is output. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a plurality of memory cells, and more particularly to a semiconductor device capable of both synchronous reading and asynchronous reading.

  Advances in semiconductor manufacturing technology have realized SoC (System on a Chip) in which a logic circuit and a memory module capable of accessing data from the logic circuit are formed on the same chip. Since such SoC (System on a Chip) can realize high-speed processing and low power consumption, it is actively applied to various devices.

  By the way, the method of reading data from the memory module is roughly divided into two modes: a synchronous mode in which a memory cell is selected and sensed in synchronization with a clock signal, and an asynchronous mode in which a read operation is executed asynchronously with the clock signal. it can.

  In general, the read mode can be speeded up more in the synchronous mode in which memory cell selection and sense operation are sequentially performed. On the other hand, the asynchronous mode is required when an evaluation test is performed on a memory cell, or when data written in a specific memory cell is read by a parallel writer connected from the outside. For this reason, SoCs have been proposed that can perform read operations in both synchronous and asynchronous modes.

  For example, in Japanese Patent Application Laid-Open No. 2004-199648 (Patent Publication 1), an asynchronous memory device, a synchronous memory device that operates in a page mode, and a synchronous memory device that operates in a burst mode are all realized on one chip. A composite memory device is disclosed.

Japanese Patent Laying-Open No. 2005-108301 (Patent Publication 2) discloses a semiconductor integrated circuit device capable of executing different operation modes in the same memory module. This semiconductor integrated circuit device has both a high-degree-of-freedom asynchronous operation and a high-speed operation mode that are not limited to a cycle time within a predetermined range.
Japanese Patent Laid-Open No. 2004-199648 JP 2005-108301 A

  In the synchronous mode, the selection of the memory cell and the sensing operation for the selected memory cell are performed in synchronization with the clock signal. For this reason, a sense amplifier for performing a sense operation in the synchronous mode is required to perform a high-speed sense operation at a predetermined timing according to the clock signal. On the other hand, in the asynchronous mode, a sensing operation must be executed in response to an address signal input regardless of the clock signal. Therefore, a sense amplifier that performs a sensing operation in the asynchronous mode is required to perform a continuous sensing operation.

  That is, the characteristics required for the sense amplifier in the synchronous mode and the asynchronous mode are different from each other. For this reason, in a memory module that can execute both the synchronous mode and the asynchronous mode, two types of sense amplifiers for performing a sensing operation in each mode are provided independently of each other.

  However, when such a configuration in which two types of sense amplifiers are provided is employed, a read signal obtained from a selected memory cell needs to be supplied to each sense amplifier, and thus power consumption increases relatively. There was a problem. There is also a problem that the overall circuit configuration is complicated.

  Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to reduce power consumption and further simplify a circuit configuration in a semiconductor device capable of both synchronous reading and asynchronous reading. A semiconductor device is provided.

  According to the present invention, a semiconductor device includes a memory array having a plurality of memory cells arranged in a matrix, and a sense amplifier for reading data from the memory cells. The semiconductor device according to the present invention is configured to be able to select a first mode in which a read operation is performed in synchronization with a clock signal and a second mode in which a read operation is performed asynchronously with the clock signal. A data line pair consisting of data lines, an input circuit for supplying a complementary read signal corresponding to the storage data of the selected memory cell to the data line pair, and connected to the data line pair, when the first mode is selected A first sense circuit for reading data and a second sense circuit connected to the data line pair for reading data when the second mode is selected are included. Then, the first sense circuit outputs the first data signal determined based on the potential relationship of the read signal appearing on the data line pair at that time in response to the enable signal given corresponding to the clock signal. The second sense circuit is configured to output a second data signal obtained by differentially amplifying the read signal appearing on the data line pair. Furthermore, the semiconductor device according to the present invention is interposed between a first gate circuit capable of interrupting the power supply potential for driving the first sense circuit, the second sense circuit and the data line pair, And a second gate circuit capable of electrically connecting and disconnecting the second sense circuit and the data line pair. The first gate circuit cuts off the supply of the power supply potential to the first sense circuit when the second mode is selected, and the second gate circuit performs the second sense when the second mode is not selected. The circuit and the data line pair are electrically disconnected.

  According to the present invention, in a semiconductor device capable of both synchronous reading and asynchronous reading, it is possible to realize a semiconductor device with reduced power consumption and a simplified circuit configuration.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that the same or corresponding parts in the drawings are denoted by the same reference numerals and description thereof will not be repeated.

FIG. 1 is a schematic configuration diagram of a semiconductor device 100 according to the present embodiment.
Referring to FIG. 1, a semiconductor device 100 includes a memory module 8, a memory module interface circuit 20, a CPU (Central Processing Unit) 22, a RAM (Random Access Memory) 24, and a DMA controller (DMAC: Dynamic Memory Access). Controller) 26 and the data bus 10. The memory module interface circuit 20, the CPU 22, the RAM 24, and the DMA controller 26 are connected to each other via the data bus 10. Further, the memory module 8 is connected to the data bus 10 via the memory module interface circuit 20.

  The CPU 22 is an arithmetic processing unit that receives data read from the memory module 8 or data read from the RAM 24 and executes arithmetic processing (logic arithmetic). Then, the CPU 22 stores the calculation result obtained by the calculation process in the memory module 8 or the RAM 24.

  The RAM 24 is a storage area for storing temporary data associated with the arithmetic processing of the CPU 22. That is, the RAM 24 is a volatile storage element.

  The DMA controller 26 is a circuit for controlling data transfer performed with the RAM 24 via the data bus 10. That is, the DMA controller 26 enables data transfer between the memory module 8 and the RAM 24 without using the CPU 22.

  The memory module 8 stores input data (not shown) via the memory module interface circuit 20 in association with an address, and reads the data stored at the selected address, so that the memory module interface circuit 20 Output to. As an example, in the present embodiment, the memory module 8 outputs data in units of 64 bits (Data 0 to Data 63). More specifically, the memory module 8 includes a control unit 1, a plurality of memory arrays 2, a plurality of sense amplifiers 4 corresponding to the plurality of memory arrays 2, and an error correction circuit 6.

  Memory module 8 is configured to be able to select a synchronous mode in which a read operation is performed in synchronization with clock signal CLK and an asynchronous mode in which a read operation is performed asynchronously with the clock signal. The memory module 8 operates in any mode in accordance with the mode selection signal MOD given from the CPU 22.

  The control unit 1 receives control signals (such as a mode selection signal MOD and a clock signal CLK) from the memory module interface circuit 20 and the CPU 22, and controls the operations of the memory array 2, the sense amplifier 4, and the error correction circuit 6.

  Each of the memory arrays 2 has a plurality of memory cells arranged in a matrix, and performs data read and data write operations in accordance with an address signal or the like given from the control unit 1. In particular, the memory array 2 is a memory cell capable of storing data in a nonvolatile manner. As an example, each memory cell is configured by a flash memory. Alternatively, each memory cell may be configured by MRAM (Magnetic Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or the like.

  In this embodiment, in order to improve the reliability of data reading and writing, the memory module 8 is provided with 64 memory arrays 2 used as data areas and 7 memory arrays 2 used as parity areas. It is done.

  Then, memory data is transferred from the selected memory cell in each of the memory arrays 2 via the corresponding complementary global bit line pairs GBLP0, / GBLP0 to GBLP6, / GBLP6, or GBL0, / GBL0 to GBL63, / GBL63. A corresponding read signal is output to the corresponding sense amplifier 4.

  Each of sense amplifiers 4 reads stored data of a corresponding memory cell based on a read signal output from corresponding memory array 2. Each of the sense amplifiers 4 outputs the read storage data to the error correction circuit 6 as data outputs DoutP0 to DoutP6 and Dout0 to Dout63.

  The error correction circuit 6 generates a parity check code from the data outputs Dout0 to Dout63 output from each of the sense amplifiers 4, and compares the generated parity check code with the data outputs DoutP0 to DoutP6 to determine whether there is a data error. Check and correct data errors. Then, the error correction circuit 6 outputs the read data Data0 to Data63 after performing the error check and error correction to the memory module interface circuit 20.

  The memory module interface circuit 20 includes a data capture clock generation unit 18, a data buffer 12, a register 14, and a data bus driver circuit 16.

  The data capture clock generation unit 18 receives the CPU clock signal CPU_CLK that defines the operation timing of the CPU 22 and controls the operation timing of the data buffer 12 and the register 14. Further, the data capture clock generation unit 18 generates a clock signal CLK for operating the memory module 8 in the synchronous mode from the CPU clock signal CPU_CLK, and supplies the clock signal CLK to the memory module 8.

  The data buffer 12 temporarily stores the read data Data0 to Data63 continuously output from the memory module 8, and outputs the stored read data to the register 14 in accordance with a FIFO (First In First Out) system.

  The register 14 outputs the read data output from the data buffer 12 to the data bus driver circuit 16 by changing the data arrangement in order to match the data width (number of bits) of the data bus 10.

  The data bus driver circuit 16 amplifies and outputs a read data signal in consideration of the input impedance of the CPU 22 and RAM 14 in order to propagate the read data on the data bus 10.

  In the present embodiment, a data reading operation from the memory module 8 will be described in detail. In the following description, complementary global bit line pairs are collectively referred to by using the symbols “GBL, / GBL”, and the corresponding global bit lines are collectively referred to by using the symbols “GBL” and “/ GBL”, respectively. To do. Further, the data output output from the sense amplifier 4 is generically referred to by using the symbol “Dout”.

FIG. 2 is a more detailed configuration diagram showing the main part of the memory module 8.
Referring to FIG. 2, each of memory arrays 2 is electrically connected to sense amplifier 4 through global bit line pair GBL, / GBL. Each of the memory arrays 2 includes bit lines BL1 to BLn, word lines WL1 to WLm, a plurality (n × m) of memory cells MC, column selectors COL to COLn, a row decoder 30, and a column. Decoder 32, reference memory cell 34, precharge transistors 36a and 36b, and discharge transistors 38a and 38b are included.

  Bit lines BL1 to BLn are arranged in alignment along the row direction, and word lines WL1 to WLm are arranged in alignment in the column direction. Memory cells MC are arranged in association with the intersections of the bit lines BL1 to BLn and the word lines WL1 to WLm. That is, the memory cells MC are arranged in an n × m matrix.

  Each of memory cells MC is connected between corresponding bit lines BL1 to BLn and a reference potential, and its gate is connected to corresponding word lines WL1 to WLm. The memory cell MC changes the threshold voltage generated between the output electrodes in accordance with the stored data. As an example, in the present embodiment, each of the memory cells MC stores binary data in association with a high threshold voltage and a low threshold voltage. In the following description, when two values of a high voltage state and a low voltage state can be taken, they are represented as “H” level (high voltage state) and “L” level (low voltage state).

  Each of the column selectors COL to COLn is inserted between the corresponding bit line BL1 to BLn and the global bit line GBL, and in response to a gate signal (not shown) applied from the column decoder 32 to the gate. The bit lines BL1 to BLn and the global bit line GBL are electrically connected or disconnected. That is, among the bit lines BL1 to BLn, the bit line corresponding to the activated column selector is electrically connected to the global bit line GBL.

  The row decoder 30 is electrically connected to the word lines WL1 to WLm, and selects the word line corresponding to the selected memory cell MC in accordance with the address signal ADD and the control signal CTRL supplied from the control unit 1 (FIG. 1). Activate. Then, the memory cell MC corresponding to the activated word line is activated, and a threshold voltage corresponding to the stored data is generated between its output electrodes.

  The column decoder 32 activates the column selector corresponding to the selected memory cell MC according to the address signal ADD and the control signal CTRL supplied from the control unit 1 (FIG. 1). Then, the memory cell MC connected to the bit line corresponding to the activated column selector is connected to the global bit line GBL.

  Therefore, the memory cell MC arranged at the intersection of the activated word line and the bit line corresponding to the activated column selector is connected to the global bit line GBL.

  Reference memory cell 34 is electrically connected to global bit line / GBL, and is formed to generate a threshold voltage intermediate between “H” level and “L” level generated by memory cell MC.

  Precharge transistors 36a and 36b are connected to global bit lines GBL and / GBL, respectively. Precharge transistors 36a and 36b provide precharge potential VPP to global bit lines GBL and / GBL, respectively, in response to precharge command PRC applied to the gates.

  Discharge transistors 38a and 38b are connected to global bit lines GBL and / GBL, respectively. The discharge transistors 38a and 38b discharge (discharge) the global bit lines GBL and / GBL to the reference potential in response to a discharge command DIS given to the gates.

  The sense amplifier 4 compares the signal generated in the selected memory cell MC with the signal generated in the reference memory cell 34 to generate and output a data output Dout. In this specification, “read signal” means a complementary signal composed of a signal generated in the selected memory cell MC and a signal generated in the reference memory cell 34.

  As described above, the memory module 8 is configured to operate in both the synchronous mode and the asynchronous mode. Therefore, the sense amplifier 4 performs a sensing operation corresponding to the selected read mode.

  In summary, in the synchronous mode, in synchronization with the clock signal CLK, the memory cell MC is selected, the global bit line GBL (and the bit line BL) is precharged, and the sense operation of the signal generated between the memory cell MC and the reference memory cell 34. In addition, the global bit line GBL (and the bit line BL) is sequentially discharged. Therefore, the sense amplifier 4 needs to determine the data value stored in the memory cell MC at a predetermined timing.

  On the other hand, in the asynchronous mode, regardless of the clock signal CLK, it is stored in the memory cell MC when the address signal ADD given from the outside of the memory module 8 is newly given (or when the address signal ADD is changed). It is necessary to determine the data value. In other words, in the asynchronous mode, the sense amplifier needs to be configured to be able to perform a sense operation at any timing.

  As described above, different sensing operations are required in each of the synchronous mode and the asynchronous mode. Therefore, in the conventional SoC, two types of sense amplifiers for executing the sensing operation in each mode are provided independently of each other.

FIG. 3 is a schematic configuration diagram showing an example of a sense amplifier in a conventional SoC.
Referring to FIG. 3, the conventional SoC includes an amplifier unit 40, a synchronous mode sense amplifier 42, and an asynchronous mode sense amplifier 46.

  The amplifier unit 40 is connected to the global bit line pair GBL, / GBL, and amplifies a read signal appearing on the global bit line pair GBL, / GBL. The amplifier unit 40 outputs the amplified read signal to the synchronous mode sense amplifier 42 and the asynchronous mode sense amplifier 46.

  The synchronous mode sense amplifier 42 includes a cross-coupled latch circuit. When receiving the amplifier enable signal AMP_Ena, the synchronous mode sense amplifier 42 holds and outputs the synchronous read data signal determined based on the potential relationship of the read signal at that time.

  On the other hand, the asynchronous mode sense amplifier 46 includes a current mirror circuit. Then, the asynchronous mode sense amplifier 46 continuously outputs an asynchronous read data signal obtained by differentially amplifying the read signal applied from the amplifier section 40 during a period when the asynchronous enable signal ASY_Ena is applied.

  Specifically, synchronous mode sense amplifier 42 includes N channel MOS transistors Q14, Q16, Q18, Q20a, Q20b, Q24a, Q24b, P channel MOS transistors Q10, Q12, and a driver circuit 44.

  P-channel MOS transistors Q10 and Q12 and N-channel MOS transistors Q14 and Q16 constitute a cross-coupled latch circuit. The latch circuit is connected between the power supply potential VDD and the reference potential, and is driven by receiving the power supply potential VDD.

  N-channel MOS transistor Q18 is connected between connection node N18 and a reference potential, and an amplifier enable signal AMP_Ena is applied to its gate. That is, N channel MOS transistor Q18 intermittently supplies power supply potential VDD to the latch circuit. When amplifier enable signal AMP_Ena is driven to the “H” level, N channel MOS transistor Q18 is activated, and a drive current is supplied from power supply potential VDD to the latch circuit.

  N channel MOS transistors Q20a and Q24a are connected in series between connection node N10 and the reference potential. An input enable signal INP_Ena is applied to the gate of N channel MOS transistor Q20a, and one of the read signals output from amplifier section 40 is applied to the gate of N channel MOS transistor Q24a.

  Similarly, N channel MOS transistors Q20b and Q24b are connected in series between connection node N20 and the reference potential. The input enable signal INP_Ena is applied to the gate of the N channel MOS transistor Q20b, and the other read signal output from the amplifier unit 40 is applied to the gate of the N channel MOS transistor Q24b.

  When input enable signal INP_Ena is driven to "H" level, N channel MOS transistors Q20a and Q20b are activated to generate predetermined potentials at connection nodes N10 and N20, respectively. Here, the threshold voltages generated in N channel MOS transistors Q24a and Q24b are determined according to the read signal transmitted through global bit line pair GBL, / GBL, respectively, so that connection nodes N10 and N12 are read out respectively. A potential corresponding to the signal is applied.

  Then, the state (active state or inactive state) of P channel MOS transistor Q10 or Q12 is determined according to the magnitude relationship between the potential of connection node N10 and the potential of connection node N12. Furthermore, when amplifier enable signal AMP_Ena is applied, power supply potential VDD (“H” level) or reference potential (“L” level) appears at connection node N20 in accordance with the state of P channel MOS transistor Q12. Further, the driver enable signal DRV_Ena is supplied to the driver circuit 44, whereby the potential appearing at the connection node N20 is amplified and output as the data output Dout.

  Asynchronous mode sense amplifier 46 includes P-channel MOS transistors Q28, Q30, Q32, N-channel MOS transistors Q34a, Q34b, Q38, and a driver circuit 48.

  P channel MOS transistors Q28 and Q30 and N channel MOS transistors Q34a and Q34b form a current mirror circuit. The current mirror circuit is connected between the power supply potential VDD and the reference potential, and is driven by receiving the power supply potential VDD.

  N-channel MOS transistor Q38 is connected between connection node N28 and a reference potential, and an asynchronous enable signal ASY_Ena is applied to its gate. That is, N channel MOS transistor Q38 intermittently supplies power supply potential VDD to the current mirror circuit. When asynchronous enable signal ASY_Ena is driven to “H” level, N channel MOS transistor Q38 is activated, and a drive current is supplied from power supply potential VDD to the current mirror circuit.

  In this current mirror circuit, a current corresponding to the difference between the current flowing through N channel MOS transistor Q34a and the current flowing through N channel MOS transistor Q34b is sent from connection node N26.

  Here, N channel MOS transistors Q34a and Q34b are formed to have the same size (ratio between channel length and channel width). Gate currents corresponding to read signals appearing on global bit lines GBL and / GBL are applied to the gates of N channel MOS transistors Q34a and Q34b, respectively. Therefore, a through current corresponding to a read signal flowing in global bit lines GBL and / GBL flows through N channel MOS transistors Q34a and Q34b, respectively, and a read signal appearing in global bit lines GBL and / GBL flows from connection node N26. The differentially amplified current is sent to the driver circuit 48.

  The driver circuit 48 is configured to be activated in response to the asynchronous enable signal ASY_Ena. Since the asynchronous enable signal ASY_Ena is held at the “H” level during the selection of the asynchronous mode, the driver circuit 48 differentially amplifies the current output corresponding to the current difference between the read signals, and outputs the data output Dout. Is output continuously.

  As described above, in the conventional SoC, since two types of sense amplifiers corresponding to the reading mode are provided, the electrical load viewed from the amplifier unit 40 is large, and the power consumption in the amplifier unit 40 is relatively large. . Further, with the formation of the synchronous mode sense amplifier 42 and the asynchronous mode sense amplifier 46, the overall circuit configuration has become relatively complicated.

  Therefore, the present embodiment provides a sense amplifier that reduces power consumption and simplifies the circuit configuration as compared with the conventional SoC shown in FIG.

FIG. 4 is a schematic configuration diagram of the sense amplifier 4 according to the present embodiment.
Referring to FIG. 4, the sense amplifier 4 according to the present embodiment includes data lines DL and / DL, an input circuit 50, a synchronous mode sense circuit 54, an asynchronous mode sense circuit 52, and a first gate circuit 62. And a second gate circuit 64 and a third gate circuit 56. In the following description, complementary data lines DL and / DL are also collectively referred to as data line pairs DL and / DL.

  When the operation of the sense amplifier 4 in the synchronous mode is outlined, the row decoder 30 (FIG. 2) and the column decoder 32 (FIG. 2) select the memory cell MC in synchronization with the clock signal CLK. In conjunction with the selection of the memory cell MC, the control unit 1 (FIG. 1) sequentially drives the amplifier enable signal AMP_Ena, the input enable signal INP_Ena, and the driver enable signal DRV_Ena to the “H” level. At this time, the asynchronous enable signal ASY_Ena is held at the “L” level. As a result, the asynchronous mode sense circuit 52 is electrically disconnected from the data line pair DL, / DL.

  Then, at the time when the input enable signal INP_Ena is driven to the “H” level, the synchronous mode sense circuit 54 sets the data signal to “L” based on the potential relationship of the read signal appearing on the data line pair DL, / DL. The level or “H” level is determined. Thereafter, when the amplifier enable signal AMP_Ena and the driver enable signal DRV_Ena are driven to the “H” level, the synchronization mode sense circuit 54 outputs the determined data signal as the data output Dout. At this time, since no data output Dout is performed from the asynchronous mode sense circuit 52, the data output Dout from the synchronous mode sense circuit 54 is output to the error correction circuit 6 (FIG. 1).

  On the other hand, the operation of the sense amplifier 4 in the asynchronous mode is outlined. The row decoder 30 (FIG. 2) and the column decoder 32 (FIG. 2) select the memory cell MC regardless of the clock signal CLK. Control unit 1 (FIG. 1) holds asynchronous enable signal ASY_Ena at the “H” level. As a result, the asynchronous mode sense circuit 52 is electrically connected to the data line pair DL, / DL, and the synchronous mode sense circuit 54 is inactivated by being cut off from the power supply potential VDD. Note that the amplifier enable signal AMP_Ena and the driver enable signal DRV_Ena are both held at the “L” level, and the input enable signal INP_Ena is held at the “H” level.

  Then, the asynchronous mode sense circuit 52 is activated, differentially amplifies the read signal appearing on the data line pair DL, / DL, and outputs it as the data output Dout. At this time, since no data output Dout is output from the synchronous mode sense circuit 54, the data output Dout from the asynchronous mode sense circuit 52 is output to the error correction circuit 6 (FIG. 1).

Hereinafter, each part of the sense amplifier 4 will be described in detail.
Input circuit 50 provides a complementary read signal corresponding to the stored data of selected memory cell MC to data line pair DL, / DL. More specifically, input circuit 50 includes complementary N-channel MOS transistors Q72a and Q72b and amplifier unit 60.

  Amplifier section 60 is connected to global bit line pair GBL, / GBL, and amplifies a read signal appearing on global bit line pair GBL, / GBL. Amplifier unit 60 outputs the amplified complementary read signals to N channel MOS transistors Q72a and Q72b, respectively.

  N channel MOS transistors Q72a and Q72b are respectively inserted between data lines DL and / DL and a reference potential, and corresponding outputs of amplifier section 60 are applied to the gates thereof. Here, N channel MOS transistors Q72a and Q72b are formed to have the same size (ratio of channel length to channel width). Therefore, a through current corresponding to a read signal flowing in global bit lines GBL and / GBL flows through N channel MOS transistors Q72a and Q72b, respectively. Therefore, a read signal corresponding to the read signal appearing on global bit line pair GBL, / GBL is applied to data line pair DL, / DL.

  The read signal appearing on data line pair DL, / DL is determined depending on the threshold voltage of complementary N channel MOS transistors Q72a, Q72b connected between data line pair DL, / DL and the reference potential. Is done. Therefore, in the N-channel MOS transistor corresponding to the “H” level read signal, since the “H” level signal is applied to the gate thereof, it is activated and becomes conductive. Therefore, a read signal in which “H” level and “L” level are inverted with respect to the read signal appearing on global bit line pair GBL, / GBL appears on data line pair DL, / DL. .

  Synchronous mode sense circuit 54 is connected to data line pair DL, / DL, and reads stored data from selected memory cell MC based on a read signal appearing on data line pair DL, / DL when synchronous mode is selected. put out. More specifically, synchronous mode sense circuit 54 includes P-channel MOS transistors Q60, Q62, N-channel MOS transistors Q64, Q66, Q68, and driver circuit 58.

  P-channel MOS transistors Q60 and Q62 and N-channel MOS transistors Q64 and Q66 constitute a cross-couple type latch circuit. That is, between connection node N64 and connection node N68, P channel MOS transistor Q60 and N channel MOS transistor Q64 are connected in series, and P channel MOS transistor Q62 and N channel MOS transistor Q66 are connected in series. Connected.

  The gate of P channel MOS transistor Q60 and the gate of N channel MOS transistor Q64 are connected in common with a connection node N62 which is a connection point between P channel MOS transistor Q62 and N channel MOS transistor Q66.

  Similarly, the gate of P channel MOS transistor Q62 and the gate of N channel MOS transistor Q66 are commonly connected to connection node N60 which is a connection point between P channel MOS transistor Q60 and N channel MOS transistor Q64.

  The synchronous mode sense circuit 54 is supplied with the power supply potential VDD from the first gate circuit 62 connected to the connection node N64 as its drive power supply. N channel MOS transistor Q68 is connected between connection node N68 and a reference potential, and an amplifier enable signal AMP_Ena is applied to the gate thereof.

  When the amplifier enable signal AMP_Ena is driven to the “H” level during the period in which the power supply potential VDD is supplied from the first gate circuit 62, the synchronous mode sense circuit 54 is activated. Then, the synchronous mode sense circuit 54 holds and outputs the synchronous read data signal determined based on the potential relationship of the read signal appearing on the data line pair DL, / DL at the time point to the data line pair DL, / DL.

  Here, driver circuit 58 is connected to data line / DL at connection node N72, and receives a synchronous read data signal output to data line / DL. Then, the driver circuit 58 amplifies the synchronous read data signal and outputs it as a data output Dout to the error correction circuit 6 (FIG. 1).

  Hereinafter, a more detailed operation in the synchronization mode sense circuit 54 will be described. As described above, the read signals appearing on data line pair DL, / DL are complementary to each other. Therefore, the potential of connection node N70 (and connection node N60) of data line DL and the potential of connection node N72 (and connection node N62) of data line / DL do not match each other, and any of the connection nodes Is in a higher potential state.

  If data line DL, that is, connection node N70 is in a higher potential state, a negative voltage corresponding to the potential difference between connection node N72 and connection node N70 is applied between the gate and source of P channel MOS transistor Q60. Is applied. On the other hand, a positive voltage corresponding to the potential difference between connection node N70 and connection node N72 is applied between the gate and source of P channel MOS transistor Q62. Therefore, P channel MOS transistor Q60 is activated to be in a conductive state, while P channel MOS transistor Q62 is maintained in a nonconductive state. When P channel MOS transistor Q60 is rendered conductive, a potential substantially matching power supply potential VDD appears at connection node N60. Then, N channel MOS transistor Q66 is activated and becomes conductive, so that a potential substantially matching the reference potential appears at connection node N62.

  As a result of such an operation, the data line DL is supplied with a potential that substantially matches the power supply potential VDD (“H” level), and the data line / DL substantially matches the reference potential (“L” level). Potential to be applied.

  On the other hand, if data line / DL, that is, connection node N72 is in a higher potential state, a negative voltage corresponding to the potential difference between connection node N70 and connection node N72 is applied between the gate and source of P channel MOS transistor Q62. Is applied. On the other hand, a positive voltage corresponding to the potential difference between connection node N72 and connection node N70 is applied between the gate and source of P channel MOS transistor Q60. Therefore, P channel MOS transistor Q62 is activated to be in a conductive state, while P channel MOS transistor Q60 is maintained in a nonconductive state. When P channel MOS transistor Q62 is rendered conductive, a potential substantially matching power supply potential VDD appears at connection node N62. Then, N channel MOS transistor Q64 is activated and becomes conductive, so that a potential substantially matching the reference potential appears at connection node N60.

  As a result of such an operation, the data line / DL is supplied with a potential that substantially matches the power supply potential VDD (“H” level), and the data line DL substantially matches the reference potential (“L” level). Potential to be applied.

  By the sensing operation as described above, the synchronous mode sense circuit 54 outputs a complementary synchronous read data signal to the data line pair DL, / DL. Further, the driver circuit 58 does not output the transient synchronous read data signal until the potential level to be output is determined as the data output Dout, at the timing when the amplifier enable signal AMP_Ena is given to the synchronous mode sense circuit 54. Configured to be delayed and activated.

  Asynchronous mode sense circuit 52 is connected to data line pair DL and / DL, and when asynchronous mode is selected, asynchronous read data signal obtained by differentially amplifying the read signal appearing on data line pair DL and / DL is continuously used as data output Dout. Output. More specifically, asynchronous mode sense circuit 52 includes P channel MOS transistors Q50, Q52, Q54 and a driver circuit 66.

  P channel MOS transistors Q50 and Q52 form a current mirror circuit. That is, P channel MOS transistor Q50 is connected between power supply potential VDD and data line DL. P channel MOS transistor Q52 is connected between power supply potential VDD and data line / DL. The gates of P channel MOS transistors Q50 and Q52 are connected in common, and further connected to the source of P channel MOS transistor Q50.

  When the asynchronous mode sense circuit 52 and the data line pair DL, / DL are electrically connected by the second gate circuit 64, a through current flows from the power supply potential VDD to the reference potential via the data lines DL and / DL, respectively. An electric current is generated. Then, the current mirror circuit of the asynchronous mode sense circuit 52 differentially amplifies the through current flowing through the data line DL and the through current flowing through the data line / DL, and sends it out from the connection node N56.

  Here, the through currents flowing through the data lines DL and / DL respectively correspond to the read signals flowing through the global bit lines GBL and / GBL, so that the differential amplification current sent from the connection node N56 is the selected memory cell. This indicates the data stored in the MC.

  The driver circuit 66 is arranged at the output stage of the asynchronous mode sense circuit 52, amplifies the differential amplification current sent from the connection node N56, and outputs it as a data output Dout to the error correction circuit 6 (FIG. 1). Further, the driver circuit 66 is activated in response to an asynchronous enable signal ASY_Ena for instructing activation of the asynchronous mode sense circuit 52.

  P-channel MOS transistor Q54 is connected in parallel with P-channel MOS transistor Q52, and an asynchronous enable signal ASY_Ena is applied to its gate. This P-channel MOS transistor Q54 is connected so that the connection node N56 does not become a floating potential during the period when the asynchronous mode sense circuit 52 is inactive, that is, during the period when the asynchronous enable signal ASY_Ena is held at the “L” level. Node N56 is held at power supply potential VDD.

  The first gate circuit 62 is configured to be capable of intermittently supplying the power supply potential VDD for driving the synchronous mode sense circuit 54 in response to the asynchronous enable signal ASY_Ena. Specifically, the first gate circuit 62 includes a P-channel MOS transistor Q58 connected between the connection node N64 of the synchronous mode sense circuit 54 and the power supply potential VDD. Asynchronous enable signal ASY_Ena is applied to the gate of P channel MOS transistor Q58.

  Therefore, when the asynchronous enable signal ASY_Ena is driven to the “H” level, the first gate circuit 62 cuts off the supply of the power supply potential VDD to the synchronous mode sense circuit 54. That is, since the asynchronous mode sense circuit 52 is activated during the period in which the asynchronous enable signal ASY_Ena is driven to the “H” level, the supply of the power supply potential VDD to the synchronous mode sense circuit 54 is cut off, which is unnecessary. To reduce power consumption.

  The second gate circuit 64 is inserted between the asynchronous mode sense circuit 52 and the data line pair DL, / DL, and in response to the asynchronous enable signal ASY_Ena, the asynchronous mode sense circuit 52 and the data line pair DL, / DL. Electrically disconnects from DL. Specifically, the second gate circuit 64 includes an N channel MOS transistor Q56a interposed between the data line DL and the connection node N54 of the asynchronous mode sense circuit 52, and the data line / DL and the asynchronous mode sense circuit. An N channel MOS transistor Q56b interposed between 52 connection nodes N56. Asynchronous enable signal ASY_Ena is commonly applied to the gates of P channel MOS transistors Q56a and Q56b.

  Therefore, when the asynchronous enable signal ASY_Ena is at “L” level, the second gate circuit 64 maintains the asynchronous mode sense circuit 52 and the data line pair DL, / DL in an electrically disconnected state. When the asynchronous enable signal ASY_Ena is driven to the “H” level, the second gate circuit 64 electrically connects the asynchronous mode sense circuit 52 and the data line pair DL, / DL. As described above, the second gate circuit 64 reduces the load elements connected to the data line pair DL, / DL during the selection of the synchronous mode, and reduces the electrical load viewed from the input circuit 50, which is unnecessary. Reduce power consumption.

  The third gate circuit 56 is inserted between the input circuit 50 and the synchronization mode sense circuit 54, and electrically connects the input circuit 50 and the synchronization mode sense circuit 54 in response to the input enable signal INP_Ena. . Specifically, the third gate circuit 56 includes an N channel MOS transistor Q70a interposed between the N channel MOS transistor Q72a of the input circuit 50 and the data line DL, and an N channel MOS transistor Q72b of the input circuit 50 and the data. N channel MOS transistor Q70b interposed between line / DL. Input enable signal INP_Ena is commonly applied to the gates of N channel MOS transistors Q70a and Q70b.

  The third gate circuit 56 applies the read signal output from the input circuit 50 to the data line pair DL, / DL during the period in which the synchronous mode sense circuit 54 and the asynchronous mode sense circuit 52 are activated. .

  Hereinafter, a data read operation from the memory cell MC in the synchronous mode and the asynchronous mode will be described using a time chart.

  FIG. 5 is a diagram showing the time waveforms of the respective parts relating to the data reading in the synchronous mode. FIG. 5 shows, as an example, a case where data is read from memory cell MC at address <AAA> and then data is read from memory cell MC at address <BBB> in the synchronous mode.

  FIG. 5A shows temporal changes in the contents of the address signal ADD supplied to the memory module 8. FIG. 5B shows a time waveform of the clock signal CLK applied to the memory module 8. FIG. 5C and FIG. 5E show time waveforms of the word line WL and the column selector COL corresponding to the address <AAA>, respectively. FIG. 5D and FIG. 5F show time waveforms of the word line WL and the column selector COL corresponding to the address <BBB>, respectively. FIG. 5G shows a time waveform of the read signal appearing on the global bit line pair GBL, / GBL. FIG. 5 (h) shows a time waveform of the read signal output from the amplifier unit 60. FIG. 5I shows a time waveform of the input enable signal INP_Ena. FIG. 5J shows the time waveform of the amplifier enable signal AMP_Ena. FIG. 5K shows a time waveform of the synchronous read data signal output from the synchronous mode sense circuit 54. FIG. 5L shows a time waveform of the driver enable signal DRV_Ena. FIG. 5 (m) shows a time waveform of the data output Dout output from the synchronous mode sense circuit 54. FIG.

  In data reading in the synchronous mode, the asynchronous enable signal ASY_Ena is fixed to the “L” level.

  Referring to FIG. 5B, clock signal CLK applied to memory module 8 changes in the rising direction at times t1 and t9. In the present embodiment, the read operation is executed with the rising edge of the clock signal CLK as the reference timing. That is, the input address signal ADD becomes valid at times t1 and t9. When address <AAA> becomes valid at time t1, as shown in FIG. 5C, at time t2, word line WL <AAA> corresponding to address <AAA> is driven to the “H” level. Subsequently, as shown in FIG. 5E, at the time t3, the column selector COL <AAA> is driven to the “H” level. At this time, the memory cell MC corresponding to the address <AAA> is electrically connected to the global bit line GBL.

  Thereafter, precharge transistors 36a and 36b (FIG. 2) are driven to "H" level, and precharge potential VPP is applied to memory cell MC and reference memory cell 34 corresponding to address <AAA>. Then, as shown in FIG. 5G, the potential of the global bit line pair GBL, / GBL rises to the precharge potential VPP (precharge period).

  In addition, in order to perform a stable sensing operation in the synchronous mode sense amplifier 42, the data line pair DL, / DL is precharged at time t4 by a precharge transistor (not shown). Then, as shown in FIG. 5 (k), the potentials of data lines DL and / DL both rise to the “H” level (output precharge period).

  As shown in FIG. 5G, after precharging the memory cell MC and the reference memory cell 34 corresponding to the address <AAA>, the global bit line pair GBL, / A predetermined potential difference is generated in the read signal appearing in GBL. Then, at time t5, the amplifier unit 60 is activated. Then, as shown in FIG. 5H, the amplifier unit 60 amplifies and outputs the read signal appearing on the global bit line pair GBL, / GBL. Subsequently, as shown in FIG. 5I, at time t6, the input enable signal INP_Ena is driven to the “H” level. Then, a read signal obtained by inverting the output of amplifier section 60 shown in FIG. 5 (h) appears on data line pair DL, / DL, and a latch circuit of synchronous mode sense circuit 54 is provided in accordance with this read signal. The state (conducting or non-conducting) of each transistor to be configured is determined. Further, as shown in FIG. 5J, the amplifier enable signal AMP_Ena is driven to the “H” level at time t7. Then, the synchronous mode sense circuit 54 is activated and holds and outputs the determined synchronous read data signal.

  As shown in FIG. 5L, the driver enable signal DRV_Ena is driven to the “H” level at time t8 with a delay from the start of holding and outputting the synchronous read data signal from the synchronous mode sense circuit 54. Then, as shown in FIG. 5 (m), the synchronous read data signal amplified by the driver circuit 58 is output as the data output Dout.

  When data output Dout is completed, discharge transistors 38a and 38b (FIG. 2) are driven to "H" level, and a reference voltage is applied to memory cell MC and reference memory cell 34 corresponding to address <AAA> to perform discharge. It is. Then, as shown in FIG. 5G, the potentials of the global bit line pair GBL, / GBL both drop to the reference potential (discharge period).

  Thereafter, at time t9 which is the next rising timing of the clock signal CLK, the next address <BBB> becomes valid. And the operation | movement similar to the above-mentioned time t1-time t9 is repeated. Since the operation is the same, detailed description will not be repeated.

  FIG. 6 is a diagram illustrating time waveforms of respective units related to data reading in the asynchronous mode. FIG. 6 shows, as an example, a case where data is read from memory cell MC at address <AAA> and then data is read from memory cell MC at address <BBB> in the asynchronous mode.

  The time waveforms shown in FIGS. 6A to 6M correspond to the time waveforms shown in FIGS. 5A to 5M except for FIG. 6K. FIG. 6K shows a time waveform of the synchronous read data signal output from the asynchronous mode sense circuit 52.

  In data reading in the asynchronous mode, the asynchronous enable signal ASY_Ena is fixed to the “H” level. Further, as shown in FIG. 6 (i), the input enable signal INP_Ena is fixed to the “H” level, and as shown in FIG. 6 (j), the amplifier enable signal AMP_Ena is fixed to the “L” level. As shown in (l), the driver enable signal DRV_Ena is fixed at the “L” level.

  As shown in FIG. 6B, the clock signal CLK may be given to the memory module 8, but in the asynchronous mode, the operation of each unit is executed regardless of the clock signal CLK.

  As shown in FIG. 6A, it is assumed that the value of the address signal ADD is changed to the address <AAA> at time t11. Then, as shown in FIG. 6E, the column selector COL <AAA> is driven to the “H” level at time t12. Subsequently, as shown in FIG. 6C, at time t13, the word line WL <AAA> corresponding to the address signal <AAA> is driven to the “H” level.

  Then, as shown in FIG. 6G, a read signal appears on the global bit line pair GBL, / GBL with a predetermined time constant in accordance with the data stored in the selected memory cell MC. In the asynchronous mode, global bit lines GBL and / GBL are not precharged.

  As shown in FIG. 6 (h), the output of the amplifier unit 60 also changes with time in accordance with the read signal on the global bit line pair GBL, / GBL. Then, the read signal appearing on the data line pair DL, / DL also changes. As a result, as shown in FIG. 6 (k), the output of the asynchronous mode sense circuit 52 that differentially amplifies the read signal appearing on the data line pair DL, / DL also changes over time. Then, as shown in FIG. 6 (m), the data output Dout is determined at time t14 when the output of the asynchronous mode sense circuit 52 is stabilized.

  After that, when the value of the address signal ADD is changed to the next address <BBB> at time t15 unrelated to the clock signal CLK, the same operation as the above-described time t11 to time t15 is repeated. Since the operation is the same, detailed description will not be repeated.

  In the present embodiment, the synchronous mode corresponds to the “first mode”, the asynchronous mode corresponds to the “second mode”, the data line pair DL, / DL corresponds to the “data line pair”, and the synchronous mode Sense circuit 54 corresponds to the “first sense circuit”, asynchronous mode sense circuit 52 corresponds to the “second sense circuit”, amplifier enable signal AMP_Ena corresponds to the “enable signal”, and the first gate The circuit 62 corresponds to the “first gate circuit”, the second gate circuit 64 corresponds to the “second gate circuit”, the input circuit 50 corresponds to the “input circuit”, and the amplifier unit 60 corresponds to the “amplifier unit”. The third gate circuit 56 corresponds to a “third gate circuit”, the driver circuit 58 corresponds to a “first driver circuit”, and the driver circuit 66 corresponds to a “second driver circuit”. To do.

  According to the embodiment of the present invention, input circuit 50 provides a read signal to data line pair DL, / DL to which synchronous mode sense circuit 54 and asynchronous mode sense circuit 52 are connected in common. Thereby, the wiring length can be reduced as compared with the conventional configuration including the synchronous mode sense amplifier 42 and the asynchronous mode sense amplifier 46. Therefore, the electric load viewed from the amplifier unit 60 is reduced, and power consumption can be reduced. Further, since the current capacity of the amplifier unit 60 itself can be reduced, the circuit area can also be reduced.

  Further, according to the embodiment of the present invention, the common input circuit 50 is provided for the synchronous mode sense circuit 54 and the asynchronous mode sense circuit 52. As a result, the circuit configuration can be further simplified as compared with the conventional configuration in which the circuit corresponding to the input circuit is provided in each of the synchronous mode sense amplifier 42 and the asynchronous mode sense amplifier 46.

  Furthermore, according to the embodiment of the present invention, in the period when the synchronous mode is selected, second gate circuit 64 electrically cuts off asynchronous mode sense circuit 52 and data line pair DL, / DL. As a result, the asynchronous mode sense circuit 52 can be disconnected from the data line pair DL, / DL during the selection of the synchronous mode that does not need to operate, so that the electrical load viewed from the amplifier unit 60 can be further reduced.

  Furthermore, according to the embodiment of the present invention, the first gate circuit 62 cuts off the supply of the power supply potential VDD to the synchronous mode sense circuit 54 during the period when the asynchronous mode is selected. As a result, it is possible to reduce the leakage current generated by applying the power supply potential VDD during the selection of the asynchronous mode that does not require the synchronous mode sense circuit 54 to be activated. Therefore, power consumption in the asynchronous mode can be suppressed.

[Modification]
In the present embodiment described above, by applying a read signal appearing on the global bit line pair GBL, / GBL to the gate of the complementary transistor connected between the complementary data line pair DL, / DL and the reference potential, In other words, the configuration in which the read signal is indirectly applied to the data line pair DL, / DL has been described. Alternatively, the read signal appearing on the global bit line pair GBL, / GBL may be directly applied to the data line pair DL, / DL.

FIG. 7 is a schematic configuration diagram of a sense amplifier 4 # according to a modification of the present embodiment.
Referring to FIG. 7, a sense amplifier 4 # according to a modification of the present embodiment is obtained by arranging an input circuit 50 # in place of input circuit 50 in sense amplifier 4 according to the present embodiment shown in FIG.

  Input circuit 50 # is configured of amplifier section 60 #. Amplifier unit 60 # is connected to global bit line pair GBL, / GBL, and amplifies a read signal appearing on global bit line pair GBL, / GBL. Amplifying unit 60 # applies the amplified complementary read signal to data line pair DL and / DL, respectively.

  In other words, amplifier unit 60 # only amplifies the read signal appearing on global bit line pair GBL, / GBL and provides the amplified signal to data line pair DL, / DL. Therefore, unlike the above-described embodiment, the read signal obtained by inverting the read signal appearing on the global bit line pair GBL, / GBL does not appear on the data line pair DL, / DL, and the global bit line pair GBL, / GBL The level of the read signal appearing at (H level or “L” level) matches the level of the read signal appearing on the data line pair DL, / DL. Others are the same as in FIG. 4, and thus detailed description will not be repeated.

  Further, since the data read operation is the same as that of the present embodiment described above, detailed description will not be repeated.

  According to the modification of the embodiment of the present invention, the effects of the above-described embodiment of the present invention can be exhibited, and the number of transistors constituting the input circuit can be reduced. Thereby, the circuit area required for the configuration of the sense amplifier can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a schematic block diagram of the semiconductor device according to this embodiment. It is a more detailed block diagram showing the main part of the memory module. It is a schematic block diagram which shows an example of the sense amplifier in the conventional SoC. It is a schematic block diagram of the sense amplifier according to this embodiment. It is a figure which shows the time waveform of each part concerning the data reading of synchronous mode. It is a figure which shows the time waveform of each part concerning data reading of asynchronous mode. It is a schematic block diagram of the sense amplifier according to the modification of this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Control part, 2 Memory array, 4, 4 # Sense amplifier, 6 Error correction circuit, 8 Memory module, 10 Data bus, 12 Data buffer, 14 Register, 16 Data bus driver circuit, 18 Data capture clock generation part, 20 Memory module interface circuit, 26 DMA controller, 30 row decoder, 32 column decoder, 34 reference memory cell, 36a, 36b precharge transistor, 38a, 38b discharge transistor, 40, 60, 60 # amplifier section, 42 synchronous mode sense amplifier , 44, 48 driver circuit, 46 asynchronous mode sense amplifier, 50, 50 # input circuit, 52 asynchronous mode sense circuit, 54 synchronous mode sense circuit, 56 third gate circuit, 58, 66 driver Circuit, 62 first gate circuit, 64 second gate circuit, 100 semiconductor device, ADD address signal, AMP_Ena amplifier enable signal, ASY_Ena asynchronous enable signal, BL bit line, CLK clock signal, COL column selector, CPU_CLK CPU clock signal, CTRL Control signal, DIS discharge command, DL, / DL data line pair, Dout data output, DRV_Ena driver enable signal, GBL, / GBL global bit line pair, INP_Ena input enable signal, MC memory cell, MOD mode selection signal, PRC precharge Command, Q10, Q12, Q14, Q16, Q18, Q20a, Q20b, Q24a, Q24b, Q28, Q30, Q32, Q34a, Q34b, Q38, Q 50, Q52, Q54, Q56a, Q56b, Q58, Q60, Q62, Q64, Q66, Q68, Q70a, Q70b Transistor, VDD power supply potential, VPP precharge potential, WL word line.

Claims (8)

A memory array having a plurality of memory cells arranged in a matrix;
A sense amplifier for reading data from the memory cell, and a semiconductor device comprising:
The semiconductor device is configured to be able to select a first mode in which a read operation is performed in synchronization with a clock signal and a second mode in which a read operation is performed asynchronously with the clock signal,
The sense amplifier is
A data line pair consisting of complementary data lines;
An input circuit for supplying a complementary read signal to the data line pair according to the stored data of the selected memory cell;
A first sense circuit connected to the data line pair for reading data when the first mode is selected;
A second sense circuit connected to the data line pair for reading data when the second mode is selected,
The first sense circuit, in response to an enable signal applied corresponding to the clock signal, outputs a first data signal determined based on a potential relationship of the read signal appearing on the data line pair at the time. Configured to output,
The second sense circuit is configured to output a second data signal obtained by differentially amplifying the read signal appearing on the data line pair,
The semiconductor device further includes:
A first gate circuit capable of interrupting a power supply potential for driving the first sense circuit;
A second gate circuit interposed between the second sense circuit and the data line pair and capable of electrically connecting and disconnecting the second sense circuit and the data line pair;
The first gate circuit cuts off the supply of the power supply potential to the first sense circuit when the second mode is selected;
The semiconductor device, wherein the second gate circuit electrically cuts off the second sense circuit and the data line pair when the second mode is not selected. The input circuit includes a complementary transistor interposed between one end of the data line pair and a reference potential,
2. The semiconductor device according to claim 1, wherein each of the complementary transistors is configured such that a corresponding read signal is applied to a gate.   The semiconductor device according to claim 2, wherein the input circuit further includes an amplifier unit for amplifying the complementary read signal and supplying the amplified read signal to the gate of the complementary transistor.   2. The semiconductor device according to claim 1, wherein the input circuit includes an amplifier unit for amplifying the complementary read signal and supplying the amplified read signal to the data line pair. The semiconductor device further includes a third gate circuit that is interposed between the input circuit and the data line pair and configured to be able to electrically connect and disconnect the input circuit and the data line pair.
5. The third gate circuit according to claim 1, wherein the third gate circuit electrically connects the input circuit and the data line pair during a period in which the first and second sense circuits are activated. 2. A semiconductor device according to item 1. The first sense circuit further includes a first driver circuit connected to one data line of the data line pair for outputting the first data signal to the outside,
6. The semiconductor device according to claim 1, wherein the first driver circuit is configured to be activated with a delay to a timing at which the enable signal is supplied to the first sense circuit. 6. apparatus. The second sense circuit further includes a second driver circuit disposed at an output stage of the second data signal,
The semiconductor device according to claim 1, wherein the second driver circuit is configured to be activated when the second mode is selected.   The semiconductor device according to claim 1, further comprising an arithmetic processing unit for executing arithmetic processing.

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