JP2014229338A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption of a semiconductor device.SOLUTION: A semiconductor device comprises: a transistor T1 having one end connected to a main IO line MIOB and the other end to which a power source potential VDD is supplied; a transistor T2 having one end connected to a main IO line MIOT and the other end to which the power source potential VDD is supplied; a transistor T3 having one end connected to the main IO line MIOB and the other end to which a ground potential VSS is supplied; a transistor T4 having one end connected to the main IO line MIOT and the other end to which the ground potential VSS is supplied; and a control circuit 55 controlling the on/off states of the transistors T1-T4 based on data to be supplied to a main IO line pair MIO. When turned on, the transistors T1, T2 supply a first potential lower than the power source potential VDD to the corresponding main IO line. When turned on, the transistors T3, T4 supply the ground potential VSS to the corresponding main IO line.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a write driver.

  In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a write driver is used for writing write data to a memory cell. The write driver controls the potential of the main IO line pair according to the write data, and each output terminal is connected to one (main IO line MIOT) and the other (main IO line MIOB) of the main IO line pair. 2 CMOS (Complementary Metal-Oxide-Semiconductor field-effect transistor). Hereinafter, the CMOS connected to the main IO line MIOT is referred to as “true side CMOS”, and the CMOS connected to the main IO line MIOB is referred to as “bar side CMOS”.

  In both the true side CMOS and the bar side CMOS, a P-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) (PMOS) and an N-channel MOSFET (NMOS) are connected to the power supply wiring to which the power supply potential VDD is supplied and to the ground. The power supply wiring to which the potential VSS is supplied is connected in series. When the main IO line MIOT is set high and the main IO line MIOB is set low, the true side CMOS PMOS and the bar side CMOS NMOS are turned on, and the other two transistors are turned off. On the other hand, when the main IO line MIOT is set to low and the main IO line MIOB is set to high, the true side CMOS NMOS and the bar side CMOS PMOS are turned on, and the other two transistors are turned off. By doing so, a potential difference of VDD-VSS is generated between the main IO line pair, and this potential difference is written into the memory cell through the sense amplifier and the bit line pair.

  FIG. 4 of Patent Document 1 discloses a semiconductor device having a write driver having the above structure.

JP 2009-13035 A

  By the way, when the transistor is turned on and off as described above, a current flows through the main IO line pair every time the transistor is turned on and off. The flow of current means that power is consumed. In recent years, the demand for lower power consumption in semiconductor devices has become stricter, and it is required to suppress power consumption due to such a current (charge / discharge current) as much as possible.

  Here, regarding the write operation of the DRAM, the potential difference between the main IO line pair does not necessarily need to be VDD-VSS, and write data can be sufficiently written even with a smaller value. Since the charge / discharge current of the main IO line pair as described above becomes larger as the fluctuation of the potential difference between the main IO line pairs becomes larger, the fact that the potential difference between the main IO line pairs is VDD-VSS reduces the power consumption. From the point of view, it is useless. Therefore, it is required to reduce the potential difference between the main IO line pairs.

  A semiconductor device according to an aspect of the present invention includes a first data line pair including first and second data lines, one end connected to the first data line, and the other end supplied with a first power supply potential. And a first transistor configured to supply a first potential lower than the first power supply potential to the first data line when turned on, and one end connected to the second data line A second transistor configured to supply the first power supply potential to the second data line when the first power supply potential is supplied to the other end and is turned on; A second power supply potential lower than the first potential is supplied to the other end, and the second power supply potential is supplied to the first data line when turned on. A third transistor configured and one end connected to the second data line; A fourth transistor configured to supply the second power supply potential to the second data line when the second power supply potential is supplied to the other end and is turned on; and And a control circuit for controlling on / off states of the first to fourth transistors based on data to be supplied to the data line pair.

  According to the present invention, the maximum value of the potential difference between the first data line pair is equal to the difference between the first potential (<first power supply potential) and the second power supply potential. Therefore, the power consumption of the semiconductor device can be reduced compared to the case where the maximum value of the potential difference between the first data line pair is equal to the difference between the first power supply potential and the second power supply potential.

1 is a block diagram showing an overall configuration of a semiconductor device 1 according to a preferred embodiment of the present invention. Is a block diagram showing a (portion extending in the local IO line LIO0 from the bank BA ₀₎ preferably a part of the structure the semiconductor device 1 according to the first embodiment of the present invention. FIG. 11 is a block diagram showing another part of the configuration of the semiconductor device 1 shown in FIG. 1 (part related to the main IO line MIO). FIG. 2 is a signal waveform diagram of the semiconductor device 1 shown in FIG. 1. FIG. 6 is a block diagram showing a part of a configuration of a semiconductor device 1 according to a preferred second embodiment of the present invention (a part related to a main IO line MIO). FIG. 6 is a signal waveform diagram of the semiconductor device 1 shown in FIG. 3 and the semiconductor device 1 shown in FIG. 5.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The semiconductor device 1 according to the first embodiment of the present invention is a DRAM of DDR4 types that are integrated into a single semiconductor chip, as shown in FIG. 1, is divided into (n + 1) of the bank _BA 0 _{~BA n} A memory cell array 30 is provided. Each bank BA _k (k is an integer of 0 to n) is a unit that can individually execute a command, and can basically operate in parallel.

Although not shown in Figure 1, a plurality of word lines and a plurality of bit lines which cross each other in each bank BA _k is provided, the memory cells are arranged at intersections thereof. The selection of the word line is performed by the row decoder 31 _k , and the selection of the bit line is performed by the column decoder 33 _k . The bit lines are respectively connected to the corresponding sense amplifiers in the sense circuit 32 _k , and the bit lines selected by the column decoder 33 _k are connected to the data control circuit 34 via the corresponding sense amplifiers. Each bit line and the data control circuit 34 are connected by a local IO line and a main IO line, which will be described in detail later. The data control circuit 34 is connected to the input / output circuit 36 via the latch circuit 35. The input / output circuit 36 is a circuit block that inputs and outputs data DQ through the data terminal 16.

  In addition to the data terminal 16, the semiconductor device 1 includes clock terminals 10a and 10b, a clock enable terminal 11, an address terminal 12, a command terminal 13, an alert terminal 14, a power supply terminal 15, a data terminal 16, a strobe terminal 17, as external terminals. An on-die termination (ODT) terminal 18 and a data mask (DM) / data bus inversion (DBI) terminal 19 are provided.

  The strobe terminal 17 is a terminal for inputting / outputting external strobe signals DQS, / DQS. The external strobe signals DQS and / DQS are signals for defining the input / output timing of the data DQ input / output via the data terminal 16, and there are signals corresponding to read data and signals corresponding to write data. . The former is output from the input / output circuit 36 to the outside via the strobe terminal 17. The latter is supplied from the outside to the latch circuit 35 via the strobe terminal 17. In the present specification, a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, external strobe signals DQS and / DQS are complementary signals.

The clock terminals 10a and 10b are terminals to which external clock signals CK and / CK are supplied, respectively. The clock signals CK and / CK are also complementary signals. The external clock signals CK and / CK supplied to the clock terminals 10 a and 10 b are supplied to the clock generation circuit 20 and the DLL circuit 37. The clock generation circuit 20 is a circuit that generates an internal clock signal based on the external clock signals CK and / CK. The generated internal clock signal is supplied to the command decoder 21, the control logic 22, the column decoders 33 _{1 to} 33 _n , the data control circuit 34, the latch circuit 35, and the like. The DLL circuit 37 is a circuit that generates an output clock signal whose phase is controlled based on the external clock signals CK and / CK. The output clock signal is used by the input / output circuit 36 as a timing signal that defines the output timing of the read data.

  The address terminal 12 includes a plurality of terminals to which each bit of the address signal ADD including the bank address signal BA and the address signal Address is supplied. The supplied address signal ADD is supplied to the row control circuit 25, the column control circuit 26, the mode register 24, the command decoder 21, and the like.

Usually, the address signal ADD is a signal for specifying a memory cell. In this case, one of the plurality of banks BA _k is specified by the bank address signal BA, and a memory cell in the bank BA _k specified by the bank address signal BA is specified by the address signal Address. The address signal Address includes a row address that specifies a word line and a column address that specifies a bit line. The row address is supplied to the row control circuit 25 and the column address is supplied to the column control circuit 26, respectively.

The row control circuit 25 has a function of selecting the bank BA _k based on the bank address signal BA and controlling the row decoder 31 _k in the selected bank BA _k based on the row address. The row decoder 31 _k, based on the supplied row address, and selects a word line as described above. The column control circuit 26 has a function of controlling the column decoder 33 _k on the basis of the column address. The column decoder 33 _k selects a bit line as described above based on the supplied column address.

  On the other hand, the address signal ADD when the semiconductor device 1 enters the mode register set mode is a signal indicating predetermined information corresponding to the command signal input at the same time. The address signal ADD in this case is supplied to the mode register 24, whereby the contents of the mode register 24 are updated.

  The command terminal 13 includes a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, an act signal / ACT, a parity signal PRT, a reset signal RESET_N, and a boundary scan signal TEN. Are constituted by a plurality of terminals to which various command signals CMD are respectively supplied. The command signal CMD supplied to the command terminal 13 is input to the command decoder 21 and converted into various internal commands by the command decoder 21. Various internal command signals generated by the command decoder 21 are supplied to the control logic 22. The control logic 22 is configured to control operations of the row control circuit 25, the column control circuit 26, and the like based on the supplied internal command signal.

  The command decoder 21 includes a verification circuit (not shown). The verification circuit verifies the address signal ADD and the command signal CMD based on the parity signal PRT. As a result, if there is an error in the address signal ADD or the command signal CMD, the verification circuit passes through the control logic 22 and the output buffer 23. The alert signal ALERT_N is output from the alert terminal 14.

The power supply terminal 15 includes a plurality of terminals to which the power supply potentials VPP and VDD and the ground potential VSS are respectively supplied. The potential supplied to the power supply terminal 15 as the power supply potential VPP is usually a potential at a higher potential level than the power supply potential VDD. Each potential supplied to the power supply terminal 15 is supplied to the voltage generation circuit 39. Voltage generating circuit 39 is a circuit block that generates various internal potentials based power supply potential VDD, the VPP, which will be described later local IO line pair precharge potential at a bit line potential VBLP, the sense amplifier in the sense circuit 32 _k The array potential VARY and the like used in the above are generated. Both the bit line potential VBLP and the array potential VARY are potential levels lower than the power supply potential VDD, and the voltage generation circuit 39 generates these potentials by stepping down the power supply potential VDD.

  The ODT terminal 18 is a terminal to which a termination signal ODT is supplied. The termination signal ODT is a signal that is activated when an output buffer (not shown) included in the input / output circuit 36 is used as a termination resistor, and is supplied from the ODT terminal 18 to the input / output circuit 36.

  The DM / DBI terminal 19 is a terminal to which the data mask signal DM or the data bus inversion signal DBI is supplied. The data mask signal DM is activated when masking part of the write data and read data, and the data bus inversion signal DBI is when the read data is inverted by the DBI technique added in DDR4. It is a signal that is activated. Both the data mask signal DM and the data bus inversion signal DBI are supplied from the DM / DBI terminal 19 to the input / output circuit 36.

The overall structure of the semiconductor device 1 according to the present embodiment has been described above. Next, a detailed description will be given focusing on the characteristic part of the present invention. In the following description, the description will be given focusing on the bank BA ₀ shown in FIG. 1, but the same applies to the other banks BA _{1 to} BA _n .

As shown in FIG. 2, inside the bank BA _0, 4 pair of bit lines BL0~BL3 is extended. As described above, although in the bank BA ₀ word line and a memory cell is provided to the other, it is not shown in these in FIG. Although the number of bit line pairs extending in the bank BA ₀ is four here, one to three or five or more bit line pairs may be extended.

  Each bit line pair BLm (m is an integer of 0 to 3) is constituted by two bit lines BLmT and BLmB. Complementary data (read data or write data) is supplied to the bit lines BLmT and BLmB.

The sense circuit 32 _k illustrated in FIG. 1, includes a sense amplifier 40 _m per bit line pair BLm. Further, the column decoder 33 _k shown in FIG. 1 includes a column switch 41 _m for each bit line pair BLm, and each bit line pair BLm is connected to the local IO line pair LIO0 (via the corresponding column switch 41 _m ). 2nd data line pair). Local IO line pair LIO0 is one of a plurality of local IO line pairs provided corresponding to the bank BA _0, the local IO line LIO0B (third data line) and the local IO line LIO0T (fourth data lines ). Other local IO line pairs and bit line pairs connected to these are not shown, but have the same configuration.

The sense amplifier 40 _m plays a role of amplifying the potential between the bit line pair BLm and outputting it to the local IO line pair LIO0 at the time of reading. Specifically, of the bit lines BLmT and BLmB, one potential whose potential is relatively low is driven to the potential level of the ground potential VSS, and the other potential is driven to the potential level of the array potential VARY described above. As a result, the read data is amplified. Meanwhile, the sense amplifier 40 _m at the time of writing, serves to write the potential between the local IO line pair LIO0, the corresponding memory cell as write data. The specific operation is the same as that at the time of reading.

Column switch 41 _m, as shown in FIG. 2, formed by transistors (NMOS) provided for each bit line. The gate electrodes of the transistors constituting the column switch 41 _m is a column switch selecting signal YSm from the column control circuit 26 shown in FIG. 1 is supplied. When the corresponding column switch selection signal YSm is activated, the column switch 41 _m connects the corresponding bit line pair BLm to the local IO line pair LIO0, and when the corresponding column switch selection signal YSm is deactivated. The corresponding bit line pair BLm is configured to be disconnected from the local IO line pair LIO0. Thereby, only the bit line pair BLm connected to the memory cell to be read or written is connected to the local IO line pair LIO0.

  The local IO line pair LIO0 is provided with a precharge circuit 42 as shown in FIG. The local IO line pair LIO0 is connected to the main IO line pair MIO (first data line pair) via the local IO line selection switch 43. Although only one local IO line pair connected to the main IO line pair MIO is shown here, a plurality of local IO line pairs are actually connected to one main IO line pair MIO. The main IO line pair MIO includes a main IO line MIOB (first data line) and a main IO line MIOT (second data line). The precharge circuit 42 and the local IO line selection switch 43 are provided for each local IO line pair.

  As shown in FIG. 2, the precharge circuit 42 includes a transistor T11 (an eleventh transistor) and a transistor (a twelfth transistor) each having one end connected to the local IO lines LIO0B and LIO0T. The bit line potential VBLP (third power supply potential) described above is commonly supplied to the other ends of the transistors T11 and T12. Transistors T11 and T12 are both NMOS. The local IO line selection switch 43 has one end connected to the local IO line LIO0B, the other end connected to the main IO line MIOB, one end connected to the local IO line LIO0T, and the other end connected to the main IO line. And a transistor T10 connected to the line MIOT. Transistors T9 and T10 are also NMOS.

  A control signal AMST0 is commonly supplied to the gate electrodes of the transistors T9 and T10 from the column control circuit 26 shown in FIG. Further, an inverted signal of the control signal AMST0 is commonly supplied to the gate electrodes of the transistors T11 and T12. Therefore, the transistors T9 and T10 and the transistors T11 and T12 are in the same ON / OFF state, respectively, and when the transistors T9 and T10 are ON, the transistors T11 and T12 are OFF, and when the transistors T9 and T10 are OFF, the transistor T11 , T12 are turned on.

  The control signal AMST0 is a signal that is activated to a high level when it is necessary to connect the local IO line pair LIO0 and the main IO line pair MIO at the time of reading or writing. The column control circuit 26 is configured to operate in response to a potential (second potential) higher than the bit line potential VBLP. Therefore, the potential level of the control signal AMST0 is higher than the bit line potential VBLP. Yes. Hereinafter, the description is continued assuming that the potential level of the control signal AMST0 is equal to the power supply potential VDD.

  Here, for example, when focusing on the transistor T11, there is an upper limit in the potential that can be supplied from the transistor T11 to the local IO line LIO0B. Specifically, a potential larger than the smaller one of VBLP and VDD (second potential) −Vth cannot be supplied to the local IO line LIO0B through the transistor T11. However, Vth is the threshold voltage of the transistor T11.

  The upper limit value VBLP is generated because the potential supplied to the drain of the transistor T11 is the bit line potential VBLP. On the other hand, the upper limit value VDD-Vth is generated because the transistor T11 is an NMOS. In other words, the NMOS does not turn on unless the potential difference between the gate and the source becomes Vth or more. However, in the case of the transistor T11, the local IO line LIO0B becomes the source, so that the potential of the local IO line LIO0B and the activation become active. The difference between the potential level of the control signal AMST0 in the state needs to be Vth or more. Since the potential level of the control signal AMST0 in the active state is the power supply potential VDD as described above, the potential of the local IO line LIO0B must be equal to or lower than VDD−Vth in order for the transistor T11 to be turned on. . Therefore, the transistor T11 cannot supply a potential higher than VDD−Vth to the local IO line LIO0B.

  The above situation also applies to the transistor T12. Thus, the potentials that can be supplied by the transistors T11 and T12 that are NMOSs are not only limited by the magnitude of the potential supplied to the drain, but also limited by the magnitude of the threshold voltage Vth. Such a limitation due to the magnitude of the threshold voltage is caused by the fact that the transistors T11 and T12 are NMOS, and does not occur if the transistors T11 and T12 are PMOS. Therefore, in general, PMOS is often used as such a precharging transistor, but NMOS is used as the transistors T11 and T12 here so that VBLP <VDD−Vth. This is because the potential is set. If VBLP <VDD−Vth, the limitation due to the magnitude of the threshold voltage is not a problem in practice. Therefore, NMOSs suitable for miniaturization can be used as the transistors T11 and T12.

  Next, as shown in FIG. 3, the main IO line pair MIO is connected to the local IO line pair LIO0 at one end and to the data control circuit 34 at the other end. The main IO line pair MIO includes a write precharge circuit 50, a read precharge circuit 51, a write driver 52, a main IO line selection switch 53, and a read precharge in order from the local IO line pair LIO0. A circuit 54 is provided. The write driver 52 is connected to a control circuit 55 that constitutes a part of the data control circuit 34 shown in FIG.

  First, the eight types of signals shown in FIG. 3 will be described. First, the data signal DWBSLT is a signal indicating write data supplied from the outside of the semiconductor device 1 to the data terminal 16 shown in FIG. 1, and passes through the input / output circuit 36 and the latch circuit 35 shown in FIG. 55 is supplied. The potential level of the data signal DWBSLT is the power supply potential VDD because the potential level of the write data is the power supply potential VDD and the input / output circuit 36 and the latch circuit 35 operate by receiving the power supply potential VDD. ing. The input of write data from the outside to the data terminal 16 is performed by, for example, a burst input of 8 bits.

  Next, the data mask signal DWDMLB is a low-active signal supplied from the outside of the semiconductor device 1 to the DM / DBI terminal 19 shown in FIG. 1, and the input / output circuit 36 and the latch circuit 35 shown in FIG. Then, it is supplied to the control circuit 55. Similarly to the data signal DWBSLT, the potential level of the data mask signal DWDMLB is also the power supply potential VDD. The data mask signal DWDMLB has bits corresponding to each of a series of data bits that are burst input to the data terminal 16 as write data, and is input to the semiconductor device 1 but is a target of writing to the memory cell. Control is performed so that the bit corresponding to the data bit that is not to be activated is activated (becomes low) and the other bits are deactivated (becomes high).

  The write enable signal DWAED0T is a high active signal supplied to the control circuit 55 from the control logic 22 shown in FIG. The control logic 22 is configured to activate the write enable signal DWAED0T when execution of a write operation is instructed by the command signal CMD supplied to the command terminal 13. Since the control logic 22 operates by receiving the power supply potential VDD, the potential level of the write enable signal DWAED0T is also the power supply potential VDD.

  The precharge signal DMIOPRE0WRT is a high active signal supplied to the write precharge circuit 50 from the column control circuit 26 shown in FIG. The precharge signal DMIOPRE0WRT is activated when the main IO line pair MIO is precharged during the write operation. Since the column control circuit 26 operates by receiving the power supply potential VDD, the potential level of the precharge signal DMIOPRE0WRT is also the power supply potential VDD.

  The precharge signal DMIOPRE0RDB and the equalize signal DMIOEQ0B are low active signals supplied from the column control circuit 26 shown in FIG. 1 to the read precharge circuit 51, respectively. Both of these are activated when the main IO line pair MIO is precharged during the read operation. The potential levels of the precharge signal DMIOPRE0RDB and the equalize signal DMIOEQ0B are also the power supply potential VDD, similar to the precharge signal DMIOPRE0WRT.

  The equalize signal DRAEQB is a low active signal supplied from the column control circuit 26 shown in FIG. 1 to the read precharge circuit 54. The equalize signal DRAEQB is also activated when the main IO line pair MIO is precharged during the read operation. The potential level of equalize signal DRAEQB is also power supply potential VDD.

  The main IO line selection signal DRATG0B is a low active signal supplied to the main IO line selection switch 53 from the column control circuit 26 shown in FIG. The main IO line selection signal DRATG0B is activated when the main IO line pair MIO is connected to the data control circuit 34 in performing the read operation. The potential level of main IO line selection signal DRATG0B is also power supply potential VDD.

  Hereinafter, the configuration of each circuit provided for the main IO line pair MIO and the operation of each circuit that has received each signal described above will be described.

  First, the write driver 52 has one end connected to the main IO line MIOB, the other end supplied with the power supply potential VDD (first power supply potential), and one end connected to the main IO line MIOT. The transistor T2 (second transistor) connected to the other end and supplied with the power supply potential VDD, one end connected to the main IO line MIOB, and the other end supplied with the ground potential VSS (second power supply potential). A transistor T3 (third transistor) and a transistor T4 (fourth transistor) having one end connected to the main IO line MIOT and the other end supplied with the ground potential VSS are configured.

  The on / off states of the transistors T1 to T4 are controlled by the control circuit 55. The control circuit 55 is configured to control the on / off states of the transistors T1 to T4 based on the data DWBSLT.

  More specifically, the control circuit 55 supplies a logical product signal of the data DWBSLT, the data mask signal DWDMLB, and the write enable signal DWAED0T to the gate electrodes of the transistors T1 and T2, and the inverted signal of the data DWBSLT and the data mask signal. A logical product signal of DWDMLB and a write enable signal DWAED0T is supplied to the gate electrodes of the transistors T3 and T4. Note that the control circuit 55 is a circuit that operates in response to the power supply potential VDD. Therefore, the potential level of these logical product signals is also the power supply potential VDD.

  Accordingly, on condition that both the data mask signal DWDMLB and the write enable signal DWAED0T are activated, the transistors T2 and T3 are turned on when the data DWBSLT is high (first value), and the transistors T1 and T4 are turned on. Is turned off. Therefore, the main IO line MIOT is at a high level and the main IO line MIOB is at a low level. On the other hand, when the data DWBSLT is low (second value), the transistors T2 and T3 are turned off and the transistors T1 and T4 are turned on. Therefore, the main IO line MIOT is at a low level and the main IO line MIOB is at a high level. When at least one of the data mask signal DWDMLB and the write enable signal DWAED0T is inactive, the transistors T1 to T4 are all turned off, and the voltage supply from the write driver 52 to the main IO line pair MIO is stopped.

  Specifically, NMOS is used as the transistors T1 to T4. As a result, the high level potential supplied from the write driver 52 to the main IO line pair MIO becomes a potential (first potential) lower than the power supply potential VDD, and the low level potential becomes the ground potential VSS.

  The high level potential is lower than the power supply potential VDD because of the above-described characteristics of the NMOS. That is, as described above, in order to turn on the NMOS, the potential difference between the gate and the source needs to be equal to or higher than the threshold voltage Vth. Further, the potential level of the signal supplied to the gate electrodes of the transistors T1 and T2 is the power supply potential VDD as described above. This means that the potential of the main IO lines MIOB and MIOT cannot be higher than VDD-Vth. Therefore, the high level potential supplied from the write driver 52 to the main IO line pair MIO is a potential that is lower than the power supply potential VDD by the threshold voltage Vth of the transistors T1 and T2.

  As described above, the high-level potential supplied from the write driver 52 to the main IO line pair MIO becomes the potential VDD-Vth lower than the power supply potential VDD, so that the potential difference between the main IO line pair MIO is VDD-Vth at the maximum. −VSS. On the other hand, if the transistors T1 and T2 are composed of PMOS, the upper limit value of the potential of the main IO lines MIOB and MIOT does not occur as described above, so that the potential difference between the main IO line pair MIO is a maximum of VDD. −VSS. Therefore, according to the semiconductor device 1 according to the present embodiment, the charge / discharge current when writing the write data to the main IO line pair MIO can be reduced as compared with the case where the transistors T1 and T2 are configured by PMOS. Thus, it can be said that the power consumption of the portion related to the data writing to the memory cell in the configuration of the semiconductor device 1 is realized.

  Next, the write precharge circuit 50 has one end connected to the main IO line MIOB, the other end connected to the transistor T5 (fifth transistor) to which the power supply potential VDD is supplied, and one end connected to the main IO line MIOT. The other end includes a transistor T6 (sixth transistor) to which the power supply potential VDD is supplied.

  The on / off states of the transistors T5 and T6 are controlled by a precharge signal DMIOPRE0WRT. The precharge signal DMIOPRE0WRT is commonly supplied to the gate electrodes of the transistors T5 and T6. Therefore, the transistors T5 and T6 are controlled to be in the same on / off state.

  NMOS is also used as the transistors T5 and T6. As a result, like the write driver 52, the high level potential (precharge potential) supplied from the write precharge circuit 50 to the main IO line pair MIO is lower than the power supply potential VDD (first potential), specifically Specifically, VDD-Vth. Accordingly, since the charge / discharge current of the main IO line pair MIO for precharging can be reduced, the semiconductor device 1 according to the present embodiment also provides data to the memory cell in the configuration of the semiconductor device 1 from this point. Low power consumption is achieved in parts related to writing.

  Next, one end of the read precharge circuit 51 is connected to the main IO line MIOB, the other end is connected to the transistor T7 (seventh transistor) to which the power supply potential VDD is supplied, and the other end is connected to the main IO line MIOT. And the transistor T8 (eighth transistor) to which the power supply potential VDD is supplied at the other end.

  The on / off states of the transistors T7 and T8 are controlled by a precharge signal DMIOPRE0RDB. The precharge signal DMIOPRE0RDB is supplied in common to the gate electrodes of the transistors T7 and T8. Therefore, the transistors T7 and T8 are controlled to be in the same ON / OFF state.

  Specifically, PMOS is used as the transistors T7 and T8. Since the upper limit value of the potential level is not generated in the PMOS as in the NMOS, the high level potential supplied from the read precharge circuit 51 to the main IO line pair MIO is different from the write precharge circuit 50 in the power supply potential. VDD. In this way, the precharge potential of the main IO line pair MIO is changed between the case of reading and the case of writing. In the case of reading, the data control circuit 34 in the subsequent stage reads the read data with certainty. This is because it is necessary to increase the potential difference between the main IO line pair MIO.

  In addition, read precharge circuit 51 includes a transistor T13 having one end connected to main IO line MIOB and the other end connected to main IO line MIOT. The transistor T13 is also a PMOS, and an equalize signal DMIOEQ0B is supplied to its gate electrode. The transistor T13 functions as an equalizer that equalizes the potentials of the main IO lines MIOB and MIOT when the equalize signal DMIOEQ0B is activated.

  The read precharge circuit 54 has the same configuration as the read precharge circuit 51, but the equalize signal DRAEQB is commonly supplied to the gate electrodes of the transistors T14, T15, and T16 corresponding to the transistors T7, T8, and T13, respectively. Is different in that it is. The read precharge circuit 54 plays a role of setting the potentials of the main IO lines MIOB and MIOT to the power supply potential VDD when the equalize signal DRAEQB is activated.

  The main IO line selection switch 53 includes a transistor T17 inserted in a portion of the main IO line MIOB between the write driver 52 and the read precharge circuit 54, and a write driver 52 and read precharge of the main IO line MIOT. The transistor T18 is inserted between the circuits 54. The transistors T17 and T18 are both PMOS, and the main IO line selection signal DRATG0B is commonly supplied to the respective gate electrodes. Thereby, the main IO line selection switch 53 becomes conductive when the main IO line selection signal DRATG0B is activated, and becomes non-conductive otherwise. Therefore, when the main IO line selection signal DRATG0B is activated, the main IO line pair MIO and the data control circuit 34 are connected to each other, and when the main IO line selection signal DRATG0B is inactive, The line pair MIO and the data control circuit 34 are disconnected.

FIG. 4 shows changes in potentials V _MIOB and V _MIOT of the main IO lines MIOB and MIOT when the read operation, the write operation, and the read precharge operation are sequentially performed in the semiconductor device 1 according to the present embodiment. It is a figure which shows an example. In the write operation shown in this example, six pieces of write data indicating “1” and two pieces of write data indicating “0” are input in bursts.

As shown in FIG. 4, the potentials V _MIOB and V _MIOT during the read operation vary between the power supply potential VDD and the ground potential VSS, and the variation range is VDD−VSS. On the other hand, the potentials V _MIOB and V _MIOT during the write operation vary between the power supply potential VDD−Vth and the ground potential VSS, and the variation range is VDD−Vth−VSS. Vth is a threshold voltage of the transistors T1, T2, T5, and T6 shown in FIG. Therefore, in the semiconductor device 1 according to the present embodiment, it can be said that the maximum value of the potential difference between the main IO line pair MIO during the write operation is reduced by Vth as compared with that during the read operation. it can.

Further, as shown in FIG. 4, the potentials V _MIOB and V _MIOT during the read precharge operation are the power supply potential VDD. On the other hand, although not shown, the potentials V _MIOB and V _MIOT during the write precharge operation become the power supply potential VDD−Vth. Therefore, in the semiconductor device 1 according to the present embodiment, it can be said that the precharge potential of the main IO line pair MIO during the write operation is reduced by Vth as compared with that during the read operation.

  As described above, according to the semiconductor device 1 according to the present embodiment, the maximum value of the potential difference between the main IO line pair MIO during the write operation is equal to the potential difference VDD−Vth−VSS. Therefore, compared with the case where the maximum value of the potential difference between the main IO line pair MIO during the write operation is equal to the difference VDD−VSS between the power supply potential VDD and the ground potential VSS, the main IO line pair MIO that flows along with the switching of the write data. Therefore, it can be said that low power consumption of the semiconductor device 1 is realized.

  Table 1 shows the case where the maximum value of the potential difference between the main IO line pair MIO during the write operation is VDD-Vth-VSS ([A]) and the case where it is VDD-VSS ([B]). The result of having measured the charging / discharging electric current of the main IO line pair MIO is shown. In Table 1, a 2.4 Gbps / fast model / -5C DRAM is used, and under the condition that the power supply voltage VDD is 1.3 V, 8-bit write data is continuously written (X8) and 16-bit The integrated value of the charge / discharge current when the write data continuous writing (X16) is repeated a predetermined number of times is shown. From the results of Table 1, it is understood that the charge / discharge current of the main IO line pair MIO can be reduced by adopting the configuration of the semiconductor device 1 according to the present embodiment.

  Further, according to the semiconductor device 1 according to the present embodiment, the precharge potential at the time of the write operation is VDD−Vth, so that it is consumed at the time of the precharge at the time of the write operation as compared with the case of the power supply potential VDD. The power used is also reduced. On the other hand, since the precharge potential during the read operation is maintained at the power supply potential VDD as in the conventional case, the read operation can be performed reliably.

  Next, as shown in FIG. 5, the semiconductor device 1 according to the second embodiment of the present invention includes a write precharge circuit 50, a read precharge circuit 51, a write driver 52, and a read precharge circuit. 54 is different from the semiconductor device 1 according to the first embodiment in that the power supply potential VDD supplied to each of 54 is changed to the array potential VARY. Since the other points are the same as those of the semiconductor device 1 according to the first embodiment, the following description will be made paying attention to different points.

  As described above, the array potential VARY is a potential level lower than the power supply potential VDD. Thereby, according to the semiconductor device 1 according to the present embodiment, a further reduction in power consumption is realized as compared with the semiconductor device 1 according to the first embodiment. Hereinafter, a specific example will be described.

6 shows the potentials of the main IO lines MIOB and MIOT for each of the semiconductor device 1 according to the first embodiment (Em.1) and the semiconductor device 1 according to the second embodiment (Em.2). V _MIOB, the change in _{V MIOT,} shows the results of measuring the change in the current I flowing main IO line MIOB, the MIOT. The measurement in the figure is also performed under the condition that a 2.4 Gbps / fast model / -5C DRAM is used and the power supply voltage VDD is 1.3V. The array voltage VARY is 1.0V.

  As shown in FIG. 6, in the semiconductor device 1 according to the present embodiment, the maximum value of the potential difference between the main IO line pair MIO during the write operation is slightly smaller than that of the semiconductor device 1 according to the first embodiment. ing. Further, the precharge potential during the write operation is 1.0 V, which is 0.3 V lower than 1.3 V of the semiconductor device 1 according to the first embodiment. As a result, in the semiconductor device 1 according to the present embodiment, as shown in FIG. 6, the current I is reduced by about 5% compared to the semiconductor device 1 according to the first embodiment.

  As described above, according to the semiconductor device 1 according to the present embodiment, the array potential VARY is supplied to the write precharge circuit 50 and the write driver 52, and therefore, compared with the semiconductor device 1 according to the first embodiment. Thus, the charge / discharge current of the main IO line pair MIO during the write operation can be reduced. Similarly, by supplying the array potential VARY to the read precharge circuits 51 and 54, the charge / discharge current of the main IO line pair MIO can be reduced not only during the write operation but also during the read operation. It has become. Therefore, further reduction in power consumption can be realized.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in each of the above embodiments, the case where the present invention is applied to the main IO line pair MIO of the DRAM has been described as an example. However, the present invention is not limited to the main IO line pair MIO of the DRAM, The present invention can be widely applied to data line pairs that need to be reduced.

  In each of the above embodiments, the transistors T1, T2, T5, and T6 are NMOSs to achieve low power consumption. However, when the transistors T1, T2, T5, and T6 are on, a potential lower than the potential level of the voltage supplied to the drain is achieved. It only needs to be supplied to the corresponding data line and does not necessarily have to be NMOS. For example, an N channel MISFET or the like can be used instead of the NMOS.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10a, 10b Clock terminal 11 Clock enable terminal 12 Address terminal 13 Command terminal 14 Alert terminal 15 Power supply terminal 16 Data terminal 17 Strobe terminal 18 ODT terminal 19 DM / DBI terminal 20 Clock generation circuit 21 Command decoder 22 Control logic 23 Output Buffer 24 Mode register 25 Row control circuit 26 Column control circuit 30 Memory cell array 31 _{0 to} 31 _n Row decoder 32 _{0 to} 32 _n Sense circuit 33 _{0 to} 33 _n Column decoder 34 Data control circuit 35 Latch circuit 36 Input / output circuit 37 DLL circuit 39 the voltage generating circuit ₄₀ 1 to 40 ₄ sense amplifiers ₄₁ 1 to 41 ₄ column switches 42 precharge circuit 43 Puricha for the local IO line selection switch 50 light Circuit 51, 54 the read precharge circuit 52 write driver 53 main IO line selection switch 55 control circuit _BA 0 _{~BA n} bank BL0~BL3 bit line pair BL0T~BL3T, BL0B~BL3B bit line LIO0 local IO line pair LIO0B, LIO0T Local IO line MIO Main IO line pair MIOB, MIOT Main IO lines T1 to T6, T9 to T12 N-channel MOSFET
T7, T8, T13 to T16 P-channel MOSFET

Claims (11)

A first data line pair comprising first and second data lines;
One end is connected to the first data line, the other end is supplied with a first power supply potential, and when on, a first potential lower than the first power supply potential is supplied to the first data line. A first transistor configured to:
One end is connected to the second data line, the first power supply potential is supplied to the other end, and the first potential is supplied to the second data line when it is on. A second transistor;
One end is connected to the first data line, and the second power supply potential lower than the first potential is supplied to the other end. When the second power supply potential is on, the second power supply potential is applied to the first data line. A third transistor configured to supply;
One end is connected to the second data line, the other power supply potential is supplied to the other end, and the second power supply potential is supplied to the second data line when it is on. A fourth transistor,
And a control circuit that controls on / off states of the first to fourth transistors based on data to be supplied to the first data line pair. 2. The semiconductor according to claim 1, wherein the control circuit is configured to control an on / off state of each of the first to fourth transistors in accordance with a signal whose potential level is the first power supply potential. apparatus. The control circuit turns off the first and fourth transistors, turns on the second and third transistors when the data has a first value, and turns on the second and third transistors. The semiconductor device according to claim 1, wherein the first and fourth transistors are turned on, and the second and third transistors are turned off. 4. The semiconductor device according to claim 1, wherein each of the first to fourth transistors is an N-channel MOSFET. 5. One end is connected to the first data line, the first power supply potential is supplied to the other end, and the first potential is supplied to the first data line when it is on. A fifth transistor;
One end is connected to the second data line, the first power supply potential is supplied to the other end, and the first potential is supplied to the second data line when it is on. A sixth transistor;
The semiconductor device according to claim 1, wherein the fifth and sixth transistors are controlled to be in the same on / off state. The semiconductor device according to claim 5, wherein on / off states of the fifth and sixth transistors are controlled by a signal whose potential level is the first power supply potential. The semiconductor device according to claim 5, wherein each of the fifth and sixth transistors is an N-channel MOSFET. One end is connected to the first data line, the first power supply potential is supplied to the other end, and the first power supply potential is supplied to the first data line when it is on. A seventh transistor;
One end is connected to the second data line, the first power supply potential is supplied to the other end, and the first power supply potential is supplied to the second data line when turned on. And an eighth transistor,
The semiconductor device according to any one of claims 1 to 7, wherein the seventh and eighth transistors are controlled to be in the same on / off state. The semiconductor device according to claim 8, wherein on / off states of the seventh and eighth transistors are controlled by a signal whose potential level is the first power supply potential. The semiconductor device according to claim 8, wherein each of the seventh and eighth transistors is a P-channel MOSFET. A second data line pair comprising third and fourth data lines;
A ninth transistor having one end connected to the third data line and the other end connected to the first data line;
A tenth transistor having one end connected to the fourth data line and the other end connected to the second data line;
An eleventh transistor which is an NMOS transistor having one end connected to the third data line and the other end supplied with a third power supply potential;
A twelfth transistor that is an NMOS transistor having one end connected to the fourth data line and the other end supplied with the third power supply potential;
The eleventh and twelfth transistors are controlled to be in the same ON / OFF state by a signal having a second potential whose potential level is higher than the third power supply potential. The semiconductor device according to any one of 10.

Images