TW201513112A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- TW201513112A TW201513112A TW103117492A TW103117492A TW201513112A TW 201513112 A TW201513112 A TW 201513112A TW 103117492 A TW103117492 A TW 103117492A TW 103117492 A TW103117492 A TW 103117492A TW 201513112 A TW201513112 A TW 201513112A
- Authority
- TW
- Taiwan
- Prior art keywords
- potential
- supplied
- power supply
- line
- transistor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
Abstract
Description
本發明，係有關於半導體裝置，特別是有關於具備有寫入驅動器之半導體裝置。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a write driver.
在DRAM(Dynamic Random Access Memory)等之半導體裝置中，於進行對於記憶體胞之寫入資料的寫入時，係使用有寫入驅動器。寫入驅動器，係為因應於寫入資料而對於主IO線對之電位進行控制者，並包含有使各別之輸出端子與主IO線對之其中一方(主IO線MIOT)以及另外一方(主IO線MIOB)作了連接之2個的CMOS(Complementary Metal-Oxide-Semiconductor field-effect transistor)，而構成之。以下，將被與主IO線MIOT作了連接的CMOS，稱作「TRUE側CMOS」，並將被與主IO線MIOB作了連接的CMOS，稱作「BAR側CMOS」。 In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a write driver is used when writing a write data to a memory cell. The write driver controls the potential of the main IO line pair in response to writing data, and includes one of the respective output terminals and the main IO line pair (main IO line MIOT) and the other side ( The main IO line MIOB) is composed of two CMOS (Complementary Metal-Oxide-Semiconductor field-effect transistor). Hereinafter, the CMOS connected to the main IO line MIOT is referred to as "TRUE side CMOS", and the CMOS connected to the main IO line MIOB is referred to as "BAR side CMOS".
TRUE側CMOS以及BAR側CMOS，係均具備有使P通道型MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)(PMOS)和N通道型MOSFET(NMOS)在被供給有電源電位VDD之電源配線和被供給有接地電位VSS之電源配線之間而作了串聯連接之構成。當將主IO線MIOT設為HIGH並將主IO線MIOB設為LOW的情況時，TRUE側CMOS之PMOS以及BAR側CMOS之NMOS係被設為ON，其他之2個的電晶體係被設為OFF。另一方面，當將主IO線MIOT設為LOW並將主IO線MIOB設為HIGH的情況時，TRUE側CMOS之NMOS以及BAR側CMOS之PMOS係被設為ON，其他之2個的電晶體係被設為OFF。藉由此，在主IO線對之間，係產生VDD-VSS之電位差，此電位差係通過感測放大器以及位元線對而被寫入至記憶體胞中。 Both the TRUE side CMOS and the BAR side CMOS are equipped with P-channel MOSFETs (Metal-Oxide-Semiconductor) The Field-Effect Transistor (PMOS) and the N-channel MOSFET (NMOS) are connected in series between a power supply line to which the power supply potential VDD is supplied and a power supply line to which the ground potential VSS is supplied. When the main IO line MIOT is set to HIGH and the main IO line MIOB is set to LOW, the PMOS of the TRUE side CMOS and the MOS of the BAR side CMOS are turned ON, and the other two electro-crystal systems are set. OFF. On the other hand, when the main IO line MIOT is set to LOW and the main IO line MIOB is set to HIGH, the PMOS of the TRUE side CMOS and the PMOS of the BAR side CMOS are turned ON, and the other two of the crystals are turned on. The system is set to OFF. Thereby, a potential difference of VDD-VSS is generated between the main IO line pairs, and this potential difference is written into the memory cell through the sense amplifier and the bit line pair.
在專利文獻1之圖4中，係對於具有上述一般之構造的寫入驅動器之半導體裝置有所揭示。 In Fig. 4 of Patent Document 1, a semiconductor device having a write driver of the above general configuration is disclosed.
[專利文獻1]日本特開2009-13035號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2009-13035
然而，當如同上述一般而進行電晶體之ON、OFF的情況時，於每次之ON、OFF的切換時，係會成為 在主IO線對處流動有電流。流動有電流一事，係代表著電力被消耗。在近年之半導體裝置中，對於低消耗電力化之要求係日益嚴苛，並要求能夠對起因於此種電流(充放電電流)所導致的電力消耗盡可能地作抑制。 However, when the transistor is turned ON or OFF as described above, it will become the switch between ON and OFF each time. There is a current flowing at the main IO line pair. The fact that there is current flowing means that electricity is being consumed. In semiconductor devices in recent years, the demand for low power consumption has become increasingly stringent, and it is required to be able to suppress as much as possible the power consumption caused by such current (charge and discharge current).
於此，針對DRAM之寫入動作，主IO線對之間的電位差係並非絕對需要身為VDD-VSS，就算是更小之值，亦能夠充分地進行寫入資料之寫入。如同上述一般之主IO線對的充放電電流，由於係成為若是主IO線對之間的電位差之變動越大則會越增大，因此，從低消耗電力化之觀點來看，主IO線對間之電位差成為VDD-VSS一事係為無謂的浪費。故而，係對於將主IO線對之間的電位差縮小一事有所要求。 Here, in the DRAM write operation, the potential difference between the main IO line pairs is not absolutely required to be VDD-VSS, and even if it is a smaller value, writing of the write data can be sufficiently performed. The charging/discharging current of the above-described main IO line pair is increased as the potential difference between the main IO line pairs increases. Therefore, the main IO line is from the viewpoint of low power consumption. The potential difference between the pair becomes VDD-VSS, which is a waste of unnecessary. Therefore, there is a need to reduce the potential difference between the main IO line pairs.
由本發明之其中一側面所致之半導體裝置，其特徵為，係具備有：第1資料線對，係由第1以及第2資料線所成；和第1電晶體，係使其中一端與前述第1資料線作連接，並於另外一端處被供給有第1電源電位，且構成為當成為ON時而將較前述第1電源電位更低之第1電位供給至前述第1資料線處；和第2電晶體，係使其中一端與前述第2資料線作連接，並於另外一端處被供給有前述第1電源電位，且構成為當成為ON時而將前述第1電位供給至前述第2資料線處；和第3電晶體，係使其中一端與前述第1資料線作連接，並於另外一端處被供給有 較前述第1電位更低之第2電源電位，且構成為當成為ON時而將前述第2電源電位供給至前述第1資料線處；和第4電晶體，係使其中一端與前述第2資料線作連接，並於另外一端處被供給有前述第2電源電位，且構成為當成為ON時而將前述第2電源電位供給至前述第2資料線處；和控制電路，係基於應供給至前述第1資料線對處之資料，來對於前述第1乃至第4電晶體之ON、OFF狀態作控制。 A semiconductor device according to one aspect of the present invention is characterized in that: a first data line pair is formed by the first and second data lines; and the first transistor is one end and the other end The first data line is connected, and the first power supply potential is supplied to the other end, and is configured to supply a first potential lower than the first power supply potential to the first data line when turned ON; And the second transistor is configured such that one end thereof is connected to the second data line, and the first power source potential is supplied to the other end, and the first potential is supplied to the first portion when the voltage is turned ON. 2 data line; and the third transistor, one end is connected to the first data line, and is supplied at the other end a second power supply potential lower than the first potential, and configured to supply the second power supply potential to the first data line when turned ON; and the fourth transistor to have one end and the second The data line is connected, and the second power supply potential is supplied to the other end, and the second power supply potential is supplied to the second data line when turned ON; and the control circuit is supplied based on The data of the first data line pair is controlled to the ON and OFF states of the first to fourth transistors.
若依據本發明，則第1資料線對間之電位差的最大值，係成為與第1電位(<第1電源電位)和第2電源電位之間的差相等。故而，相較於第1資料線對間之電位差的最大值係成為與第1電源電位和第2電源電位之間的差相等的情況，係能夠實現半導體裝置之低消耗電力化。 According to the invention, the maximum value of the potential difference between the first data line pair is equal to the difference between the first potential (<first power supply potential) and the second power supply potential. Therefore, the maximum value of the potential difference between the first data line pair and the second power source potential is equal to the difference between the first power supply potential and the second power supply potential, and the semiconductor device can be reduced in power consumption.
1‧‧‧半導體裝置 1‧‧‧Semiconductor device
10a、10b‧‧‧時脈端子 10a, 10b‧‧‧ clock terminals
11‧‧‧時脈致能端子 11‧‧‧clock enable terminal
12‧‧‧位址端子 12‧‧‧ address terminal
13‧‧‧指令端子 13‧‧‧Command terminals
14‧‧‧警報端子 14‧‧‧Alarm terminal
15‧‧‧電源端子 15‧‧‧Power terminal
16‧‧‧資料端子 16‧‧‧data terminal
17‧‧‧閃控端子 17‧‧‧Flash control terminal
18‧‧‧ODT端子 18‧‧‧ODT terminal
19‧‧‧DM/DBI端子 19‧‧‧DM/DBI terminals
20‧‧‧時脈產生電路 20‧‧‧ Clock generation circuit
21‧‧‧指令解碼器 21‧‧‧Command decoder
22‧‧‧控制邏輯 22‧‧‧Control logic
23‧‧‧輸出緩衝器 23‧‧‧Output buffer
24‧‧‧模式暫存器 24‧‧‧ mode register
25‧‧‧行控制電路 25‧‧‧ line control circuit
26‧‧‧列控制電路 26‧‧‧ column control circuit
30‧‧‧記憶體胞陣列 30‧‧‧ Memory Cell Array
310~31n‧‧‧行解碼器 31 0 ~ 31 n ‧‧‧ row decoder
320~32n‧‧‧感測電路 32 0 ~ 32 n ‧‧‧Sensor circuit
330~33n‧‧‧列解碼器 33 0 ~33 n ‧‧‧ column decoder
34‧‧‧資料控制電路 34‧‧‧Data Control Circuit
35‧‧‧閂鎖電路 35‧‧‧Latch circuit
36‧‧‧輸入輸出電路 36‧‧‧Input and output circuits
37‧‧‧DLL電路 37‧‧‧DLL circuit
39‧‧‧電壓產生電路 39‧‧‧Voltage generation circuit
401~404‧‧‧感測放大器 40 1 ~ 40 4 ‧‧‧Sense Amplifier
411~414‧‧‧列開關 41 1 ~41 4 ‧‧‧ column switch
42‧‧‧預充電電路 42‧‧‧Precharge circuit
43‧‧‧局部IO線選擇開關 43‧‧‧Local IO line selector switch
50‧‧‧寫入用預充電電路 50‧‧‧Precharging circuit for writing
51、54‧‧‧讀取用預充電電路 51, 54‧‧‧Precharge circuit for reading
52‧‧‧寫入驅動器 52‧‧‧Write driver
53‧‧‧主IO線選擇開關 53‧‧‧Main IO line selector switch
55‧‧‧控制電路 55‧‧‧Control circuit
BA0~BAn‧‧‧記憶庫 BA 0 ~BA n ‧‧‧Memory
BL0~BL3‧‧‧位元線對 BL0~BL3‧‧‧ bit line pair
BL0T~BL3T、BL0B~BL3B‧‧‧位元線 BL0T~BL3T, BL0B~BL3B‧‧‧ bit line
LIO0‧‧‧局部IO線對 LIO0‧‧‧Local IO pair
LIO0B、LIO0T‧‧‧局部IO線 LIO0B, LIO0T‧‧‧Local IO line
MIO‧‧‧主IO線對 MIO‧‧‧Main IO line pair
MIOB、MIOT‧‧‧主IO線 MIOB, MIOT‧‧‧ main IO line
T1~T6、T9~T12‧‧‧N通道型MOSFET T1~T6, T9~T12‧‧‧N channel MOSFET
T7、T8、T13~T16‧‧‧P通道型MOSFET T7, T8, T13~T16‧‧‧P channel MOSFET
[圖1]對於由本發明之理想實施形態所致的半導體裝置1之全體構成作展示的區塊圖。 Fig. 1 is a block diagram showing the overall configuration of a semiconductor device 1 according to a preferred embodiment of the present invention.
[圖2]對於由本發明之理想之第1實施形態所致的半導體裝置1之構成的一部分(從記憶庫BA0起直到局部IO線LIO0為止的部份)作展示之區塊圖。 [Fig. 2] A block diagram showing a part of the configuration of the semiconductor device 1 (the portion from the memory BA 0 to the local IO line LIO0) due to the first preferred embodiment of the present invention.
[圖3]對於圖1中所示之半導體裝置1的構成之另外一部分(關連於主IO線MIO之部分)作展示的區塊圖。 [Fig. 3] A block diagram showing another part of the configuration of the semiconductor device 1 shown in Fig. 1 (portion related to the main IO line MIO).
[圖4]圖1中所示之半導體裝置1的訊號波形圖。 FIG. 4 is a signal waveform diagram of the semiconductor device 1 shown in FIG. 1.
[圖5]對於由本發明之理想之第2實施形態所致的半導體裝置1之構成的一部分(關連於主IO線MIO之部份)作展示之區塊圖。 [Fig. 5] A block diagram showing a part of the configuration of the semiconductor device 1 (part of the main IO line MIO) which is obtained by the second embodiment of the present invention.
[圖6]圖3中所示之半導體裝置1以及圖5中所示之半導體裝置1的訊號波形圖。 FIG. 6 is a signal waveform diagram of the semiconductor device 1 shown in FIG. 3 and the semiconductor device 1 shown in FIG. 5.
以下，參考所添附之圖面，針對本發明之理想實施形態作詳細說明。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.
由本發明之第1實施形態所致之半導體裝置1，係為被積體於1個的半導體晶片中之DDR4型態的DRAM，並如圖1中所示一般，具備有被分割成n+1個的記憶庫(bank)BA0~BAn之記憶體胞陣列30。各記憶庫BAk(k為0~n之整數)係為能夠個別地實行指令之單位，基本上係能夠平行(parallel)地進行動作。 The semiconductor device 1 according to the first embodiment of the present invention is a DDR4 type DRAM which is integrated in one semiconductor wafer, and is generally divided into n+1 as shown in FIG. The memory cell array 30 of the banks BA 0 ~ BA n . Each of the banks BA k (k is an integer of 0 to n) is a unit capable of individually executing commands, and basically operates in parallel.
於圖1中雖並未作展示，但是，在各記憶庫BAk中，係被設置有相互交叉之複數之字元線和複數之位元線，在該些之交點處係被配置有記憶體胞。字元線之選擇，係藉由行(row)解碼器31k來進行，位元線之選擇，係藉由列(column)解碼器33k來進行。位元線，係分別被與感測電路32k內之所對應的感測放大器作連接， 藉由列解碼器33k所選擇了的位元線，係經由所對應之感測放大器而被與資料控制器34作連接。各位元線和資料控制電路34之間，係藉由局部IO線以及主IO線而被作連接，但是，針對此點，係於後再作詳細敘述。資料控制電路34，係經由閂鎖電路35而被與輸入輸出電路36作連接。輸入輸出電路36，係為經由資料端子16而進行資料DQ之輸入輸出的電路區塊。 Although in FIG. 1 is not for display, however, in each memory bank BA k in the train is provided with a plurality of word lines intersecting each other and a plurality of bit lines are arranged at intersections of the plurality of lines with memory Body cell. Select the word lines, line by line (Row) performed by the decoder 31 k, the selected bit line, column by line (column) decoder 33 k is performed. Bit lines, as lines are connected to the corresponding sensing circuits within the sense amplifier 32 k, 33 k by the column decoder of the selected bit line, sense line via the corresponding sense amplifier and is The data controller 34 is connected. The bit lines and the data control circuit 34 are connected by a local IO line and a main IO line. However, this point will be described in detail later. The data control circuit 34 is connected to the input/output circuit 36 via the latch circuit 35. The input/output circuit 36 is a circuit block that performs input and output of the material DQ via the data terminal 16.
半導體裝置1，係除了資料端子16以外，亦作為外部端子，而具備有時脈端子10a、10b、時脈致能端子11、位址端子12、指令端子13、警報端子14、電源端子15、資料端子16、閃控(strobe)端子17、中斷電阻(On DieTermination，ODT)端子18、資料遮罩(DM)/資料匯流排轉位(DATA BUS INVERSION，DBI)端子19。 The semiconductor device 1 includes the pulse terminals 10a and 10b, the clock enable terminal 11, the address terminal 12, the command terminal 13, the alarm terminal 14, and the power supply terminal 15, in addition to the data terminal 16. Data terminal 16, strobe terminal 17, On DieTermination (ODT) terminal 18, data mask (DM) / data BUS INVERSION (DBI) terminal 19.
閃控端子17，係為用以將外部閃控訊號DQS、/DQS作輸入輸出的端子。外部閃控訊號DQS、/DQS，係為對於經由資料端子16所輸入輸出的資料DQ之輸入輸出時序作規定的訊號，並存在有對應於讀取資料者和對應於寫入資料者。前者，係從輸入輸出電路36而經由閃控端子17來輸出至外部。後者，係從外部而經由閃控端子17來供給至閂鎖電路35處。另外，在本說明書中，在訊號名稱之前頭而附加有斜線(/)的訊號，係代表其為所對應之訊號的反轉訊號或者是低啟動(low active)之訊號。故而，外部閃控訊號DQS、/DQS係為互 為相補之訊號。 The flash control terminal 17 is a terminal for inputting and outputting the external flashing signals DQS and /DQS. The external flash control signals DQS and /DQS are signals for specifying the input/output timing of the data DQ input and output via the data terminal 16, and there are those corresponding to the read data and the corresponding data. The former is output from the input/output circuit 36 to the outside via the flash control terminal 17. The latter is supplied to the latch circuit 35 via the flash control terminal 17 from the outside. In addition, in the present specification, a signal with a slash (/) appended to the signal name indicates that it is a reverse signal of the corresponding signal or a low active signal. Therefore, the external flash control signals DQS, /DQS are mutual For the signal of complement.
時脈端子10a、10b，係為分別被供給有外部時脈CK、/CK之端子。時脈訊號CK、/CK亦係為互為相補之訊號。被供給至時脈端子10a、10b處之外部時脈CK、/CK，係被供給至時脈產生電路20以及DLL電路37處。時脈產生電路20，係為基於外部時脈訊號CK、/CK而產生內部時脈訊號之電路。所產生了的內部時脈訊號，係被供給至指令解碼器21、控制邏輯22、列解碼器331~33n、資料控制電路34以及閂鎖電路35等處。DLL電路37，係為產生基於外部時脈訊號CK、/CK而被作了相位控制的輸出時脈訊號之電路。輸出時脈訊號，係作為對於藉由輸入輸出電路36所進行的讀取資料之輸出時序作規定的時序訊號而被使用。 The clock terminals 10a and 10b are terminals to which external clock pulses CK and /CK are respectively supplied. The clock signals CK and /CK are also complementary signals. The external clocks CK and /CK supplied to the clock terminals 10a and 10b are supplied to the clock generating circuit 20 and the DLL circuit 37. The clock generation circuit 20 is a circuit that generates an internal clock signal based on the external clock signals CK and /CK. The generated internal clock signal is supplied to the command decoder 21, the control logic 22, the column decoders 33 1 to 33 n , the data control circuit 34, the latch circuit 35, and the like. The DLL circuit 37 is a circuit for generating an output clock signal that is phase-controlled based on the external clock signals CK and /CK. The output clock signal is used as a timing signal for specifying the output timing of the read data by the input/output circuit 36.
位址端子12，係藉由被供給有包含記憶庫位址訊號BA以及位址訊號Address之位址訊號ADD的各位元之複數的端子所構成。所被供給而來之位址訊號ADD，係被供給至行控制電路25、列控制電路26、模式暫存器24、指令解碼器21等處。 The address terminal 12 is constituted by a terminal to which a plurality of bits including the memory address signal BA and the address signal ADD of the address signal Address are supplied. The address signal ADD supplied is supplied to the row control circuit 25, the column control circuit 26, the mode register 24, the command decoder 21, and the like.
通常，位址訊號ADD係成為特定出記憶體胞之訊號。於此情況，係藉由記憶庫位址訊號BA而特定出複數之記憶庫BAk中的其中一者，並藉由位址訊號Address來特定出藉由記憶庫位址訊號BA所特定出的記憶庫BAk內之記憶體胞。在位址訊號Address中，係包含有特定出字元線之行位址、和特定出位元線之列位址，行 位址係被供給至行控制電路25處，列位址係被供給至列控制電路26處。 Usually, the address signal ADD is a signal that is specific to the memory cell. In this case, one of the memory banks BA k of the complex number is specified by the memory address signal BA, and the address signal Address is used to specify the specific address by the memory address signal BA. The memory cells in the memory BA k . In the address signal Address, the row address of the specific word line and the column address of the specific bit line are included, and the row address is supplied to the row control circuit 25, and the column address is supplied. At the column control circuit 26.
行控制電路25，係具備有基於記憶庫位址訊號BA來選擇記憶庫BAk並基於行位址來對於所選擇了的記憶庫BAk內之行解碼器31k作控制的功能。行解碼器31k，係基於被供給而來之行位址而如同上述一般地進行字元線之選擇。又，列控制電路26，係具備有基於列位址來對於列解碼器33k作控制之功能。列解碼器33k，係基於被供給而來之列位址而如同上述一般地進行位元線之選擇。 Row control circuit 25, there is provided based on memory address signal to select memory bank BA and BA K for 31 k to the row within the selected memory bank BA K as a function of controlling the decoder based on the row address. Row decoder 31 k, and the system as described above is generally based on the selected word line from the row address is supplied. Further, the column control circuit 26 has a function of controlling the column decoder 33 k based on the column address. Column decoder 33 k, and the system as described above generally be selected based on the bit line of the column address is supplied from.
另一方面，當半導體裝置1係在模式暫存器設定模式中有所登錄的情況時之位址訊號ADD，係成為代表與在同時期中所輸入的指令訊號相對應之既定之資訊的訊號。此情況之位址訊號ADD係被供給至模式暫存器24處，藉由此，模式暫存器24之內容係被更新。 On the other hand, when the semiconductor device 1 is registered in the mode register setting mode, the address signal ADD is a signal representing the predetermined information corresponding to the command signal input in the same period. . The address signal ADD in this case is supplied to the mode register 24, whereby the contents of the mode register 24 are updated.
指令端子13，係為藉由分別被供給有晶片選擇訊號/CS、行位址閃控訊號/RAS、列位址閃控訊號/CAS、寫入致能訊號/WE、動作訊號/ACT、同位(parity)訊號PRT、重置訊號RESET_N以及邊界掃描訊號TEN等之各種指令訊號CMD的複數之端子所構成。被供給至指令端子13處之指令訊號CMD，係被輸入至指令解碼器21中，並藉由指令解碼器21而被轉換為各種內部指令。指令解碼器12所產生的各種內部指令訊號，係被供給至控制邏輯22處。控制邏輯22，係構成為基於被供 給而來之內部指令訊號，而對於行控制電路25、列控制電路26等之動作進行控制。 The command terminal 13 is provided with a wafer selection signal/CS, a row address flashing signal/RAS, a column address flashing signal/CAS, a write enable signal/WE, an action signal/ACT, and a parity. The (parity) signal PRT, the reset signal RESET_N, and the boundary scan signal TEN and the like are composed of a plurality of terminals of the command signal CMD. The command signal CMD supplied to the command terminal 13 is input to the command decoder 21, and is converted into various internal commands by the command decoder 21. The various internal command signals generated by the instruction decoder 12 are supplied to the control logic 22. Control logic 22 is configured to be based on being provided The internal command signal is given, and the operations of the row control circuit 25, the column control circuit 26, and the like are controlled.
在指令解碼器21中，係包含有未圖示之驗證電路。驗證電路，係基於同位訊號PRTY來對於位址訊號ADD以及指令訊號CMD進行驗證，並當其結果為在位址訊號ADD或者是指令訊號CMD中為存在有錯誤的情況時，經由控制邏輯22以及輸出緩衝器23而從警報端子14輸出警報訊號ALERT_N。 The command decoder 21 includes a verification circuit not shown. The verification circuit performs verification on the address signal ADD and the instruction signal CMD based on the parity signal PRTY, and when the result is that there is an error in the address signal ADD or the instruction signal CMD, via the control logic 22 and The buffer 23 is output and the alarm signal ALERT_N is output from the alarm terminal 14.
電源端子15，係藉由分別被供給有電源電位VPP、VDD以及接地電位VSS之複數的端子所構成。作為電源電位VPP而被供給至電源端子15處之電位，通常係為較電源電位VDD而更高電位準位之電位。被供給至電源端子15處之各電位，係被供給至電壓產生電路39處。電壓產生電路39，係為基於電源電位VDD、VPP而產生各種內部電位之電路區塊，並產生身為後述之局部IO線對之預充電電位的位元線電位VBLP、在感測電路32k內之感測放大器處所被使用的陣列電位VARY等。位元線電位VBLP以及陣列電位VARY，係均為較電源電位VDD而更低之電位準位的電位，電壓產生電路39，係藉由將電源電位VDD降壓，而產生此些之電位。 The power supply terminal 15 is constituted by terminals that are supplied with a plurality of power supply potentials VPP, VDD, and a ground potential VSS, respectively. The potential supplied to the power supply terminal 15 as the power supply potential VPP is usually a potential higher than the power supply potential VDD and higher. The respective potentials supplied to the power supply terminal 15 are supplied to the voltage generating circuit 39. The voltage generating circuit 39 is a circuit block that generates various internal potentials based on the power supply potentials VDD and VPP, and generates a bit line potential VBLP which is a precharge potential of a local IO line pair to be described later, in the sensing circuit 32 k The array potential VARY used at the sense amplifier inside. The bit line potential VBLP and the array potential VARY are potentials lower than the potential of the power supply potential VDD, and the voltage generating circuit 39 generates such potentials by stepping down the power supply potential VDD.
ODT端子18，係為被供給有終端訊號ODT之端子。終端訊號ODT，係為當將被包含於輸入輸出電路36中之未圖示的輸出緩衝器作為終端電阻來使用的情況時而被活性化之訊號，並從ODT端子18而被供給至輸入 輸出電路36處。 The ODT terminal 18 is a terminal to which the terminal signal ODT is supplied. The terminal signal ODT is a signal that is activated when an output buffer (not shown) included in the input/output circuit 36 is used as a terminating resistor, and is supplied from the ODT terminal 18 to the input. At output circuit 36.
DM/DBI端子19，係為被供給有資料遮罩訊號DM或者是資料匯流排轉位訊號DBI之端子。資料遮罩訊號DM，係為當將寫入資料以及讀取資料之一部分作遮蔽的情況時而被活性化之訊號，資料匯流排轉位訊號DBI，係為當藉由被追加於DDR4中之DBI技術來使讀取資料作了反轉的情況時而被活性化之訊號。資料遮罩訊號DM以及資料匯流排轉位訊號DBI，係均從DM/DBI端子19而被供給至輸入輸出電路36處。 The DM/DBI terminal 19 is a terminal to which a data mask signal DM or a data bus transposition signal DBI is supplied. The data mask signal DM is a signal that is activated when a part of the data is read and a part of the data is masked. The data bus index bit signal DBI is added to the DDR4 by being added. DBI technology is used to activate the signal when the read data is reversed. The data mask signal DM and the data bus index bit signal DBI are supplied from the DM/DBI terminal 19 to the input/output circuit 36.
以上，係針對由本實施形態所致之半導體裝置1的全體構造作了說明。接著，注目於本發明之特徵部分，而進行更為詳細之說明。另外，於以下之說明中，雖係注目於圖1中所示之記憶庫BA0來進行說明，但是，針對其他之記憶庫BA1~BAn，係亦為相同。 The entire structure of the semiconductor device 1 according to the present embodiment has been described above. Next, attention will be paid to the features of the present invention, and a more detailed description will be made. In the following description, although the memory bank BA 0 shown in FIG. 1 is described, the same is true for the other memories BA 1 to BA n .
如圖2中所示一般，在記憶庫BA0之內部，係延伸設置有4個的位元線對BL0~BL3。如同上述一般，除此之外，在記憶庫BA0中係亦被設置有字元線和記憶體胞，但是，於圖2中係將此些之圖示省略。另外，於此雖係將在記憶庫BA0內所延伸設置之位元線對的數量設為4個，但是係亦可延伸設置1~3或者是5以上之位元線對。 As shown in FIG. 2, generally, within the memory bank BA 0 , four bit line pairs BL0 to BL3 are extended. As described above, in addition to the above, word cells and memory cells are also provided in the memory bank BA 0 , but these illustrations are omitted in FIG. In addition, although the number of bit line pairs extended in the memory BA 0 is set to four, it is also possible to extend the bit line pair of 1 to 3 or 5 or more.
各位元線對BLm(m係為0~3之整數)，係藉由2根的位元線BLmT、BLmB所構成。在位元線BLmT、BLmB處，係被供給有互補之資料(讀取資料或 寫入資料)。 Each of the element line pairs BLm (m is an integer of 0 to 3) is composed of two bit lines BLmT and BLmB. At the bit lines BLmT, BLmB, they are supplied with complementary data (read data or Write data).
於圖1所示之感測電路32k中，係包含有各位元線對BLm之個別的感測放大器40m。又，在圖1所示之列解碼器33k中，係包含有各位元線對BLm之個別的列開關41m，各位元線對BLm，係經由所對應之列開關41m，而被與局部IO線對LIO0(第2資料線對)作連接。局部IO線對LIO0，係為對於記憶庫BA0所設置的複數之局部IO線對中的其中一者，並藉由局部IO線LIO0B(第3資料線)和局部IO線LIO0T(第4資料線)所構成。關於其他的局部IO線對以及被與該些作連接之位元線對，係省略圖示，但是該些係具備有相同之構成。 32 k in the sensing circuit shown in Figure 1, the system includes a 40 m wire element you individual BLm the sense amplifier. Further, in the column decoder 33 k shown in FIG. 1, the column switches 41 m including the individual element line pairs BLm and the bit line pairs BLm are connected to the corresponding column switches 41 m . The local IO line is connected to LIO0 (the second data line pair). The local IO line pair LIO0 is one of the complex local IO line pairs set for the memory bank BA 0 , and is provided by the local IO line LIO0B (3rd data line) and the local IO line LIO0T (4th data) Line). The other partial IO line pairs and the bit line pairs connected thereto are not shown, but they have the same configuration.
感測放大器40m，在讀取時係達成將位元線對BLm之間的電位放大並輸出至局部IO線對LIO0處之功能。具體而言，係藉由將位元線BLmT、BLmB中之相對性而言電位為較低之一方的電位，驅動為接地電位VSS之電位準位，並將另外一方的電位，驅動為上述之陣列電位VARY之電位準位，來進行讀取資料之放大。另一方面，進行寫入時之感測放大器40m，係達成將局部IO線對LIO0之間的電位作為寫入資料來寫入至所對應之記憶體胞中的功能。關於其之具體性的動作，係與讀取時相同。 The sense amplifier 40 m is configured to amplify the potential between the bit line pair BLm and output it to the local IO line pair LIO0 at the time of reading. Specifically, the potential of the lower potential of the bit lines BLmT and BLmB is driven to the potential of the ground potential VSS, and the other potential is driven as described above. The potential level of the array potential VARY is used to amplify the read data. On the other hand, the sense amplifier 40 m at the time of writing is a function of writing the potential between the local IO line pair LIO0 as a write data to the corresponding memory cell. The action on the specificity is the same as the reading.
列開關41m，係如圖2中所示一般，為藉由在每一位元線處所分別設置之電晶體(NMOS)所構成者。在構成列開關41m之各電晶體的閘極電極處，係從圖1中 所示之列控制電路26而被供給有列開關選擇訊號YSm。列開關41m，係構成為若是所對應之列開關選擇訊號YSm被活性化，則將所對應之位元線對BLm與局部IO線對LIO0作連接，而若是所對應之列開關選擇訊號YSm被設為非活性化，則將所對應之位元線對BLm從局部IO線對LIO0而切離。藉由此，僅有被與身為讀取或者是寫入之對象的記憶體胞作了連接之位元線對BLm，會被與局部IO線對LIO0作連接。 The column switch 41 m is generally formed by a transistor (NMOS) provided at each bit line as shown in FIG. 2 . The column switch selection signal YSm is supplied from the column control circuit 26 shown in Fig. 1 at the gate electrode of each of the transistors constituting the column switch 41 m . The column switch 41 m is configured to connect the corresponding bit line pair BLm and the local IO line pair LIO0 if the corresponding column switch selection signal YSm is activated, and if the corresponding column switch selection signal YSm When it is set to be inactive, the corresponding bit line pair BLm is separated from the local IO line pair LIO0. Thereby, only the bit line pair BLm connected by the memory cell which is the object of reading or writing is connected to the local IO line pair LIO0.
在局部IO線對LIO0處，係如圖2中所示一般，被設置有預充電電路42。又，局部IO線對LIO0，係經由局部IO線選擇開關43，而被與主IO線對MIO(第1資料線對)作連接。另外，於此雖係僅圖示有1個的被與主IO線對MIO作連接之局部IO線對，但是，實際上在1個的主IO線對MIO處係被連接有複數之局部IO線對。主IO線對MIO，係藉由主IO線MIOB(第1資料線)和主IO線MIOT(第2資料線)所構成。預充電電路42以及局部IO線選擇開關43，係被設置於每一IO線對處。 At the local IO line pair LIO0, as shown in FIG. 2, a precharge circuit 42 is provided. Further, the local IO line pair LIO0 is connected to the main IO line pair MIO (first data line pair) via the local IO line selection switch 43. In addition, although only one local IO line pair connected to the main IO line pair MIO is shown here, actually, a plurality of local IOs are connected to one main IO line pair MIO. Line pair. The main IO line pair MIO is composed of a main IO line MIOB (first data line) and a main IO line MIOT (second data line). The precharge circuit 42 and the local IO line selection switch 43 are provided at each IO line pair.
預充電電路42，係如圖2中所示一般，藉由使各別之其中一端被與局部IO線LIO0B、LIO0T作了連接的電晶體T11(第11電晶體)以及電晶體T12(第12電晶體)所構成。在電晶體T11、T12之各別的另外一端處，係共通性地被供給有上述之位元線電位VBLP(第3電源電位)。電晶體T11、T12係均為NMOS。又，局部IO線選擇開關43，係藉由使其中一端被與局部IO線 LIO0B作連接並使另外一端與主IO線MIOB作連接之電晶體T9和使其中一端被與局部IO線LIO0T作連接並使另外一端與主IO線MIOT作連接之電晶體T10所構成。電晶體T9、T10亦係為NMOS。 The precharge circuit 42 is generally as shown in FIG. 2, and has a transistor T11 (11th transistor) and a transistor T12 (12th) in which one end is connected to the local IO lines LIO0B, LIO0T. The crystal is composed of. The bit line potential VBLP (third power supply potential) described above is commonly supplied to the other end of each of the transistors T11 and T12. The transistors T11 and T12 are all NMOS. Moreover, the local IO line selection switch 43 is formed by making one end thereof and the local IO line The LIO0B is connected to the transistor T9 having the other end connected to the main IO line MIOB, and the transistor T10 having one end connected to the local IO line LIO0T and the other end connected to the main IO line MIOT. The transistors T9 and T10 are also NMOS.
在電晶體T9、T10之各閘極電極處，係從圖1中所示之列控制電路26而被共通地供給有控制訊號AMST0。又，在電晶體T11、T12之各閘極電極處，係被共通地供給有控制訊號AMST0之反轉訊號。故而，電晶體T9、T10，電晶體T11、T12，係分別相互採取相同之ON、OFF狀態，並且，當電晶體T9、T10為ON時，電晶體T11、T12係成為OFF，當電晶體T9、T10為OFF時，電晶體T11、T12係成為ON。 At each of the gate electrodes of the transistors T9 and T10, the control signal AMST0 is commonly supplied from the column control circuit 26 shown in FIG. Further, at the gate electrodes of the transistors T11 and T12, the inversion signals of the control signals AMST0 are commonly supplied. Therefore, the transistors T9, T10, and the transistors T11 and T12 are in the same ON and OFF states, respectively, and when the transistors T9 and T10 are ON, the transistors T11 and T12 are turned OFF, and the transistor T9 is turned off. When T10 is OFF, the transistors T11 and T12 are turned ON.
控制訊號AMST0，係為當進行讀取或寫入時而有必要將局部IO線對LIO0和主IO線對MIO作連接的情況時，會被活性化為HIGH準位之訊號。列控制電路26，係構成為接收較位元線電位VBLP而更高之電位(第2電位)並動作，故而，控制訊號AMST0之電位準位，係成為較位元線電位VBLP而更高之電位。以下，係假設控制訊號AMST0之電位準位為與電源電位VDD相等，來繼續進行說明。 The control signal AMST0 is a signal that is activated to a HIGH level when it is necessary to connect the local IO line pair LIO0 and the main IO line pair MIO when reading or writing. The column control circuit 26 is configured to receive a higher potential (second potential) than the bit line potential VBLP, and therefore, the potential level of the control signal AMST0 is higher than the bit line potential VBLP. Potential. Hereinafter, the description will be continued assuming that the potential level of the control signal AMST0 is equal to the power supply potential VDD.
於此，例如若是注目於電晶體T11，則能夠從電晶體T11所供給至局部IO線LIO0B處之電位，係存在有上限值。具體而言，係並無法透過電晶體T11，來對於局部IO線LIO0B而供給較VBLP以及VDD(第2電位) -Vth的兩者中之較小者而更大之電位。但是，Vth係為電晶體T11之臨限值電壓。 Here, for example, if attention is paid to the transistor T11, the potential which can be supplied from the transistor T11 to the local IO line LIO0B has an upper limit value. Specifically, it is not possible to supply the VBLP and the VDD (the second potential) to the local IO line LIO0B through the transistor T11. The smaller of the two of -Vth and the greater potential. However, Vth is the threshold voltage of the transistor T11.
上限值VBLP的發生原因，係因為被供給至電晶體T11之汲極處的電位乃身為位元線電位VBLP之故。另一方面，上限值VDD-Vth的發生原因，係因為電晶體T11乃身為NMOS之故。亦即是，NMOS，若是閘極和源極間之電位差並未成為Vth以上則便不會成為ON，但是，在電晶體T11的情況時，由於局部IO線LIO0B係成為源極，因此為了成為ON，在局部IO線LIO0B之電位和活性狀態下之控制訊號AMST0之電位準位之間的差，係需要成為Vth以上。在活性狀態下之控制訊號AMST0的電位準位，由於係如同上述一般而身為電源電位VDD，因此，為了使電晶體T11成為ON，局部IO線LIO0B之電位，係必須要成為VDD-Vth以下。故而，電晶體T11，係成為無法對於局部IO線LIO0B供給較VDD-Vth而更大之電位。 The reason why the upper limit value VBLP occurs is because the potential supplied to the drain of the transistor T11 is the bit line potential VBLP. On the other hand, the reason why the upper limit value VDD-Vth occurs is because the transistor T11 is an NMOS. In other words, the NMOS does not turn ON if the potential difference between the gate and the source does not become Vth or more. However, in the case of the transistor T11, since the local IO line LIO0B is the source, in order to become ON, the difference between the potential of the local IO line LIO0B and the potential level of the control signal AMST0 in the active state needs to be Vth or more. Since the potential level of the control signal AMST0 in the active state is the power supply potential VDD as described above, in order to turn on the transistor T11, the potential of the local IO line LIO0B must be VDD-Vth or less. . Therefore, the transistor T11 is a potential that cannot be supplied to the local IO line LIO0B by more than VDD-Vth.
以上之事態，對於電晶體T12而言，亦為相同。如此這般，身為NMOS之電晶體T11、T12所能夠供給之電位，係不僅會受到被供給至汲極處之電位的大小所限制，而亦會受到起因於臨限值電壓Vth之大小所造成的限制。此種起因於臨限值電壓之大小所造成的限制，係為起因於電晶體T11、T12乃身為NMOS一事所導致者，如果電晶體T11、T12乃身為PMOS，則並不會造成此限制。故而，一般而言，作為此種預充電用之電晶體，多係 使用PMOS，但是，於此作為電晶體T11、T12而使用NMOS的原因，係因為以成為VBLP<VDD-Vth的方式來對於各電位作設定之故。由於若是成為VBLP<VDD-Vth，則起因於臨限值電壓之大小所導致的限制實際上係並不會造成問題，因此作為電晶體T11、T12，係能夠使用適於小型化之NMOS。 The above situation is the same for the transistor T12. In this way, the potential that can be supplied by the transistors NMOS and T12 of the NMOS is limited not only by the magnitude of the potential supplied to the drain but also by the threshold voltage Vth. The restrictions caused. The limitation caused by the magnitude of the threshold voltage is caused by the fact that the transistors T11 and T12 are NMOS. If the transistors T11 and T12 are PMOS, this does not cause this. limit. Therefore, in general, as such a pre-charging transistor, multiple systems The PMOS is used. However, the reason why the NMOS is used as the transistors T11 and T12 is because the potential is set such that VBLP < VDD - Vth. In the case of VBLP < VDD - Vth, the limitation due to the magnitude of the threshold voltage does not actually cause a problem. Therefore, as the transistors T11 and T12, an NMOS suitable for miniaturization can be used.
接著，如圖3中所示一般，主IO線對MIO，係於其中一端處而被與局部IO線對LIO0作連接，並於另外一端處而被與資料控制電路34作連接。又，在主IO線對MIO處，係從局部IO線對LIO0側起，而依序被設置有寫入用預充電電路50、讀取用預充電電路51、寫入驅動器52、主IO線選擇開關53、以及讀取用預充電電路54。寫入驅動器52，係被與構成圖1中所示之資料控制電路34的一部分之控制電路55作連接。 Next, as shown in FIG. 3, the main IO line pair MIO is connected to the local IO line pair LIO0 at one end thereof, and is connected to the material control circuit 34 at the other end. Further, in the main IO line pair MIO, the write precharge circuit 50, the read precharge circuit 51, the write driver 52, and the main IO line are sequentially provided from the local IO line pair LIO0 side. The switch 53 and the read precharge circuit 54 are selected. The write driver 52 is coupled to a control circuit 55 that forms part of the data control circuit 34 shown in FIG.
首先，針對圖3中所示之8種類的訊號作說明。首先，資料訊號DWBSLT，係為代表從半導體裝置1之外部而被供給至圖1中所示之資料端子16處的寫入資料之訊號，並經由圖1中所示之輸入輸出電路36以及閂鎖電路35而被供給至控制電路55處。由於寫入資料之電位準位係身為電源電位VDD，並且輸入輸出電路36以及閂鎖電路35係為接收電源電位VDD而動作的電路，因此資料訊號DWBSLT之電位準位係成為電源電位VDD。從外部所對於資料端子16之寫入資料的輸入，例如係藉由1次8位元之叢發輸入來進行。 First, the description will be given for the eight types of signals shown in FIG. First, the data signal DWBSLT is a signal representing the write data supplied from the outside of the semiconductor device 1 to the data terminal 16 shown in FIG. 1, and via the input and output circuit 36 and the latch shown in FIG. The lock circuit 35 is supplied to the control circuit 55. Since the potential level of the write data is the power supply potential VDD, and the input/output circuit 36 and the latch circuit 35 are circuits that operate by receiving the power supply potential VDD, the potential level of the data signal DWBSLT becomes the power supply potential VDD. The input of the data to the data terminal 16 from the outside is performed, for example, by a single 8-bit burst input.
接著，資料遮罩訊號DWDMLB，係為代表從半導體裝置1之外部而被供給至圖1中所示之DM/DBI端子19處的低啟動(low active)之訊號，並經由圖1中所示之輸入輸出電路36以及閂鎖電路35而被供給至控制電路55處。資料遮罩訊號DWDMLB之電位準位，亦係與資料訊號DWBSLT相同的，而成為電源電位VDD。資料遮罩訊號，係具備有與作為寫入資料而被叢發輸入至資料端子16處之一連串的資料位元之各者相互對應的位元，並以使雖然被輸入至半導體裝置1中但是並不會成為對於記憶體胞之寫入對象的資料位元相對應之位元活性化(成為LOW)且使其他的位元成為非活性(成為HIGH)的方式而被作控制。 Next, the data mask signal DWDMLB is a low active signal that is supplied from the outside of the semiconductor device 1 to the DM/DBI terminal 19 shown in FIG. 1 and is shown in FIG. The input/output circuit 36 and the latch circuit 35 are supplied to the control circuit 55. The potential level of the data mask signal DWDMLB is also the same as the data signal DWBSLT, and becomes the power supply potential VDD. The data mask signal is provided with a bit corresponding to each of the data bits which are serially input to the data terminal 16 as the write data, and is input to the semiconductor device 1 although it is input to the semiconductor device 1 It is not controlled that the bit corresponding to the data bit to which the memory cell is written is activated (below LOW) and the other bit is made inactive (becomes HIGH).
寫入致能訊號DWAED0T，係為從圖1中所示之控制邏輯22所供給至控制電路55處之高啟動(high active)之訊號。控制邏輯22，係構成為當藉由被供給至指令端子13處之指令訊號CMD而被指示有寫入動作之實行的情況時，將寫入致能訊號DWAED0T活性化。控制邏輯22，由於係為接收電源電位VDD而動作的電路，因此寫入致能訊號DWAED0T之電位準位亦係成為電源電位VDD。 The write enable signal DWAED0T is a high active signal supplied from the control logic 22 shown in FIG. 1 to the control circuit 55. The control logic 22 is configured to activate the write enable signal DWAED0T when the execution of the write operation is instructed by the command signal CMD supplied to the command terminal 13. The control logic 22 is a circuit that operates to receive the power supply potential VDD. Therefore, the potential level of the write enable signal DWAED0T also becomes the power supply potential VDD.
預充電訊號DMIOPRE0WRT，係為從圖1中所示之列控制電路26所供給至寫入用預充電電路50處之高啟動(high active)之訊號。預充電訊號DMIOPRE0WRT，係當在進行寫入動作時而進行主IO線 對MIO之預充電的情況時被活性化。列控制電路26，由於係為接收電源電位VDD而動作的電路，因此預充電訊號DMIOPRE0WRT之電位準位亦係成為電源電位VDD。 The precharge signal DIOOPRE0WRT is a high active signal supplied from the column control circuit 26 shown in FIG. 1 to the write precharge circuit 50. The pre-charge signal DMIOPRE0WRT is used to perform the main IO line while the write operation is being performed. The case of precharging the MIO is activated. Since the column control circuit 26 is a circuit that operates to receive the power supply potential VDD, the potential level of the precharge signal DMIOPRE0WRT also becomes the power supply potential VDD.
預充電訊號DMIOPRE0RDB以及均衡訊號DMIOEQ0B，係分別為從圖1中所示之列控制電路26所供給至讀取用預充電電路51處之低啟動(low active)之訊號。此些係均為當在進行讀取動作時而進行主IO線對MIO之預充電的情況時被活性化。預充電訊號DMIOPRE0RDB以及均衡訊號DMIOEQ0B之各別的電位準位，係亦與預充電訊號DMIOPRE0WRT相同的，而身為電源電位VDD。 The precharge signal DMIOPRE0RDB and the equalization signal DMIOEQ0B are respectively low active signals supplied from the column control circuit 26 shown in FIG. 1 to the read precharge circuit 51. These are all activated when the main IO line pair MIO is precharged while the read operation is being performed. The respective potential levels of the precharge signal DMIOPRE0RDB and the equalization signal DMIOEQ0B are also the same as the precharge signal DMIOPRE0WRT, and are the power supply potential VDD.
均衡訊號DRAEQB，係為從圖1中所示之列控制電路26所供給至寫入用預充電電路54處之低啟動(low active)之訊號。均衡訊號DRAEQB，亦係為當在進行讀取動作時而進行主IO線對MIO之預充電的情況時被活性化。均衡訊號DRAEQB之電位準位，亦係為電源電位VDD。 The equalization signal DRAEQB is a low active signal supplied from the column control circuit 26 shown in FIG. 1 to the write precharge circuit 54. The equalization signal DRAEQB is also activated when the main IO line pair MIO is precharged during the read operation. The potential level of the equalization signal DRAEQB is also the power supply potential VDD.
主IO線選擇訊號DRATG0B，係為從圖1中所示之列控制電路26所供給至主IO線選擇開關53處之低啟動(low active)之訊號。主IO線選擇訊號DRATG0B，係為當進行讀取動作時而將主IO線對MIO與資料控制電路34作連接的情況時，而被活性化。主IO線選擇訊號DRATG0B之電位準位，亦係為電源電位VDD。 The main IO line select signal DRATG0B is a low active signal supplied from the column control circuit 26 shown in FIG. 1 to the main IO line select switch 53. The main IO line selection signal DRATG0B is activated when the main IO line pair MIO is connected to the data control circuit 34 when the reading operation is performed. The potential level of the main IO line selection signal DRATG0B is also the power supply potential VDD.
以下，針對關連於主IO線對MIO所設置的 各電路之構成以及接收有上述之各訊號的各電路之動作作說明。 Below, for the MIO set for the main IO line The configuration of each circuit and the operation of each circuit that receives each of the above signals will be described.
首先，寫入驅動器52，係包含有：電晶體T1(第1電晶體)，係使其中一端與主IO線MIOB作連接，並於另外一端處被供給有電源電位VDD(第1電源電位)；和電晶體T2(第2電晶體)，係使其中一端與主IO線MIOT作連接，並於另外一端處被供給有電源電位VDD；和電晶體T3(第3電晶體)，係使其中一端與主IO線MIOB作連接，並於另外一端處被供給有接地電位VSS(第2電源電位)；和電晶體T4(第4電晶體)，係使其中一端與主IO線MIOT作連接，並於另外一端處被供給有接地電位VSS，而構成之。 First, the write driver 52 includes a transistor T1 (first transistor), and one end thereof is connected to the main IO line MIOB, and the other end is supplied with a power supply potential VDD (first power supply potential). And the transistor T2 (the second transistor), one end of which is connected to the main IO line MIOT, and the other end is supplied with the power supply potential VDD; and the transistor T3 (the third transistor), One end is connected to the main IO line MIOB, and the other end is supplied with a ground potential VSS (second power supply potential); and the transistor T4 (fourth transistor) is connected to the main IO line MIOT. It is configured to be supplied with a ground potential VSS at the other end.
電晶體T1~T4之各別的ON、OFF狀態，係藉由控制電路55而被作控制。控制電路55，係構成為基於資料DWBSLT來對於電晶體T1~T4之各別的ON、OFF狀態作控制。 The respective ON and OFF states of the transistors T1 to T4 are controlled by the control circuit 55. The control circuit 55 is configured to control the respective ON and OFF states of the transistors T1 to T4 based on the data DWBSLT.
若是作具體性說明，則控制電路55，係以將資料DWBSLT、資料遮罩訊號DWDMLB以及寫入致能訊號DWAED0T之邏輯積訊號供給至電晶體T1、T2的閘極電極處並且將資料DWBSLT之反轉訊號、資料遮罩訊號DWDMLB以及寫入致能訊號DWAED0T之邏輯積訊號供給至電晶體T3、T4之閘極電極處的方式，而構成之。另外，控制電路55係為接收電源電位VDD而動作的電路，因此，此些之邏輯積訊號的電位準位亦係成為電源電位 VDD。 For specific description, the control circuit 55 supplies the logical product signals of the data DWBSLT, the data mask signal DWDMLB, and the write enable signal DWAED0T to the gate electrodes of the transistors T1 and T2 and the data DWBSLT. The reverse signal, the data mask signal DWDMLB, and the logic signal of the write enable signal DWAED0T are supplied to the gate electrodes of the transistors T3 and T4, and are formed. In addition, the control circuit 55 is a circuit that operates to receive the power supply potential VDD. Therefore, the potential level of the logic product signal is also the power supply potential. VDD.
藉由此，以資料遮罩訊號DWDMLB以及寫入致能訊號DWAED0T均被活性化一事作為條件，當資料DWBSLT係身為HIGH(第1值)的情況時，電晶體T2、T3係成為ON，電晶體T1、T4係成為OFF。故而，主IO線MIOT係成為HIGH準位，主IO線MIOB係成為LOW準位。另一方面，當資料DWBSLT係身為LOW(第2值)的情況時，電晶體T2、T3係成為OFF，電晶體T1、T4係成為ON。故而，主IO線MIOT係成為LOW準位，主IO線MIOB係成為HIGH準位。當資料遮罩訊號DWDMLB以及寫入致能訊號DWAED0T之至少其中一方係身為非活性時，電晶體T1~T4係均成為OFF，從寫入驅動器52所對於主IO線對MIO之電壓供給係被停止。 Therefore, the data mask signal DWDMLB and the write enable signal DWAED0T are both activated. When the data DWBSLT is HIGH (first value), the transistors T2 and T3 are turned ON. The transistors T1 and T4 are turned OFF. Therefore, the main IO line MIOT is at the HIGH level, and the main IO line MIOB is at the LOW level. On the other hand, when the data DWBSLT is LOW (second value), the transistors T2 and T3 are turned off, and the transistors T1 and T4 are turned ON. Therefore, the main IO line MIOT becomes the LOW level, and the main IO line MIOB becomes the HIGH level. When at least one of the data mask signal DWDMLB and the write enable signal DWAED0T is inactive, the transistors T1 to T4 are turned OFF, and the voltage supply from the write driver 52 to the main IO line pair MIO is aborted.
作為電晶體T1~T4，具體而言，係使用NMOS。其結果，從寫入驅動器52所供給至主IO線對MIO處之HIGH準位的電位，係成為較電源電位VDD而更低之電位(第1電位)，LOW準位之電位係成為接地電位VSS。 As the transistors T1 to T4, specifically, an NMOS is used. As a result, the potential of the HIGH level supplied from the write driver 52 to the main IO line pair MIO is lower than the power supply potential VDD (first potential), and the potential of the LOW level is the ground potential. VSS.
HIGH準位之電位成為較電源電位VDD而更低之電位的原因，係為起因於上述之NMOS之性質所導致者。亦即是，如同上述一般，為了使NMOS成為ON，閘極-源極間之電位差係有必要成為臨限值電壓Vth以上。又，被供給至電晶體T1、T2之閘極電極處的訊號之電位準位，係均如同上述一般而身為電源電位VDD。此事， 係代表著無法將主IO線MIOB、MIOT之電位設為較VDD-Vth而更大之值。故而，從寫入驅動器52所供給至主IO線對MIO處之HIGH準位的電位，係成為較電源電位VDD而更降低了電晶體T1、T2之臨限值電壓Vth的量之電位。 The reason why the potential of the HIGH level becomes a potential lower than the power supply potential VDD is due to the nature of the NMOS described above. That is, as described above, in order to turn the NMOS ON, the potential difference between the gate and the source is required to be equal to or higher than the threshold voltage Vth. Further, the potential levels of the signals supplied to the gate electrodes of the transistors T1 and T2 are all the power supply potential VDD as described above. This matter, It means that the potential of the main IO lines MIOB and MIOT cannot be set to be larger than VDD-Vth. Therefore, the potential of the HIGH level supplied from the write driver 52 to the main IO line pair MIO is the potential which is lower than the power supply potential VDD by the threshold voltage Vth of the transistors T1 and T2.
如此這般，從寫入驅動器52所供給至主IO線對MIO處之HIGH準位的電位，係成為較電源電位VDD而更低之電位VDD-Vth，藉由此，主IO線對MIO之間的電位差，最大值係成為VDD-Vth-VSS。相對於此，假設若是將電晶體T1、T2藉由PMOS來構成，則由於係並不會產生上述一般之主IO線MIOB、MIOT之電位的上限值，因此，主IO線對MIO之間的電位差之最大值係成為VDD-VSS。故而，由於若依據由本實施形態所致之半導體裝置1，則相較於將電晶體T1、T2藉由PMOS來構成的情況，係成為能夠減少在將寫入資料寫入至主IO線對MIO中時的充放電電流，因此，可以說係能夠實現半導體裝置1之構成中的關連於對於記憶體胞之資料寫入的部份之低消耗電力化。 In this manner, the potential supplied from the write driver 52 to the HIGH level at the main IO line pair MIO is a potential VDD-Vth lower than the power supply potential VDD, whereby the main IO line pair MIO The potential difference between the two is VDD-Vth-VSS. On the other hand, if the transistors T1 and T2 are configured by PMOS, the upper limit of the potential of the above-described general main IO lines MIOB and MIOT does not occur, so that the main IO line is between the MIOs. The maximum value of the potential difference is VDD-VSS. Therefore, according to the semiconductor device 1 of the present embodiment, it is possible to reduce the writing of the write data to the main IO line pair MIO as compared with the case where the transistors T1 and T2 are formed of PMOS. In the middle of the charge and discharge current, it can be said that the low power consumption of the portion of the semiconductor device 1 that is related to the writing of the data to the memory cell can be realized.
接著，寫入用預充電電路50，係構成為包含有：電晶體T5(第5電晶體)，係使其中一端被與主IO線MIOB作連接，並於另外一端處被供給有電源電位VDD；和電晶體T6(第6電晶體)，係使其中一端被與主IO線MIOT作連接，並於另外一端處被供給有電源電位VDD。 Next, the pre-charging circuit 50 for writing is configured to include a transistor T5 (fifth transistor) such that one end thereof is connected to the main IO line MIOB, and the other end is supplied with a power supply potential VDD. And the transistor T6 (the sixth transistor) is such that one end thereof is connected to the main IO line MIOT, and the other end is supplied with the power supply potential VDD.
電晶體T5、T6之各別的ON、OFF狀態，係藉由預充電訊號DMIOPRE0WRT而被作控制。預充電訊號DMIOPRE0WRT，係被共通性地供給至電晶體T5、T6之閘極電極處，故而，電晶體T5、T6係以相互成為同一之ON、OFF狀態的方式而被作控制。 The respective ON and OFF states of the transistors T5 and T6 are controlled by the precharge signal DMIOPRE0WRT. The precharge signals DIOOPRE0WRT are commonly supplied to the gate electrodes of the transistors T5 and T6. Therefore, the transistors T5 and T6 are controlled so as to be in the same ON and OFF states.
作為電晶體T5、T6，亦係使用NMOS。其結果，與寫入驅動器52相同的，從寫入用預充電電路50所供給至主IO線對MIO處之HIGH準位的電位(預充電電位)，係成為較電源電位VDD而更低之電位(第1電位)，具體而言，係成為VDD-Vth。故而，由於係能夠減少在預充電中所耗費之主IO線對MIO的充放電電流，因此，從此觀點來看，若依據由本實施形態所致之半導體裝置1，則亦可以說能夠實現半導體裝置1之構成中的關連於對於記憶體胞之資料寫入的部份之低消耗電力化。 As the transistors T5 and T6, an NMOS is also used. As a result, similarly to the write driver 52, the potential (precharge potential) supplied from the write precharge circuit 50 to the HIGH level at the main IO line pair MIO is lower than the power supply potential VDD. The potential (first potential) is specifically VDD-Vth. Therefore, since the charge/discharge current of the main IO line to the MIO consumed in the precharge can be reduced, from this point of view, according to the semiconductor device 1 of the present embodiment, it can be said that the semiconductor device can be realized. The structure of 1 is related to the low power consumption of the portion written to the data of the memory cell.
接著，讀取用預充電電路51，係構成為包含有：電晶體T7(第7電晶體)，係使其中一端被與主IO線MIOB作連接，並於另外一端處被供給有電源電位VDD；和電晶體T8(第8電晶體)，係使其中一端被與主IO線MIOT作連接，並於另外一端處被供給有電源電位VDD。 Next, the read precharge circuit 51 is configured to include a transistor T7 (seventh transistor) such that one end thereof is connected to the main IO line MIOB, and the other end is supplied with the power supply potential VDD. And the transistor T8 (the eighth transistor) is such that one end thereof is connected to the main IO line MIOT, and the other end is supplied with the power supply potential VDD.
電晶體T7、T8之各別的ON、OFF狀態，係藉由預充電訊號DMIOPRE0RDB而被作控制。預充電訊號DMIOPRE0RDB，係被共通性地供給至電晶體T7、T8之閘極電極處，故而，電晶體T7、T8係以相互成為同一 之ON、OFF狀態的方式而被作控制。 The respective ON and OFF states of the transistors T7 and T8 are controlled by the precharge signal DMIOPRE0RDB. The precharge signal DMIOPRE0RDB is commonly supplied to the gate electrodes of the transistors T7 and T8, so that the transistors T7 and T8 are identical to each other. The ON and OFF states are controlled.
作為電晶體T7、T8，具體而言，係使用PMOS。在PMOS的情況中，由於係並不會產生如同NMOS一般之電位準位的上限值，因此，從讀取用預充電電路51所供給至主IO線對MIO處之HIGH準位的電位，係與寫入用預充電電路50相異，而成為電源電位VDD。如此這般地在讀取之情況和寫入之情況中而主IO線對MIO之預充電電位會有所改變的原因，係因為當進行讀取的情況時，為了藉由後段之資料控制電路34來確實地將讀取資料作讀取，係有必要將主IO線對MIO之間的電位差增大之故。 As the transistors T7 and T8, specifically, a PMOS is used. In the case of the PMOS, since the upper limit value of the potential level as the NMOS is not generated, the potential supplied from the read precharge circuit 51 to the HIGH level at the main IO line pair MIO is It is different from the write precharge circuit 50 and becomes the power supply potential VDD. The reason why the precharge potential of the main IO line pair MIO changes in the case of reading and writing in this way is because when the reading is performed, in order to control the circuit by the data of the latter stage In order to reliably read the read data, it is necessary to increase the potential difference between the main IO line and the MIO.
讀取用預充電電路51，係另外包含有：電晶體T13，係使其中一端與主IO線MIOB作連接，並使另外一端與主IO線MIOT作連接。電晶體T13，係亦為PMOS，在其之閘極電極處，係被供給有均衡訊號DMIOEQ0B。電晶體T13，係作為當均衡訊號DMIOEQ0B為活性化的情況時而用以將主IO線MIOB、MIOT之電位設為相同的均衡器而起作用。 The pre-charging circuit 51 for reading further includes a transistor T13, wherein one end thereof is connected to the main IO line MIOB, and the other end is connected to the main IO line MIOT. The transistor T13, which is also a PMOS, is supplied with an equalization signal DMIOEQ0B at its gate electrode. The transistor T13 functions as an equalizer for setting the potentials of the main IO lines MIOB and MIOT to be the same when the equalization signal DMIEOQ0B is activated.
讀取用預充電電路54，係具備有與讀取用預充電電路51相同之構成，但是，係在分別與電晶體T7、T8、T13相對應的電晶體T14、T15、T16之閘極電極處而共通性地被供給有均衡訊號DRAEQB，在此點上，係為相異。讀取用預充電電路54，係亦發揮有當均衡訊號DRAEQB為活性化的情況時而將主IO線MIOB、MIOT之 電位設為電源電位VDD的功能。 The read precharge circuit 54 has the same configuration as the read precharge circuit 51, but is a gate electrode of the transistors T14, T15, and T16 corresponding to the transistors T7, T8, and T13, respectively. The equalization signal DRAEQB is supplied in common, and at this point, it is different. The pre-charge circuit 54 for reading also functions to activate the main IO line MIOB, MIOT when the equalization signal DRAEQB is activated. The potential is set to the power supply potential VDD.
主IO線選擇開關53，係藉由被插入至主IO線MIOB中之寫入驅動器52和讀取用預充電電路54之間的部份處之電晶體T17、和被插入至主IO線MIOT中之寫入驅動器52和讀取用預充電電路54之間的部份處之電晶體T18，而構成之。電晶體T17、T18係均為PMOS，在各別之閘極電極處，係被共通地供給有主IO線選擇訊號DRATG0B。藉由此，主IO線選擇開關53，當主IO線選擇訊號DRATG0B為活性化的情況時，係成為導通狀態，當並非如此的情況時，則係成為非導通狀態。故而，當主IO線選擇訊號DRATG0B為活性化的情況時，主IO線對MIO和資料控制電路34係被相互作連接，當主IO線選擇訊號DRATG0B成為非活性化的情況時，主IO線對MIO和資料控制電路34係被相互切離。 The main IO line selection switch 53 is inserted into the main IO line MIOT by the transistor T17 inserted between the write driver 52 and the read precharge circuit 54 in the main IO line MIOB, and the main IO line MIOT. The transistor T18 at a portion between the write driver 52 and the read precharge circuit 54 is formed. The transistors T17 and T18 are all PMOS, and the main IO line selection signal DRATG0B is commonly supplied to each of the gate electrodes. As a result, the main IO line selection switch 53 is turned on when the main IO line selection signal DRATG0B is activated, and when it is not the case, it is in a non-conduction state. Therefore, when the main IO line selection signal DRATG0B is activated, the main IO line pair MIO and the data control circuit 34 are connected to each other, and when the main IO line selection signal DRATG0B is inactivated, the main IO line The MIO and data control circuits 34 are separated from each other.
圖4，係為對於在由本實施形態所致之半導體裝置1中而依序進行了讀取動作、寫入動作以及讀取用預充電動作的情況時之主IO線MIOB、MIOT的各別之電位VMIOB、VMIOT的變化之其中一例作展示之圖。在此例所示之寫入動作中，係被叢發輸入有代表6個「1」之寫入資料和代表2個「0」的寫入資料。 4 is a diagram showing the respective main IO lines MIOB and MIOT when the read operation, the write operation, and the read precharge operation are sequentially performed in the semiconductor device 1 according to the present embodiment. One of the changes in the potentials V MIOB and V MIOT is shown in the figure. In the write operation shown in this example, a write data representing six "1"s and a write data representing two "0"s are input by the burst.
如圖4中所示一般，讀取動作時之電位VMIOB、VMIOT，係在電源電位VDD和接地電位VSS之間而變動，其變動幅度係為VDD-VSS。另一方面，寫入動作時之電位VMIOB、VMIOT，係在電源電位VDD-Vth和接 地電位VSS之間而變動，其變動幅度係為VDD-Vth-VSS。另外，Vth係為圖3中所示之電晶體T1、T2、T5、T6的臨限值電壓。故而，可以說，在由本實施形態所致之半導體裝置1中，係能夠實現將寫入動作時之主IO線對MIO之間的電位差之最大值相較於讀取動作時而作Vth之量的縮小。 As shown in FIG. 4, in general, the potentials V MIOB and V MIOT at the time of the read operation fluctuate between the power supply potential VDD and the ground potential VSS, and the fluctuation range is VDD-VSS. On the other hand, the potentials V MIOB and V MIOT at the time of the write operation fluctuate between the power supply potential VDD-Vth and the ground potential VSS, and the fluctuation range is VDD-Vth-VSS. Further, Vth is a threshold voltage of the transistors T1, T2, T5, and T6 shown in FIG. Therefore, in the semiconductor device 1 of the present embodiment, it can be realized that the maximum value of the potential difference between the main IO line pair MIO at the time of the write operation is compared with the Vth amount at the time of the read operation. The reduction.
又，如圖4中所示一般，讀取用預充電動作時之電位VMIOB、VMIOT，係為電源電位VDD。另一方面，雖並未圖示，但是，寫入用預充電動作時之電位VMIOB、VMIOT，係成為電源電位VDD-Vth。故而，可以說，在由本實施形態所致之半導體裝置1中，係能夠實現將寫入動作時之主IO線對MIO的預充電電位相較於讀取動作時而作Vth之量的縮小。 Further, as shown in FIG. 4, in general, the potentials V MIOB and V MIOT at the time of the precharge operation for reading are the power supply potential VDD. On the other hand, although not shown, the potentials V MIOB and V MIOT at the time of the precharge operation for writing are the power supply potential VDD-Vth. Therefore, in the semiconductor device 1 of the present embodiment, it can be realized that the amount of Vth of the main IO line pair MIO during the address operation is reduced by Vth compared to the case of the read operation.
如同以上所說明一般，若依據由本實施形態所致之半導體裝置1，則在寫入動作時之主IO線對MIO之間的電位差之最大值，係成為等於電位差VDD-Vth-VSS。故而，相較於寫入動作時之主IO線對MIO之間的電位差之最大值為等於電源電位VDD和接地電位VSS之差VDD-VSS的情況，由於伴隨著寫入資料之切換所流動的主IO線對MIO之充放電電流係能夠成為少量，因此可以說係能夠實現半導體裝置1之低消耗電力化。 As described above, according to the semiconductor device 1 of the present embodiment, the maximum value of the potential difference between the main IO line pair MIO at the time of the write operation is equal to the potential difference VDD-Vth-VSS. Therefore, the maximum value of the potential difference between the main IO line pair MIO at the time of the write operation is equal to the difference VDD-VSS between the power supply potential VDD and the ground potential VSS, which is caused by the switching of the write data. Since the charge and discharge current of the main IO line to the MIO can be made small, it can be said that the semiconductor device 1 can be reduced in power consumption.
針對寫入動作時之主IO線對MIO之間的電位差之最大值為VDD-Vth-VSS的情況(〔A〕)和為VDD-VSS的情況(〔B〕)的各者，而對於主IO線對 MIO之充放電電流作了測定，並將結果展示於表1中。另外，在表1中，係針對下述之情況的充放電電流之積算值作展示：亦即是，係使用2.4Gbps/fast model/-5C之DRAM，並將電源電壓VDD設為1.3V，而在此條件下，將8位元之寫入資料的連續寫入(X8)和16位元之寫入資料的連續寫入(X16)分別重複了既定之次數。根據表1之結果，可以理解到，藉由採用由本實施形態所致之半導體裝置1的構成，主IO線對MIO之充放電電流係成為僅需要少量即可。 For the case where the maximum value of the potential difference between the main IO line pair MIO at the time of the write operation is VDD-Vth-VSS ([A]) and the case of VDD-VSS ([B]), for the main IO line pair The charge and discharge currents of MIO were measured and the results are shown in Table 1. In addition, in Table 1, the integrated calculation of the charge and discharge current in the following cases is shown: that is, the DRAM of 2.4 Gbps/fast model/-5C is used, and the power supply voltage VDD is set to 1.3V. Under this condition, the continuous write (X8) of the 8-bit write data and the continuous write (X16) of the 16-bit write data are respectively repeated for a predetermined number of times. According to the results of Table 1, it can be understood that by using the configuration of the semiconductor device 1 according to the present embodiment, the charge and discharge current of the main IO line pair MIO is only required to be small.
又，若依據由本實施形態所致之半導體裝置1，則由於在進行寫入動作時之預充電電位係成為VDD-Vth，因此，相較於係成為電源電位VDD的情況，於進行寫入動作之預充電時所消耗的電力亦有所降低。另一方面，關於讀取動作時之預充電電位，由於係與先前技術相同的而維持於電源電位VDD，因此係成為能夠確實地進行讀取動作。 Further, according to the semiconductor device 1 of the present embodiment, since the precharge potential is VDD-Vth during the address operation, the write operation is performed as compared with the case where the power supply potential VDD is applied. The power consumed during pre-charging is also reduced. On the other hand, since the precharge potential at the time of the read operation is maintained at the power supply potential VDD as in the prior art, the read operation can be surely performed.
接著，由本發明之第2實施形態所致之半導體裝置1，係如同圖5中所示一般，將供給至寫入用預充電電路50、讀取用預充電電路51、寫入驅動器52以及讀取用預充電電路54的各者處之電源電位VDD改變為陣列 電位VARY，在此點上，係與由第1實施形態所致之半導體裝置1相異。在其他構成上，由於係與由第1實施形態所致之半導體裝置1相同，因此，以下係注目於相異點而作說明。 Next, the semiconductor device 1 according to the second embodiment of the present invention is supplied to the write precharge circuit 50, the read precharge circuit 51, the write driver 52, and the read as shown in FIG. The power supply potential VDD at each of the precharge circuits 54 is changed to an array The potential VARY is different from the semiconductor device 1 according to the first embodiment in this point. The other configuration is the same as that of the semiconductor device 1 according to the first embodiment. Therefore, the following description focuses on the differences.
如同上述一般，陣列電位VARY係為較電源電位VDD而更低之電位準位的電位。藉由此，若依據由本實施形態所致之半導體裝置1，則相較於由第1實施形態所致之半導體裝置1，係能夠實現更進一步之低消耗電力化。以下，列舉出具體例來作說明。 As described above, the array potential VARY is a potential lower than the potential of the power supply potential VDD. As a result, according to the semiconductor device 1 of the first embodiment, it is possible to achieve further reduction in power consumption compared to the semiconductor device 1 according to the first embodiment. Hereinafter, specific examples will be described.
圖6，係為針對由第1實施形態(Em.1)所致之半導體裝置1和由第2實施形態(Em.2)所致之半導體裝置1的各者，而對於主IO線MIOB、MIOT之各者的電位VMIOB、VMIOT之變化和流入至主IO線MIOB、MIOT中之電流I的變化作了測定的結果，而作展示之圖。該圖之測定，亦同樣的，係為使用2.4Gbps/fast model/-5C之DRAM，並在將電源電壓VDD設為1.3V的條件下而進行者。陣列電壓VARY，係為1.0V。 6 is a main IO line MIOB for each of the semiconductor device 1 according to the first embodiment (Em. 1) and the semiconductor device 1 according to the second embodiment (Em. 2). each of those Miot potential V MIOB, the sum variation V MIOT flows to the main line IO MIOB, the result of the current change I in the Miot were measured, and for the display of FIG. Similarly, the measurement of this figure was performed using a DRAM of 2.4 Gbps/fast model/-5C, and the power supply voltage VDD was set to 1.3 V. The array voltage VARY is 1.0V.
如同圖6中所示一般，在由本實施形態所致之半導體裝置1中，於寫入動作時之主IO線對MIO之間的電位差之最大值，相較於由第1實施形態所致之半導體裝置1，係成為更些許小。又，寫入動作時之預充電電位係為1.0V，相較於由第1實施形態所致之半導體裝置1的1.3V，係降低了0.3V。其結果，在由本實施形態所致之半導體裝置1中，如同圖6中所示一般，相較於由第1 實施形態所致之半導體裝置1，電流I係作了約5%之削減。 As shown in FIG. 6, in the semiconductor device 1 according to the present embodiment, the maximum value of the potential difference between the main IO line pair MIO at the time of the write operation is compared with that of the first embodiment. The semiconductor device 1 is made even smaller. Further, the precharge potential at the time of the write operation was 1.0 V, which was 0.3 V lower than the 1.3 V of the semiconductor device 1 according to the first embodiment. As a result, in the semiconductor device 1 according to the present embodiment, as shown in FIG. 6, it is compared with the first In the semiconductor device 1 according to the embodiment, the current I was reduced by about 5%.
如此這般，若依據由本實施形態所致之半導體裝置1，則藉由對於寫入用預充電電路50以及寫入驅動器52供給陣列電位VARY，相較於由第1實施形態所致之半導體裝置1，係成為能夠將寫入動作時之主IO線對MIO的充放電電流降低。同樣的，藉由對於讀取用預充電電路51、54供給陣列電位VARY，不僅是在寫入動作時，在讀取動作時亦成為能夠將主IO線對MIO的充放電電流降低。故而，係成為能夠實現更進一步之低消耗電力化。 As described above, according to the semiconductor device 1 of the present embodiment, the array potential VARY is supplied to the write precharge circuit 50 and the write driver 52, compared to the semiconductor device according to the first embodiment. 1, it is possible to reduce the charge/discharge current of the main IO line to MIO during the write operation. Similarly, by supplying the array potential VARY to the read precharge circuits 51 and 54, the charge/discharge current of the main IO line pair MIO can be reduced not only during the write operation but also during the read operation. Therefore, it is possible to achieve further reduction in power consumption.
以上，雖針對本發明之理想實施形態作了說明，但是本發明係並不限定於上述之實施形態，不用說，在不脫離本發明之主旨的範圍內，係可進行各種之變更，且該些亦係為被包含於本發明之範圍內。 Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the spirit and scope of the invention. These are also included in the scope of the present invention.
例如，在上述各實施形態中，雖係針對將本發明適用在DRAM之主IO線對MIO中的情況為例來作了說明，但是，本發明係並不被限定於DRAM之主IO線對MIO，而能夠廣泛地適用於有必要降低充放電電流之資料線對中。 For example, in each of the above embodiments, the case where the present invention is applied to the main IO line pair MIO of the DRAM has been described as an example. However, the present invention is not limited to the main IO line pair of the DRAM. MIO can be widely applied to data line pairs where it is necessary to reduce the charge and discharge current.
又，在上述各實施形態中，雖係藉由將電晶體T1、T2、T5、T6設為NMOS，來實現了低消耗電力化，但是，只要是能夠在成為ON時而將較被供給至汲極處之電壓的電位準位而更低之電位供給至所對應之資料線 處即可，而並非絕對需要身為NMOS。例如，代替NMOS，係亦可使用N通道型MISFET等。 In addition, in each of the above-described embodiments, the transistors T1, T2, T5, and T6 are NMOS, and the power consumption is reduced. However, if the power is turned ON, the battery can be supplied to the battery. The potential level of the voltage at the drain is supplied to the corresponding data line at a lower potential It's all right, and it's not absolutely necessary to be an NMOS. For example, instead of the NMOS, an N-channel type MISFET or the like can be used.
50‧‧‧寫入用預充電電路 50‧‧‧Precharging circuit for writing
51、54‧‧‧讀取用預充電電路 51, 54‧‧‧Precharge circuit for reading
52‧‧‧寫入驅動器 52‧‧‧Write driver
53‧‧‧主IO線選擇開關 53‧‧‧Main IO line selector switch
55‧‧‧控制電路 55‧‧‧Control circuit
MIO‧‧‧主IO線對 MIO‧‧‧Main IO line pair
MIOB、MIOT‧‧‧主IO線 MIOB, MIOT‧‧‧ main IO line
T1~T6‧‧‧N通道型MOSFET T1~T6‧‧‧N channel MOSFET
T7、T8、T13~T16‧‧‧P通道型MOSFET T7, T8, T13~T16‧‧‧P channel MOSFET
T17、T18‧‧‧PMOS電晶體 T17, T18‧‧‧ PMOS transistor
VDD‧‧‧電源電位 VDD‧‧‧ power supply potential
VSS‧‧‧接地電位 VSS‧‧‧ Ground potential
DRAEQB‧‧‧均衡訊號 DRAEQB‧‧‧Equilibrium signal
DRATG0B‧‧‧主IO線選擇訊號 DRATG0B‧‧‧Main IO line selection signal
DMIOPRE0RDB‧‧‧預充電訊號 DMIOPRE0RDB‧‧‧Precharge signal
DMIOPRE0WRT‧‧‧預充電訊號 DMIOPRE0WRT‧‧‧Precharge signal
DMIOEQ0B‧‧‧均衡訊號 DMIOEQ0B‧‧‧Equilibrium signal
DWAED0T‧‧‧寫入致能訊號 DWAED0T‧‧‧Write enable signal
DWDMLB‧‧‧資料遮罩訊號 DWDMLB‧‧‧Material Mask Signal
DWBSLT‧‧‧資料訊號 DWBSLT‧‧‧Information Signal
Claims (11)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013111215A JP2014229338A (en) | 2013-05-27 | 2013-05-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201513112A true TW201513112A (en) | 2015-04-01 |
Family
ID=51988578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103117492A TW201513112A (en) | 2013-05-27 | 2014-05-19 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2014229338A (en) |
| TW (1) | TW201513112A (en) |
| WO (1) | WO2014192542A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7088542B2 (en) * | 2017-06-02 | 2022-06-21 | 北川工業株式会社 | Compositions for heat conductive materials and heat conductive materials |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0660658A (en) * | 1992-08-04 | 1994-03-04 | Fujitsu Ltd | Semiconductor storage device |
| JP3267436B2 (en) * | 1993-04-19 | 2002-03-18 | 三菱電機株式会社 | Semiconductor device |
| JP2000215669A (en) * | 1999-01-19 | 2000-08-04 | Mitsubishi Electric Corp | Semiconductor storage device |
| JP2000311489A (en) * | 1999-04-23 | 2000-11-07 | Fujitsu Ltd | Semiconductor memory |
| US6414897B1 (en) * | 2000-08-31 | 2002-07-02 | United Memories, Inc. | Local write driver circuit for an integrated circuit device incorporating embedded dynamic random access memory (DRAM) |
-
2013
- 2013-05-27 JP JP2013111215A patent/JP2014229338A/en not_active Withdrawn
-
2014
- 2014-05-14 WO PCT/JP2014/062791 patent/WO2014192542A1/en active Application Filing
- 2014-05-19 TW TW103117492A patent/TW201513112A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| JP2014229338A (en) | 2014-12-08 |
| WO2014192542A1 (en) | 2014-12-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8284593B2 (en) | Multi-port memory having a variable number of used write ports | |
| US8295101B2 (en) | Semiconductor device | |
| US9318158B2 (en) | Non-volatile memory using bi-directional resistive elements | |
| US7590003B2 (en) | Self-reference sense amplifier circuit and sensing method | |
| US20190304516A1 (en) | Apparatuses and methods for coupling data lines in memory devices | |
| US20040165462A1 (en) | Low-voltage sense amplifier and method | |
| US11349479B2 (en) | Input buffer circuit | |
| US9589608B2 (en) | Semiconductor memory device | |
| US10366764B2 (en) | Sense amplifier for detecting data read from memory cell | |
| TW200532688A (en) | Semiconductor storage device | |
| US20150078102A1 (en) | Nonvolatile semiconductor memory device and data transmission method | |
| EP3324410B1 (en) | Write assist circuit and method therefor | |
| US20090129175A1 (en) | Semiconductor storage device | |
| US6891763B1 (en) | Input buffer with differential amplifier | |
| TW201513112A (en) | Semiconductor device | |
| CN111312311B (en) | Apparatus and method of use for reducing write pull-up time | |
| US7339845B2 (en) | Memory device | |
| US10734060B2 (en) | Input buffer circuit | |
| JP2007134037A (en) | Semiconductor memory | |
| JP2016504705A (en) | Low power static random access memory | |
| KR101579958B1 (en) | Five transistor sram cell | |
| KR100991384B1 (en) | Semiconductor memory device and operation method thereof | |
| US7542341B2 (en) | MIS-transistor-based nonvolatile memory device with verify function | |
| CN117219136A (en) | Semiconductor device | |
| KR100687877B1 (en) | Active Core Voltage Driver Control Circuit |