CN101640482B - Electrification overshoot voltage inhibitor for power supply regulator - Google Patents
Electrification overshoot voltage inhibitor for power supply regulator Download PDFInfo
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- CN101640482B CN101640482B CN2008100436797A CN200810043679A CN101640482B CN 101640482 B CN101640482 B CN 101640482B CN 2008100436797 A CN2008100436797 A CN 2008100436797A CN 200810043679 A CN200810043679 A CN 200810043679A CN 101640482 B CN101640482 B CN 101640482B
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Abstract
The invention discloses an electrification overshoot voltage inhibitor for a power supply regulator, which comprises an error amplifier, an output driving tube, a feedback network, a source follower, a coupling capacitor and a current generation circuit, wherein the drain electrode of an input tube of the source follower is connected with an input voltage node, a grid electrode is connected with an output voltage node, and a source electrode is connected with a current loading tube of the current generation circuit; one end of the coupling capacitor is connected with the grid electrode of the output driving tube, and the other end of the coupling capacitor is connected with the output end of the source follower; and the current generation circuit comprises a current loading tube of the source follower, and the current loading tube is connected with the source electrode of the current loading tube and the coupling capacitor. The electrification overshoot voltage inhibitor has small circuit area and low power consumption, and the output voltage can accept any overshoot voltage regardless of the electrification speed of the input voltage node, so the integrated performance is improved; and no chip-outlaid capacitor is required, so the production cost is reduced effectively.
Description
Technical field
The present invention relates to a kind of chip power source apparatus that is applied to, be specifically related to a kind of voltage suppression device that is applied on the feed regulator isolator.
Background technology
At present, typically be that the feed regulator isolator block diagram of output driving element is as shown in Figure 1, comprising error amplifier, resistance-feedback network (R0 and R1) and output driving tube (transistor M0) with PMOS.Wherein reference voltage V REF generally offers a current potential accurately by voltage source accurately.
Circuit with Fig. 1 is an example, owing to power in moment, for example; Input voltage node has risen to 5V with the speed of 1V/ns from 0, and this moment, because the current potential that PGATE order also has little time rising; Thereby cause the gate source voltage of transistor M0 very high, high ten times of voltages during than operate as normal or higher, thereby difference between current seldom to be the drive current that needs in the practical application big 100 times or more; These unnecessary electric currents will be accumulated very high electric charge on the output node output voltage node; That is to say that very big overshoot voltage is arranged on output voltage node, might just equal input voltage node by overshoot voltage.Because need loop, make the gate source voltage of PMOS be operated in a normal magnitude of voltage through negative feedback.And the bandwidth of loop is common all in the magnitude of KHz, and therefore whole loop approximately needs us just can make output voltage node return to normal operating voltage from very high overshoot voltage to the magnitude of ms.Use the IP of the output of this voltage adjuster as power supply so, that suppose the IP use is the MOSFETs of low pressure 1.8V, just might make the device failure of these low pressure IP so in the process of overshoot from having to do not having.
Usually solve the output voltage overshoot several typical methods are arranged.First kind is to use big as far as possible Cout electric capacity, and Cout is big more, and output voltage node is just more little.Second method is to use electric voltage observation circuit, when monitoring output voltage when being higher than threshold voltage, just raises the gate source voltage of PMOS through extra circuit.The bandwidth of the feedback circuit that this is extra can be done very highly, does not have very big overshoot on the output voltage node thereby make.But, still have a little overshoot so on the output voltage node if the speed of input voltage node is higher than this extra feedback circuit response speed.The third method is the type that changes output element.
First method can increase very big chip area or need the external electric capacity of chip, influences production cost.Second method can only guarantee that the power supply electrifying process more than certain frequency overshoot voltage can not occur.The third simple output element that changes can cause under certain condition of work, can't realizing original performance.
Summary of the invention
Technical problem to be solved by this invention provides a kind of overshoot voltage restraining device that is applied to need not in the chip voltage adjuster of external capacitor.
In order to solve above technical problem, the invention provides a kind of overshoot voltage restraining device that powers on that is applied to feed regulator isolator, comprising: error amplifier, its in-phase end connects a reference voltage node, and its end of oppisite phase is connected with feedback network; The output driving tube, its source electrode connects input voltage node, and grid connects the output of error amplifier, and drain electrode is connected with output voltage node; Feedback network, the one of which end is connected with the error amplifier end of oppisite phase, and the other end is connected with output voltage node; Source follower, the drain electrode of its input pipe links to each other with input voltage node, and grid links to each other with output voltage node, and source electrode links to each other with the current loading pipe of current generating circuit; Coupling capacitance, the one of which end connects the grid of output driving tube, and the other end connects the output of source follower; Current generating circuit comprises the current loading pipe of source follower, and said current loading pipe links to each other with the source electrode and the coupling capacitance of source follower.
Beneficial effect of the present invention is that circuit area is little, and is low in energy consumption, and no matter input voltage node powers on speed how soon, and output voltage does not have unacceptable overshoot voltage and occurs, thereby is very helpful to improving overall performance; Need not the external electric capacity of chip simultaneously, effectively reduce production costs.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
Fig. 1 is existing typical voltage adjuster block diagram;
Fig. 2 is that the overshoot voltage of the embodiment of the invention suppresses circuit diagram;
Fig. 3 is the physical circuit figure of one embodiment of the invention;
Fig. 4 is the physical circuit figure of another embodiment of the present invention.
Embodiment
Voltage-regulating circuit structure among the present invention has mainly added transistor M1, current generating circuit I0 and coupling capacitance C0 on traditional circuit structure (as shown in Figure 1) (the appearance value of coupling capacitance C0 is bigger; The parasitic capacitance of bringing than transistor M0 and cabling etc. is big), as shown in Figure 2.Adopt the advantage of such scheme to be that area is little, low in energy consumption, and no matter input voltage node powers on speed how soon, does not occur being very helpful to improving overall performance thereby output voltage does not have unacceptable overshoot voltage.
Whole overshoot voltage suppresses circuit and is divided into 3 parts:
1) current generating circuit, 9 transistor M3 ~ transistor M11 in the left side among Fig. 3, capacitor C 2 and resistance R 4; Concrete connected mode is used for producing bias voltage and setovers 2 shown in figure) the grid current potential of transistor M2 pipe, and can control voltage settling time very easily through C2, just, electric current settling time.
2) source follower circuit (or claiming current potential translation circuit), the transistor M1 among Fig. 3, transistor M2.Wherein, Transistor M1 is as the input pipe of source follower, and drain electrode links to each other with input voltage node Vin, and grid links to each other with input voltage node Vout; Substrate links to each other with source electrode, and it act as and obtains the COUP current potential after an input voltage node Vout reduces a gate source voltage.Transistor M2 is as a current loading pipe.
3) coupling capacitance C0.Coupling capacitance C0 two ends are connected on respectively between the grid PGATE point and COUP of transistor M0.Mainly utilized the clock feedthrough characteristic of coupling capacitance C0 to make PGATE can not keep low level at powered on moment.
Like Fig. 2, shown in Figure 3, the overshoot voltage restraining device that powers on that is applied to feed regulator isolator according to the invention comprises: error amplifier, and its in-phase end connects reference voltage node, and its end of oppisite phase is connected with feedback network; The output driving tube uses the P transistor npn npn, and its source electrode connects input voltage node, and grid connects the output of error amplifier, and drain electrode is connected with output voltage node; Feedback network, the one of which end is connected with the error amplifier end of oppisite phase, and the other end is connected with output voltage node; Also comprise: the source follower input pipe, its drain electrode links to each other with input voltage node, and grid links to each other with output voltage node, and source electrode links to each other with the current loading pipe that current generating circuit provides; Coupling capacitance, the one of which end connects the grid of output driving tube, and the other end connects the output of source follower; Current generating circuit comprises the current loading pipe of source follower, and said current loading pipe links to each other with the source electrode and the coupling capacitance of source follower.Feedback network comprises resistance R 0 and resistance R 1, and resistance R 0 one ends connect output voltage node, and the other end connects error amplifier end of oppisite phase and resistance R 1; Resistance R 1 one ends connect error amplifier end of oppisite phase and resistance R 0, other end ground connection.The output branch road of current generating circuit is the current loading pipe, and its grid is connected with input voltage node, source ground, and drain electrode links to each other with the source electrode and the coupling capacitance of source follower.
The circuit operation principle is following:
Suppose that input power input voltage node Vin is 5V, output voltage node Vout is 1.8V, and VREF is 1V;
1) step signal of adding 1V/ns on input voltage node Vin
2) grid of powered on moment transistor M2 (BIAS) current potential is ' 0 ', and this moment, M2 was in not on-state.
3) powered on moment output voltage, just the grid potential of transistor M1 also is ' 0 ', the raceway groove of M1 is not opened.
4) drain electrode of M1 is connected with the input power supply, and all not in the time period of unlatching, the current potential of COUP is mainly by Cds at M1 and M2, and the clock feed-through effect of M1 (the drain-source parasitic capacitance of M1) determines.The time that moment powers on is short more, and the current potential that COUP is ordered is high more, and approaches supply voltage more.
5) existence of coupling capacitance C0 causes PGATE point current potential moment to rise to supply voltage or a little less than the current potential (depending primarily on the speed of powering on) of supply voltage.
6) BIAS point current potential is along with the foundation of current generating circuit is stablized (needing us level or longer settling time) gradually; When the BIAS current potential raises gradually, M2 has got into conducting state from off state, promptly has electric current above the M2; Then the COUP current potential is dragged down, and the PGATE current potential also just decreases.
7) transistor M0 uses the P transistor npn npn to M0 is opened when the PGATE current potential is low, and immediate current is just drawn high the Vout current potential.This moment, Vout probably can the highest being flushed to about 2V.Cause the output FB of feedback network higher than VREF voltage, this moment, the amplifier electric current charged to the PGATE point, and the PGATE current potential is risen, and M0 closes, and the last excess charges of Vout is mainly released by feedback network the Vout current potential is descended.Meanwhile, current loading is also ceaselessly being given the discharge of electric capacity bottom crown, and COUP point current potential is descended.In this process, can cause the Vout output voltage that less voltage fluctuation is arranged.
8) charging and discharging currents in amplifier discharges and recharges the C0 top crown in the dynamic equilibrium of the C0 bottom crown being discharged with the current loading pipe, and the COUP current potential descends (speed of decline is relevant with loop bandwidth) gradually, and source follower is set up gradually.Level when the current potential that last COUP is ordered drops to the source follower stable state.At this moment, whole loop settles out.Because the effect of source follower, the Vout current potential has also dropped to desirable 1.8V from 2V.
Circuit with Fig. 3 is an example, and no matter input voltage node Vin rises to high voltage with high arbitrarily speed from 0, and electric current I 0 always needs a period of time (~ 10us level) could be from 0 to desired value.So when input voltage node Vin powered on soon, COUP point current potential always was equal to or slightly lower than supply voltage (depend on the speed that powers on, speed is fast more, and COUP point current potential approaches supply voltage more).Since coupling capacitance C0 two terminal potentials can instantaneous variation characteristic; Cause PGATE point current potential; The gate voltage that is transistor M0 can not keep 0 current potential when input voltage node Vin moment raises, rise with almost equal speed but following input voltage node Vin.Thereby the drain-source current that guarantees transistor M0 can be very not big, do not exist thereby output voltage node Vout does not have intolerable overshoot voltage.
Shown in Figure 4 is the enforcement circuit of other a kind of electric current producing method, and this mode produces the electric current output effect same with current generating circuit shown in Figure 3.For current generating circuit of the present invention, multiple known other alternative implementation methods are arranged, here just for example with the simplest circuit.The key of this circuit be can be in fast powering-up reaction at once of current generating circuit, need to postpone a period of time could set up electric current, the circuit of its various concrete realizations should be thought and covered by current generating circuit according to the invention.
Claims (3)
1. overshoot voltage restraining device that powers on that is applied to feed regulator isolator comprises:
Error amplifier, its in-phase end connects reference voltage, and its end of oppisite phase is connected with feedback network;
The output driving tube, its source electrode connects input voltage, and grid connects the output of error amplifier, and drain electrode is as the output voltage output;
Feedback network, the one of which end is connected with the error amplifier end of oppisite phase, and the other end is connected with output voltage node;
It is characterized in that, also comprise:
Source follower, the drain electrode of its input pipe links to each other with input voltage node, and grid links to each other with output voltage node, and source electrode links to each other with the current loading pipe of current generating circuit;
Coupling capacitance, the one of which end connects the grid of output driving tube, and the other end connects the output of source follower;
Current generating circuit, its current loading pipe links to each other with the source electrode and the coupling capacitance of source follower.
2. the overshoot voltage restraining device that powers on that is applied to feed regulator isolator as claimed in claim 1; It is characterized in that; Said feedback network comprises resistance R 0 and resistance R 1, and resistance R 0 one ends connect output voltage node, and the other end connects error amplifier end of oppisite phase and resistance R 1; Resistance R 1 one ends connect error amplifier end of oppisite phase and resistance R 0, other end ground connection.
3. the overshoot voltage restraining device that powers on that is applied to feed regulator isolator as claimed in claim 1; It is characterized in that, the current loading Guan Weiyi current source of said current generating circuit, the one of which end links to each other with the source electrode of source follower; Other end ground connection is for source follower produces direct current biasing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100436797A CN101640482B (en) | 2008-07-31 | 2008-07-31 | Electrification overshoot voltage inhibitor for power supply regulator |
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| CN2008100436797A CN101640482B (en) | 2008-07-31 | 2008-07-31 | Electrification overshoot voltage inhibitor for power supply regulator |
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| CN101640482B true CN101640482B (en) | 2012-06-20 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103427617B (en) * | 2012-05-25 | 2016-05-04 | 原景科技股份有限公司 | Power circuit |
| TWI492016B (en) * | 2013-04-03 | 2015-07-11 | Holtek Semiconductor Inc | Low dropout linear regulator |
| CN107272794B (en) * | 2017-07-17 | 2018-10-12 | 无锡科技职业学院 | Suspension follows voltage-stabilized power supply circuit device |
| CN109164865B (en) * | 2018-11-23 | 2021-07-27 | 湖南国科微电子股份有限公司 | Overshoot protection circuit, linear voltage regulator and power module |
| CN114326890B (en) * | 2020-09-29 | 2023-04-07 | 圣邦微电子（北京）股份有限公司 | Voltage regulating circuit |
| CN113258536B (en) * | 2021-07-08 | 2021-10-01 | 上海芯龙半导体技术股份有限公司南京分公司 | Output overshoot suppression circuit and switching power supply chip |
| CN114253341B (en) * | 2021-12-22 | 2023-03-14 | 江苏集萃智能集成电路设计技术研究所有限公司 | Output circuit and voltage buffer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574577A (en) * | 2003-06-04 | 2005-02-02 | 罗姆股份有限公司 | Switching regulator |
| CN1722589A (en) * | 2004-07-02 | 2006-01-18 | 罗姆股份有限公司 | Power supply apparatus using synchronous rectified step-down converter |
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- 2008-07-31 CN CN2008100436797A patent/CN101640482B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574577A (en) * | 2003-06-04 | 2005-02-02 | 罗姆股份有限公司 | Switching regulator |
| CN1722589A (en) * | 2004-07-02 | 2006-01-18 | 罗姆股份有限公司 | Power supply apparatus using synchronous rectified step-down converter |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2005-168169A 2005.06.23 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131219 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20131219 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |