CN101577545A - Dual bootstrap and voltage compensation technology-based A/D converter sampling switch - Google Patents

Abstract

The invention discloses a dual bootstrap and voltage compensation technology-based A/D converter sampling switch, which comprises a primary switch unit used for a to-be-sampled signal channel to sample to-be-sampled signals, a underlayer voltage bootstrap unit for realizing the underlayer voltage bootstrap of a switching tube PMOS Switch in the primary switch unit, a grid voltage bootstrap unit for realizing the grid voltage bootstrap of the switching tube PMOS Switch in the primary switch unit, a storage unit for parallelly sampling input signals VIN and realizing the temporary storage of a VIN voltage, and a voltage compensation unit for compensating the sampling output voltage of an output end VOUT. The invention provides a sampling switch which is capable of working at low voltage and low power consumption and is insensitive to process errors. Meanwhile, the adopted voltage self-compensation method effectively solves a nonlinear problem caused by clock feedthrough occurring after the grid voltage bootstrap of the switching tube.

Description

A/D converter sampling switch based on dual bootstrap and voltage compensation technology

Technical field

The present invention relates to the Microelectronics and Solid State Electronics technical field, relate in particular to a kind of low-voltage high linearity A/D converter sampling switch based on dual bootstrap and voltage compensation technology.

Background technology

1. bootstrapped switch and accuracy limitations thereof

Analog digital A/D (Analog-to-Digital) transducer is the indispensable interface between analog signal and the digital signal in all electronic systems, and its conversion accuracy directly influences the indicators of overall performance of whole electronic system.

Current, in order to adapt to computer, communication and development of multimedia technology, A/D converter has all been made significant headway on technology, structure, performance, just towards low-power consumption, at a high speed, high-resolution direction develops.Sample circuit is as vital unit in the A/D converter, and the quality of its performance is the performance of decision whole system directly.Along with the raising of sampling clock frequency, the linearity of common CMOS sampling switch constantly descends, and has restricted the dynamic range of circuit; Simultaneously, because the decline of supply voltage, the input reference signal of common CMOS sampling switch is more and more littler, makes its application run into great difficulty.

We can say that traditional CMOS sampling switch structure can't satisfy the requirement of low voltage, high-speed high resolution A/D transducer to the sampled signal dynamic property.In order to address this problem, the bootstrapping sampling switch is suggested and extensive use as basic solution.

Fig. 1 is the circuit theory schematic diagram that utilizes the sampling switch of NMOS formation.Work as V _GateDuring for high voltage, switching tube conducting, sampling capacitance C _SCharge to V _IN, work as V _GateWhen low, sampling capacitance keeps sampled level, V _OUT=V _INIn actual applications, have certain conducting resistance after the conducting of NMOS pipe, its conducting equivalent resistance is:

$R_{\mathrm{ON}}=\frac{1}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}\frac{W}{L}(V_{\mathrm{Gate}}-V_{\mathrm{IN}}-V_{\mathrm{TH}})}---(1-1)$

Can find two problems from formula: the first, suppose the threshold voltage V of switch _THDuring for constant, R _ONBe one and input signal V _INRelevant nonlinear resistance, and this will cause the nonlinear distortion of output signal, for the occasion that sampling precision is had relatively high expectations, this distortion that sampling switch is introduced can't be ignored the influence of system accuracy; The second, have only as grid voltage V _GateWith source electrode input V _INDifference during greater than the threshold voltage of switch, switch could normally, this makes V _INValue must satisfy V _IN＜V _Gate-V _TH, this requirement can limit the scope of input signal greatly.

As shown in Figure 2, Fig. 2 is the circuit diagram of bootstrapping sampling switch under the conducting state.Bootstrapped switch shown in Figure 2 has provided solution at above problem, and its operation principle is: by MOS switch gate voltage is promoted a constant voltage, to eliminate the low excessively restriction of switch control voltage, the more important thing is that when switch conduction this also makes V _Gate-V _INBecome constant, thereby make R _ONConstant, solved conducting resistance with the problem that input signal changes, improved the linearity of switch.But,, must consider the bulk effect of MOS switching tube, i.e. V for the higher application of required precision _THNo longer be counted as constant, but obtain by following formula:

$V_{\mathrm{TH}}=V_{\mathrm{TH}0}+\mathrm{\γ}(\sqrt{|2{\mathrm{\φ}}_F+V_{\mathrm{SB}}|}-\sqrt{\left|2{\mathrm{\φ}}_F\right|})---(1-2)$

Wherein, V _TH0Be the intrinsic threshold voltage of metal-oxide-semiconductor, γ is a body-effect coefficient, Φ _FBeing Fermi level, all is constant.But because underlayer voltage V _BulkBe steady state value, so source-underlayer voltage V _SB=V _IN-V _BulkVariation will make V _THVariation with input voltage changes.In that the linearity is required in the high circuit, especially after the bootstrapping of having carried out grid voltage, this by V _THThe nonlinear change of introducing becomes the key factor of limited samples switched linear degree.

2. existing solution analysis

At present, the threshold voltage variation of the switch MOS pipe that the elimination bulk effect causes mainly contains two kinds of methods, illustrates and is analyzed as follows.

At first, first method is by changing the grid voltage V of nmos switch pipe _GateIn formula (1-1), in order to offset threshold voltage V _THVariation, except making V _GateIn comprise V _INVariation, also at V _GateThe middle introducing and V _THChange corresponding to component, i.e. V _GateCan be expressed as:

V _Gate＝V _TH+V _IN+c (1-3)

Wherein, C is a constant.Formula (1-3) is brought formula (1-1), R into _ONCan be rewritten as:

$R_{\mathrm{ON}}=\frac{1}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}\frac{W}{L}\·c}---(1-4)$

Like this, R _ONBecome and V _INIrrelevant steady state value.In theory, this method can be eliminated the non-linear of switch fully.But when reality realizes, how to make V _GateIn comprise V _THComponent be the difficult point place, as the implementation of classics, the scheme that the author proposes in the document [1] as shown in Figure 3, Fig. 3 offsets V for adopting _THThe circuit diagram of the bootstrapping sampling switch realized of method.

Suppose that M2 is the metal-oxide-semiconductor that duplicates M1 fully, the voltage that utilizes the short characteristic of void of operational amplifier to make A order equals V _A=V _INThereby, the voltage V that B is ordered _B=V _IN+ V _TH, and at Φ _PBootstrap capacitor C when closed _BootOn voltage be V _DD, this makes at switch Φ _SClosed, Φ _PDuring open circuit, the grid voltage V of switching tube M1 _GMI=V _B+ V _DD=V _IN+ V _TH+ V _DD, reached and the consistent requirement of formula (1-3).The conducting resistance of this scheme is

$R_{\mathrm{ON}}=\frac{1}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}\frac{W}{L}(V_{\mathrm{DD}}+\sqrt{I_{\mathrm{bias}}/\left(\frac{1}{2}{\mathrm{\μ}}_n{C}_{\mathrm{ox}}\frac{W}{L}\right)})}---(1-5)$

But there are the following problems for this scheme: at first, M2 can not duplicate the operating state of M1 pipe fully, because M2 always works in saturation condition, and the M1 pipe is being gone through a plurality of operating states under the effect of large-signal, simultaneously according to V _INAnd V _OUTRelation constantly change with signal, the problem that the source drain terminal exchanges can occur, and before final the shutoff, be operated in non-saturated region, this must make the V of two metal-oxide-semiconductors _THCan not be identical; Secondly, when considering short channel effect, V _THWith source-drain voltage V _DSRelevant, and the V of M1 and M2 _DSAnd inequality, will cause V _THCan be not identical; At last, also be unusual the important point, this scheme need be introduced amplifier, and will inevitably there be static working current in this, and complexity and power consumption that this has increased switch have greatly limited its range of application.

Secondly, another scheme is by offsetting V _THVariation with input signal solves the bulk effect problem, and operation principle is: the V in the freeze mode (1-2) _SBConstant, thus make V _THConstant.In formula (1-2), V _SB=V _IN-V _BulkBe unique amount that changes with input, if make underlayer voltage V _BulkAnd V _INEquate, so V _SB=0, V _THVariation with input is offset fully.Concrete enforcement is very simple, only needs substrate and input short circuit are got final product.But, under Current Standard CMOS technology, having only single trap is that the N trap exists, the P type substrate of NMOS pipe all links together, and can only get minimum voltage, so substrate can not be linked to each other with input, can only use the PMOS pipe replacement that is made in the N trap as switching tube, so just can be with the N type substrate separate connection of switching tube to input.Fig. 4 adopts the PMOS pipe to eliminate the circuit diagram of the bootstrapping sampling switch of bulk effect.

For this scheme, have following problem: at first, because input signal constantly changes, the source drain terminal of switching tube is distinguished indeterminate, and works as V _OUTDuring for the source end, if last time the level of sampling was far above this input signal, the situation that source electrode and substrate PN junction positively biased might occur occurs; Secondly, this scheme needs twice continuous gate voltage bootstrapping, the conducting of M4 need utilize the C2 bootstrapping to finish, the grid of switching tube MS could be by the required voltage of booting after this, this has reduced the speed limit of switch to a certain extent, add that the bootstrapping effect of C2 is subjected to the influence of parasitic capacitance and process deviation easily, make the practical effect of this scheme have a greatly reduced quality.

In addition, although more than two kinds of schemes eliminated to a certain extent by conducting resistance introduce non-linear, all ignored for bootstrapping back bootstrap voltage mode clock feedthrough will introduce new non-linear.This is because in bootstrapped switch, and except electric charge injects, the MOS switch also can be coupled to the clock saltus step on the sampling capacitance by overlap capacitance, is example with the basic circuit among Fig. 2, supposes grid and source electrode and leak level to have overlap capacitance C _OV, as shown in Figure 5, Fig. 5 bursts for clock and leads to the principle schematic that error produces.Error can be expressed as [3]

$\mathrm{\ΔV}=\mathrm{\Δ}{V}_{\mathrm{Gate}}\frac{{\mathrm{WC}}_{\mathrm{OV}}}{{\mathrm{WC}}_{\mathrm{OV}}+C_S}---(1-6)$

After grid voltage was booted, the variable quantity of grid voltage was

ΔV _Gate＝V _IN+V _DD-V _SS(1-7)

Therefore, formula (1-6) can be expressed as

$\mathrm{\ΔV}=V_{\mathrm{IN}}\frac{{\mathrm{WC}}_{\mathrm{OV}}}{{\mathrm{WC}}_{\mathrm{OV}}+C_S}+(V_{\mathrm{DD}}-V_{\mathrm{SS}})\frac{{\mathrm{WC}}_{\mathrm{OV}}}{{\mathrm{WC}}_{\mathrm{OV}}+C_S}---(1-8)$

In this expression formula, back one is DC terms, does not introduce nonlinearity erron, and not within the scope of paying close attention to, but last relevant with input signal, shows as gain error, believes with number linking to each other closely with importing.

As seen, clock logical the making of bursting new nonlinearity erron factor occurred after the gate voltage bootstrapping.In the application of high-speed, high precision, the size of switch MOS pipe is generally bigger, and the influence of parasitic capacitance is also more remarkable, and clock is burst and led to the source that will become new nonlinear distortion, and existing bootstrapped switch scheme all fails to address this problem.

Summary of the invention

(1) technical problem that will solve

Weak point at above scheme existence, main purpose of the present invention is to provide a kind of A/D converter sampling switch of the low-voltage high linearity based on dual bootstrap and voltage compensation technology, to reduce the power consumption of A/D converter sampling switch, reduce the susceptibility of A/D converter sampling switch, and solve the nonlinear problem that occurs the routed passband of clock after the switching tube gate voltage is booted fabrication error.

(2) technical scheme

For achieving the above object, technical scheme provided by the invention is as follows:

A kind of A/D converter sampling switch based on dual bootstrap and voltage compensation technology comprises:

The main switch unit is used to treat the sampled signal path, realizes treating the sampling function of sampled signal;

Underlayer voltage bootstrapping unit is used for realizing the underlayer voltage bootstrapping function of main switch unit switching tube PMOS Switch;

Grid voltage bootstrapping unit is used for realizing the grid voltage bootstrapping function of main switch unit switching tube PMOS Switch;

The unit is pressed in storage, is used for input signal V _INCarry out parallel sampling, realize V _INThe temporary transient memory function of voltage;

The voltage compensation unit is used to realize output V _OUTThe compensate function of sampling and outputting voltage.

Preferably, described main switch unit is made of switching tube PMOS Switch, grid by PMOSSwitch is connected with grid voltage bootstrapping unit, and substrate by PMOS Switch and the underlayer voltage unit of booting is connected, by source electrode and the input signal V of PMOS Switch _INConnect, by leakage level and the output V of PMOS Switch _OUTBe connected with the voltage compensation unit.

Preferably, described underlayer voltage is booted the unit by switch S ₁, S ₂, S ₃And capacitor C ₁Constitute, the substrate by PMOS Switch is connected with the main switch unit, and the substrate by Parallel Switch and store up the pressure unit and be connected passes through switch S ₁With input signal V _INConnect.

Preferably, described grid voltage is booted the unit by switch S ₄, S ₅, S ₆And capacitor C ₂Constitute, the grid by PMOS Switch is connected with the main switch unit, and the grid by Parallel Switch and store up the pressure unit and be connected passes through switch S ₄With input signal V _INConnect.

Preferably, described switch S ₁To S ₆With bootstrap capacitor C ₁, C ₂Be used to eliminate R _ONNon-linear, the concrete course of work is:

At first, at clock Φ ₁Be low, Φ ₂When high, switch S ₂, S ₃, S ₅, S ₆Closure, C ₁Both end voltage is charged to V _DD-GND=V _DD, C ₂Two ends are charged to V _DD-2V _DD=-V _DD, at this moment, switch P metal-oxide-semiconductor substrate V ₁With grid V ₂Voltage all is V _DD, switching tube disconnects, for keeping phase;

Afterwards, at Φ ₁Be high, Φ ₂When low, switch S ₂, S ₃, S ₅, S ₆Disconnect S ₁And S ₄Closure, because the electric capacity both end voltage remains unchanged, underlayer voltage and grid voltage become V respectively _IN+ V _DDAnd V _IN-V _DD, at this moment, with conducting resistance R _ONExpression formula be

$R_{\mathrm{ON}}=\frac{1}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}\frac{W}{L}(-V_{\mathrm{DD}}-(V_{\mathrm{TH}0}+\mathrm{\γ}(\sqrt{|2{\mathrm{\φ}}_F-V_{\mathrm{DD}}|}-\sqrt{\left|2{\mathrm{\φ}}_F\right|})))}$

As seen, R _ONWith V _INThere is not dependence; Simultaneously, because the underlayer voltage scope is enhanced V _DD～2V _DD, the situation of positively biased will can not appear in PN junction between leak in substrate and source again.

Preferably, described storage presses the unit by parallel sampling switching tube Parallel Switch and capacitor C ₃Constitute, the substrate by Parallel Switch is connected with underlayer voltage bootstrapping unit, and grid by Parallel Switch and the grid voltage unit of booting is connected, by source electrode and the input signal V of Parallel Switch _INConnect, the leakage level by Parallel Switch is connected with the voltage compensation unit.

Preferably, described voltage compensation unit is by switch S ₇～S ₁₂And capacitor C ₄, C ₅Constitute, by leakage level and main switch unit and the output V of PMOS Switch _OUTConnect, press the unit to be connected by leakage level and the storage of ParallelSwitch.

Preferably, switching tube PMOS Switch, the switch S of described main switch unit ₉～S ₁₂And capacitor C ₃～C ₅Be used to eliminate the routed logical nonlinearity erron of the clock that causes after the sampling switch bootstrapping, the concrete course of work is:

At Φ ₁Be high, Φ ₂When low, switching tube PMOS Switch conducting, input signal VIN is sampled to C by switching tube PMOS Switch ₃, by S ₈Disconnect V _INAt C ₃On be temporarily stored;

At Φ ₁Be high, Φ ₂When low, C ₃Top voltage is used to finish the grid and the underlayer voltage bootstrapping of dummy PMOS pipe, its course of work is identical with switching tube PMOS Switch, be the phase lag half period, the switch motion of dummy PMOS pipe is anti-phase with the respective switch action of finishing the main switch bootstrapping; At this moment, the voltage jump of the dummy gate pmos utmost point and substrate is respectively:

ΔV′ _gate＝V _DD-(V _IN-(2V _DD-V _DD))＝2V _DD-V _IN

ΔV′ _bulk＝V _DD-(V _IN+(2V _DD-V _DD))＝-V _IN

Because dummy PMOS pipe source is leaked and to be joined, and links to each other with output, be that the overlap capacitance of switching tube unit width is identical as if the overlap capacitance of its unit width, and its channel width is switching tube half, and utilizes overlap capacitance much smaller than sampling capacitance C _SCondition, can obtain the error voltage that the dummy pipe introduces be on sampling capacitance:

$\mathrm{\&Delta;}{V}^{\&prime;}=\{-V_{\mathrm{IN}}\&CenterDot;(\frac{\frac{1}{2}{\mathrm{<figure-callout\; id="1"\; label="WC\; OVgate"\; filenames="A20081010601000211.png,A20081010601000221.png"\; state="\{\{state\}\}">WC</figure-callout>}}_{\mathrm{OVgate}}}{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{\frac{1}{2}{\mathrm{<figure-callout\; id="1"\; label="WC\; OVbulk"\; filenames="A20081010601000211.png,A20081010601000221.png"\; state="\{\{state\}\}">WC</figure-callout>}}_{\mathrm{OVbulk}}}{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})+2V_{\mathrm{DD}}\&CenterDot;\frac{\frac{1}{2}{\mathrm{<figure-callout\; id="1"\; label="WC\; OVgate"\; filenames="A20081010601000211.png,A20081010601000221.png"\; state="\{\{state\}\}">WC</figure-callout>}}_{\mathrm{OVgate}}}{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}\}\&times;2$

$\&ap;\{-V_{\mathrm{IN}}\&CenterDot;(\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVbulk}}}{{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})+2V_{\mathrm{DD}}\&CenterDot;\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{{\mathrm{OVgate}}_{}}+C_S}\}\&times;2$

$=-V_{\mathrm{IN}}\&CenterDot;(\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{{\mathrm{WC}}_{\mathrm{OVbulk}}}{{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})+2V_{\mathrm{DD}}\&CenterDot;\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}$

Corresponding $\mathrm{\&Delta;V}=V_{\mathrm{IN}}\&CenterDot;(\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{{\mathrm{WC}}_{\mathrm{OVbulk}}}{{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})-2V_{\mathrm{DD}}\&CenterDot;\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S},$ Have

ΔV＝ΔV

So the routed logical error that causes of clock is cancelled out each other, overall error is 0, can eliminate the nonlinearity erron of the new introducing in sampling switch bootstrapping back fully.

(3) beneficial effect

From technique scheme as can be seen, the present invention has following beneficial effect:

1, the present invention is on basic boostrap circuit basis, and the comprehensive advantage of existing scheme is designed with the method for grid and underlayer voltage dual bootstrap and can be operated under the low-voltage, low-power consumption, to the insensitive sampling switch of fabrication error; Simultaneously, take the self-compensating way of voltage to eliminate, efficiently solve the nonlinear problem that occurs the routed passband of clock after the switching tube gate voltage is booted.

2, utilize the present invention, owing to adopted the voltage bootstrap technique, so can realize under the low-voltage restriction of sampling switch to input signal avoided in the rail-to-rail sampling of input signal.

3, utilize the present invention,,, realized low power dissipation design so there is not quiescent dissipation because all circuit all adopts the metal-oxide-semiconductor switching circuit to realize.

4, utilize the present invention,,, improved the linearity of conducting resistance greatly so eliminated the correlation of switch conduction resistance with input signal because grid voltage and underlayer voltage have been carried out " dual bootstrap " design.

5, utilize the present invention, because underlayer voltage is booted,, the situation of PN junction voltage positively biased promptly can under the bigger situation of twice continuous sampling voltage difference, not occur so avoided the shortcoming of general substrate and the direct connectivity scenario of source drain terminal.

6, utilize the present invention, because the technology that employing compensates after sampled signal is stored so the non-linear of the routed passband of clock occur after having eliminated grid voltage and underlayer voltage bootstrapping fully, makes sampling error and input signal irrelevant fully.

Description of drawings

Fig. 1 is the circuit theory schematic diagram that utilizes the sampling switch of NMOS formation;

Fig. 2 is the circuit diagram of bootstrapping sampling switch under the conducting state;

Fig. 3 offsets V for adopting _THThe circuit diagram of the bootstrapping sampling switch realized of method;

Fig. 4 adopts the PMOS pipe to eliminate the circuit diagram of the bootstrapping sampling switch of bulk effect;

Fig. 5 bursts for clock and leads to the principle schematic that error produces;

Fig. 6 is the structural circuit figure of the A/D converter sampling switch of the low-voltage high linearity based on dual bootstrap and voltage compensation technology provided by the invention;

Fig. 7 is the sequential schematic diagram of the clock of circuit employing shown in Figure 6;

Fig. 8 produces the routed logical principle schematic of clock behind grid and underlayer voltage dual bootstrap;

Fig. 9 is the structural circuit figure based on the A/D converter sampling switch of the low-voltage high linearity of dual bootstrap and voltage compensation technology according to the embodiment of the invention.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.

The present invention is from the most basic boostrap circuit, the advantage of comprehensive existing scheme, design with the method for grid and underlayer voltage dual bootstrap and can be operated under the low-voltage, low-power consumption, to the insensitive sampling switch of fabrication error, simultaneously, take the self-compensating way of voltage to eliminate, solved the nonlinear problem that occurs the routed passband of clock after the switching tube gate voltage is booted.

As shown in Figure 6, Fig. 6 is the structural circuit figure of the A/D converter sampling switch of the low-voltage high linearity based on dual bootstrap and voltage compensation technology provided by the invention, and this A/D converter sampling switch comprises following functional unit: unit and voltage compensation unit are pressed in main switch unit, underlayer voltage bootstrapping unit, grid voltage bootstrapping unit, storage.

Wherein, the main switch unit is used to treat the sampled signal path, realizes treating the sampling function of sampled signal; This main switch unit is made of switching tube PMOS Switch, and grid by PMOS Switch and grid voltage bootstrapping unit are connected, and substrate by PMOS Switch and the underlayer voltage unit of booting is connected, by source electrode and the input signal V of PMOS Switch _INConnect, by leakage level and the output V of PMOS Switch _OUTBe connected with the voltage compensation unit.

Underlayer voltage bootstrapping unit is used for realizing the underlayer voltage bootstrapping function of main switch unit switching tube PMOS Switch; This underlayer voltage bootstrapping unit is by switch S ₁, S ₂, S ₃And capacitor C ₁Constitute, the substrate by PMOS Switch is connected with the main switch unit, and the substrate by Parallel Switch and store up the pressure unit and be connected passes through switch S ₁With input signal V _INConnect.

Grid voltage bootstrapping unit is used for realizing the grid voltage bootstrapping function of main switch unit switching tube PMOS Switch; This grid voltage bootstrapping unit is by switch S ₄, S ₅, S ₆And capacitor C ₂Constitute, the grid by PMOS Switch is connected with the main switch unit, and the grid by Parallel Switch and store up the pressure unit and be connected passes through switch S ₄With input signal V _INConnect.

Storage presses the unit to be used for input signal V _INCarry out parallel sampling, realize V _INThe temporary transient memory function of voltage; This storage presses the unit by parallel sampling switching tube Parallel Switch and capacitor C ₃Constitute, be connected, pass through Parallel by substrate and the underlayer voltage of the Parallel Switch unit of booting

The grid of Switch is connected with grid voltage bootstrapping unit, by source electrode and the input signal V of Parallel Switch _INConnect, the leakage level by Parallel Switch is connected with the voltage compensation unit.

The voltage compensation unit is used to realize output V _OUTThe compensate function of sampling and outputting voltage.This voltage compensation unit is by switch S ₇～S ₁₂And capacitor C ₄, C ₅Constitute, by leakage level and main switch unit and the output V of PMOS Switch _OUTConnect, press the unit to be connected by leakage level and the storage of Parallel Switch.

Fig. 7 shows the sequential schematic diagram of the clock of circuit employing shown in Figure 6.

The bootstrapped switch main body adopts the PMOS pipe as switching tube, and has parallel sampling PMOS pipe and dummy PMOS pipe to constitute accordingly, and remainder is made up of 12 MOS switches, 4 bootstrap capacitors and 1 parallel sampling electric capacity.The course of work of bootstrapped switch is divided into sampling, keeps two phase places, and the whole switches among Fig. 6 are by two inversion clock Φ ₁And Φ ₂Control, when voltage was high, switch disconnected Φ when switch closure, voltage were low ₁High Φ ₂Be sampling phase, Φ when low ₁Low Φ ₂Gao Shiwei keeps phase.Clock Φ ₁And Φ ₂Phase relation as shown in Figure 7, in reality realizes, can obtain one tunnel clock signal back of negating.Be the detailed operation principle of invention below.

1. eliminate R _ONNon-linear

Among Fig. 6, switch S ₁～S ₆With bootstrap capacitor C ₁And C ₂Be used for eliminating R _ONNon-linear.The course of work is: at first, and at clock Φ ₁Be low, Φ ₂When high, switch S ₂, S ₃, S ₅, S ₆Closure, C ₁Both end voltage is charged to V _DD-GND=V _DD, C ₂Two ends are charged to V _DD-2V _DD=-V _DD, at this moment, switch P metal-oxide-semiconductor substrate V ₁With grid V ₂Voltage all is V _DD, switching tube disconnects, for keeping phase; Afterwards, at Φ ₁Be high, Φ ₂When low, switch S ₂, S ₃, S ₅, S ₆Disconnect S ₁And S ₄Closure, because the electric capacity both end voltage remains unchanged, underlayer voltage and grid voltage become V respectively _IN+ V _DDAnd V _IN-V _DD, at this moment, with conducting resistance R _ONExpression formula be

$R_{\mathrm{ON}}=\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}(-V_{\mathrm{DD}}-(V_{\mathrm{TH}0}+\mathrm{\&gamma;}(\sqrt{|2{\mathrm{\&phi;}}_F-V_{\mathrm{DD}}|}-\sqrt{\left|2{\mathrm{\&phi;}}_F\right|})))}---(2-1)$

As seen, R _ONWith V _INThere is not dependence.Simultaneously, because the underlayer voltage scope is enhanced V _DD～2V _DD, the situation of positively biased will can not appear in PN junction between leak in substrate and source again.

2. eliminate routed lead to non-linear of the clock that causes after the bootstrapping

Fig. 8 shows and produce the routed logical principle schematic of clock behind grid and underlayer voltage dual bootstrap.Suppose grid to the source or the overlap capacitance of drain electrode be C _OVgate, substrate to the source or the overlap capacitance of drain electrode be C _OVbulk, the error that is incorporated on the sampling capacitance after the bootstrapping release can be expressed as

$\mathrm{\&Delta;V}=\mathrm{\&Delta;}{V}_{\mathrm{gate}}\frac{{\mathrm{WC}}_{\mathrm{Ovgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\mathrm{\&Delta;}{V}_{\mathrm{bulk}}\frac{{\mathrm{WC}}_{\mathrm{OVbulk}}}{{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S}---(2-2)$

Wherein, the voltage jump of grid and substrate is respectively

ΔV _gate＝(V _IN-(2V _DD-V _DD))-V _DD＝V _IN-2V _DD (2-3)

ΔV _bulk＝(V _IN+(2V _DD-V _DD))-V _DD＝V _IN (2-4)

Finally, at sampling capacitance C _SThe error voltage of last generation is

$\mathrm{\&Delta;V}=V_{\mathrm{IN}}\&CenterDot;(\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{{\mathrm{WC}}_{\mathrm{OVbulk}}}{{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})-2V_{\mathrm{DD}}\&CenterDot;\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}---(2-5)$

Thus, find bootstrapping clock feedthrough afterwards and input V _INRelevant, will cause new nonlinearity erron.For addressing this problem the PMOS pipe of the parallel sampling among Fig. 6, switch S ₉～S ₁₂And capacitor C ₃～C ₅Be used to eliminate this error.The course of work is: at Φ ₁Be high, Φ ₂When low, the conducting of parallel PMOS pipe, input signal V _INSampled to C by parallel PMOS pipe ₃, by S ₈Disconnect V _INAt C ₃On be temporarily stored, at Φ ₁Be high, Φ ₂When low, C ₃Top voltage is used to finish the grid and the underlayer voltage bootstrapping of dummy PMOS pipe, its course of work is identical with main switch PMOS pipe, be the phase lag half period, i.e. the switch motion of dummyPMOS pipe is anti-phase with the respective switch action of finishing the main switch bootstrapping.At this moment, the voltage jump of the dummy gate pmos utmost point and substrate is respectively

ΔV′ _gate＝V _DD-(V _IN-(2V _DD-V _DD))＝2V _DD-V _IN (2-6)

ΔV′ _bulk＝V _DD-(V _IN+(2V _DD-V _DD))＝-V _IN (2-7)

Because dummy PMOS pipe source is leaked and to be joined, and links to each other with output, be that the overlap capacitance of switching tube unit width is identical as if the overlap capacitance of its unit width, and its channel width is switching tube half, and utilizes overlap capacitance much smaller than sampling capacitance C _SCondition, can obtain the error voltage that the dummy pipe introduces be on sampling capacitance

$\mathrm{\&Delta;}{V}^{\&prime;}=\{-V_{\mathrm{IN}}\&CenterDot;(\frac{\frac{1}{2}{\mathrm{<figure-callout\; id="1"\; label="WC\; OVgate"\; filenames="A20081010601000211.png,A20081010601000221.png"\; state="\{\{state\}\}">WC</figure-callout>}}_{\mathrm{OVgate}}}{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{\frac{1}{2}{\mathrm{<figure-callout\; id="1"\; label="WC\; OVbulk"\; filenames="A20081010601000211.png,A20081010601000221.png"\; state="\{\{state\}\}">WC</figure-callout>}}_{\mathrm{OVbulk}}}{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})+2V_{\mathrm{DD}}\&CenterDot;\frac{\frac{1}{2}{\mathrm{<figure-callout\; id="1"\; label="WC\; OVgate"\; filenames="A20081010601000211.png,A20081010601000221.png"\; state="\{\{state\}\}">WC</figure-callout>}}_{\mathrm{OVgate}}}{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}\}\&times;2$

$\&ap;\{-V_{\mathrm{IN}}\&CenterDot;(\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVbulk}}}{{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})+2V_{\mathrm{DD}}\&CenterDot;\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{{\mathrm{OVgate}}_{}}+C_S}\}\&times;2---(2-8)$

$=-V_{\mathrm{IN}}\&CenterDot;(\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{{\mathrm{WC}}_{\mathrm{OVbulk}}}{{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})+2V_{\mathrm{DD}}\&CenterDot;\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}$

Corresponding (2-5) has

ΔV＝ΔV′(2-9)

So the routed logical error that causes of clock is cancelled out each other, overall error is 0.Therefore, the present invention can eliminate the new nonlinearity erron of introducing in sampling switch bootstrapping back fully.

The present invention is when implementing, and all switches all utilize NMOS pipe or PMOS pipe to realize.Owing to consider the requirement of device stability, the maximum voltage difference between the source electrode of all MOS, leakage level and grid, the substrate should maintain-V _DD～V _DDScope in, for this reason, when realizing, can consider to increase the metal-oxide-semiconductor that some clocks remain on conducting state dividing potential drop is carried out in the bigger place of node voltage, increase the reliability of circuit.

In actual applications, a kind of circuit theory of execution mode as shown in Figure 9, timing relationship wherein is as shown in Figure 7.NM wherein ₁₅And NM ₁₆And capacitor C ₆And C ₇Be used for producing complementary 2V _DDVoltage.PMOS Switch and Parallel Switch are identical, and the DummySwitch breadth length ratio is half of above-mentioned two pipes.The course of work of entire circuit is divided into sampling and keeps two phase places, specifies as follows:

1, (be Φ in previous maintenance phase place ₁Be low, Φ ₂Be height), capacitor C ₁PM is passed through at two ends ₁～PM ₃Be charged to-V _DD, C ₂By charging NM ₄And PM ₅To V _DD, this moment, switching tube PMOS Switch and parallel sampling pipe Parallel Switch grid voltage were V _DD, underlayer voltage is V _DD, all be in closed condition;

2, after sampling arrives mutually, (be Φ ₁Be high, Φ ₂For low), C ₁One end passes through NM ₁And NM ₂With input signal V _INLink to each other C ₂One end passes through NM ₅With V _INJoin C ₁And C ₂The other end link to each other with substrate with the grid of parallel sampling pipe Parallel Switch with switching tube PMOS Switch respectively, respectively grid voltage and underlayer voltage are booted to V _DD-V _INAnd V _DD+ V _IN, making its conducting, input signal is sampled to sampling capacitance by switching tube, samples to C by the parallel sampling pipe simultaneously ₃

3, in same sampling phase, the grid of Dummy Switch passes through PM ₇And PM ₈, substrate passes through PM ₁₀, all be connected to V _DD

4, in ensuing maintenance phase, grid and the underlayer voltage of PMOW Switch and Parallel Switch return to V _DD, pipe is closed, and the routed logical error voltage that causes of input signal and clock is sampled to electric capacity;

5, in same maintenance phase, the grid of Dummy Switch and substrate are finished bootstrapping with the similar mode of switching tube respectively, and utilization is kept at C ₃On applied signal voltage boot to V _DD-V _INAnd V _DD+ V _IN, the clock of Dummy Switch is burst to switch on to pressing and is introduced output V by way of compensation in finishing this bootstrapping process _OUT, the voltage on the sampling capacitance to be revised, the sampling process in the one-period is finished.

Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

List of references

[1]、A.K.Ong，V.I.Prodanov，M.Tarsia，“A?method?for?reducingthe?variation?in“on”resistance?of?a?mos?sampling?switch，”Proc.IEEEISCAS，vol.5，pp.437-440，2000.

[2]、M.Waltari，K.Halonen，“Bootstrapped?switch?without?bulkeffect?in?standard?CMOS?technology”，Electronics?Letters，vol.38，pp.555-557，2002.

[3], Behzad Razavi, " Design ofAnalog CMOS Integrated Circuits ", publishing house of Xi'an Communications University, 2003.

Claims (8)

1, a kind of A/D converter sampling switch based on dual bootstrap and voltage compensation technology is characterized in that, comprising:

The main switch unit is used to treat the sampled signal path, realizes treating the sampling function of sampled signal;

Underlayer voltage bootstrapping unit is used for realizing the underlayer voltage bootstrapping function of main switch unit switching tube PMOS Switch;

Grid voltage bootstrapping unit is used for realizing the grid voltage bootstrapping function of main switch unit switching tube PMOS Switch;

The unit is pressed in storage, is used for input signal V _INCarry out parallel sampling, realize V _INThe temporary transient memory function of voltage;

The voltage compensation unit is used to realize output V _OUTThe compensate function of sampling and outputting voltage.

2, the A/D converter sampling switch based on dual bootstrap and voltage compensation technology according to claim 1, it is characterized in that, described main switch unit is made of switching tube PMOS Switch, grid by PMOS Switch is connected with grid voltage bootstrapping unit, substrate by PMOSSwitch is connected with underlayer voltage bootstrapping unit, by source electrode and the input signal V of PMOS Switch _INConnect, by leakage level and the output V of PMOS Switch _OUTBe connected with the voltage compensation unit.

3, the A/D converter sampling switch based on dual bootstrap and voltage compensation technology according to claim 1 is characterized in that, described underlayer voltage bootstrapping unit is by switch S ₁, S ₂, S ₃And capacitor C ₁Constitute, the substrate by PMOS Switch is connected with the main switch unit, and the substrate by Parallel Switch and store up the pressure unit and be connected passes through switch S ₁With input signal V _INConnect.

4, the A/D converter sampling switch based on dual bootstrap and voltage compensation technology according to claim 1 is characterized in that, described grid voltage bootstrapping unit is by switch S ₄, S ₅, S ₆And capacitor C ₂Constitute, the grid by PMOS Switch is connected with the main switch unit, and the grid by Parallel Switch and store up the pressure unit and be connected passes through switch S ₄With input signal V _INConnect.

5, according to claim 3 or 4 described A/D converter sampling switchs, it is characterized in that described switch S based on dual bootstrap and voltage compensation technology ₁To S ₆With bootstrap capacitor C ₁, C ₂Be used to eliminate R _ONNon-linear, the concrete course of work is:

At first, at clock Φ ₁Be low, Φ ₂When high, switch S ₂, S ₃, S ₅, S ₆Closure, C ₁Both end voltage is charged to V _DD-GND=V _DD, C ₂Two ends are charged to V _DD-2V _DD=-V _DD, at this moment, switch P metal-oxide-semiconductor substrate V ₁With grid V ₂Voltage all is V _DD, switching tube disconnects, for keeping phase;

Afterwards, at Φ ₁Be high, Φ ₂When low, switch S ₂, S ₃, S ₅, S ₆Disconnect S ₁And S ₄Closure, because the electric capacity both end voltage remains unchanged, underlayer voltage and grid voltage become V respectively _IN+ V _DDAnd V _IN-V _DD, at this moment, with conducting resistance R _ONExpression formula be

$R_{\mathrm{ON}}=\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}(-V_{\mathrm{DD}}-(V_{\mathrm{TH}0}+\mathrm{\&gamma;}(\sqrt{|2{\mathrm{\&phi;}}_R-V_{\mathrm{DD}}|}-\sqrt{\left|{2\mathrm{\&phi;}}_F\right|})))}$

As seen, R _ONWith V _INThere is not dependence; Simultaneously, because the underlayer voltage scope is enhanced V _DD～2V _DD, the situation of positively biased will can not appear in PN junction between leak in substrate and source again.

6, the A/D converter sampling switch based on dual bootstrap and voltage compensation technology according to claim 1 is characterized in that, described storage presses the unit by parallel sampling switching tube ParallelSwitch and capacitor C ₃Constitute, the substrate by Parallel Switch is connected with underlayer voltage bootstrapping unit, and grid by Parallel Switch and the grid voltage unit of booting is connected, by source electrode and the input signal V of Parallel Switch _INConnect, the leakage level by Parallel Switch is connected with the voltage compensation unit.

7, the A/D converter sampling switch based on dual bootstrap and voltage compensation technology according to claim 1 is characterized in that, described voltage compensation unit is by switch S ₇～S ₁₂And capacitor C ₄, C ₅Constitute, by leakage level and main switch unit and the output V of PMOS Switch _OUTConnect, press the unit to be connected by leakage level and the storage of Parallel Switch.

8, according to claim 6 or 7 described A/D converter sampling switchs, it is characterized in that switching tube PMOSSwitch, the switch S of described main switch unit based on dual bootstrap and voltage compensation technology ₉～S ₁₂And capacitor C ₃～C ₅Be used to eliminate the routed logical nonlinearity erron of the clock that causes after the sampling switch bootstrapping, the concrete course of work is:

At Φ ₁Be high, Φ ₂When low, switching tube PMOS Switch conducting, input signal V _INSampled to C by switching tube PMOS Switch ₃, by S ₈Disconnect V _INAt C ₃On be temporarily stored;

At Φ ₁Be high, Φ ₂When low, C ₃Top voltage is used to finish the grid and the underlayer voltage bootstrapping of dummy PMOS pipe, its course of work is identical with switching tube PMOS Switch, be the phase lag half period, the switch motion of dummy PMOS pipe is anti-phase with the respective switch action of finishing the main switch bootstrapping; At this moment, the voltage jump of the dummy gate pmos utmost point and substrate is respectively:

ΔV′ _gate＝V _DD-(V _IN-(2V _DD-V _DD))＝2V _DD-V _IN

ΔV′ _bulk＝V _DD-(V _IN+(2V _DD-V _DD))＝-V _IN

Because dummy PMOS pipe source is leaked and to be joined, and links to each other with output, be that the overlap capacitance of switching tube unit width is identical as if the overlap capacitance of its unit width, and its channel width is switching tube half, and utilizes overlap capacitance much smaller than sampling capacitance C _SCondition, can obtain the error voltage that the dummy pipe introduces be on sampling capacitance:

${\mathrm{\&Delta;V}}^{\&prime;}=\{-V_{\mathrm{IN}}\&CenterDot;(\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}}{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVbulk}}}{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})+2V_{\mathrm{DD}}\&CenterDot;\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}}{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}\}\&times;2$

$\&ap;\{-V_{\mathrm{IN}}\&CenterDot;(\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVbulk}}}{{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})+{2V}_{\mathrm{DD}}\&CenterDot;\frac{\frac{1}{2}{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}\}\&times;2$

$=-V_{\mathrm{IN}}\&CenterDot;(\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{{\mathrm{WC}}_{\mathrm{OVbulk}}}{{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})+{2V}_{\mathrm{DD}}\&CenterDot;\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}$

Corresponding $\mathrm{\&Delta;V}=V_{\mathrm{IN}}\&CenterDot;(\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S}+\frac{{\mathrm{WC}}_{\mathrm{OVbulk}}}{{\mathrm{WC}}_{\mathrm{OVbulk}}+C_S})-2V_{\mathrm{DD}}\&CenterDot;\frac{{\mathrm{WC}}_{\mathrm{OVgate}}}{{\mathrm{WC}}_{\mathrm{OVgate}}+C_S},$ Have

ΔV＝ΔV′

So the routed logical error that causes of clock is cancelled out each other, overall error is 0, can eliminate the nonlinearity erron of the new introducing in sampling switch bootstrapping back fully.

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