CN107896110B - Bootstrap sampling switch circuit, sample-and-hold circuit, and time-interleaved ADC - Google Patents

Bootstrap sampling switch circuit, sample-and-hold circuit, and time-interleaved ADC Download PDF

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CN107896110B
CN107896110B CN201711353832.1A CN201711353832A CN107896110B CN 107896110 B CN107896110 B CN 107896110B CN 201711353832 A CN201711353832 A CN 201711353832A CN 107896110 B CN107896110 B CN 107896110B
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clock
signal
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sampling
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CN107896110A (en
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张辉
富浩宇
高远
王海军
陈正
李琪林
李丹
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Shanghai Beiling Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase

Abstract

The invention discloses a bootstrap sampling switch circuit, a sampling hold circuit and a time-interleaved ADC (analog-to-digital converter), wherein the bootstrap sampling switch circuit comprises a charge pump, a first capacitor, a first NMOS (N-channel metal oxide semiconductor) tube, a first PMOS (P-channel metal oxide semiconductor) tube, a first clock input end, a gating input end, a clock output end, a duty ratio adjusting circuit, a synchronous circuit, a second NMOS tube and a third NMOS tube; the gating input end is used for accessing a sampling selection signal of a sub-ADC channel of the time-interleaved ADC, the first clock input end is used for accessing a system clock, the clock output end is used for outputting a sampling clock signal, and the sampling clock signal is used for controlling a sampling switch of a sampling holding circuit of the sub-ADC. The invention utilizes the system clock of the time-interleaved ADC and the sampling selection signal of the sub-ADC channel generated by the digital platform to perform combinational logic to generate the sampling clock signal, thereby greatly reducing the jitter, simplifying the additional clock circuit and improving the time sequence matching between the channels.

Description

Bootstrap sampling switch circuit, sample-and-hold circuit, and time-interleaved ADC
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a bootstrap sampling switch circuit, a sample-and-hold circuit, and a time-interleaved ADC (analog-to-digital converter) for an analog-to-digital converter circuit.
Background
Analog-to-digital converters are used to convert analog signals into digital signals and are widely used in various data acquisition and communication systems. The sampling rate of the ADC directly determines the signal bandwidth that can be processed, and the accuracy of the ADC (e.g., SNR, SFDR, etc.) determines the dynamic range of the overall system. The ADC has various architectures, such as a pipelined ADC, a successive approximation ADC (SAR ADC), a flash ADC, a time interleaved ADC, and the like. In the architectures, the time-interleaved ADC is formed by time-interleaving a plurality of low-speed (relatively speaking) sub-ADCs, so that the process limitation can be greatly broken through, and the sampling rate can be increased. Theoretically, M sub-ADCs with the sampling rate of fs/M are adopted for time interleaving, and the sampling rate of the whole ADC can reach fs.
However, while time-interleaved ADCs boost the sampling rate, mismatches between sub-ADC channels also introduce a variety of errors, including: mismatch error, gain mismatch error, sampling bandwidth mismatch error, and sampling time mismatch error. The offset mismatch and the gain mismatch can be corrected very conveniently through digital background calibration, and the mismatch error of the sampling bandwidth and the sampling time is very difficult to solve through pure digital calibration, and the mixed signal calibration needs to be carried out by combining an analog circuit.
To further understand the sampling bandwidth and sampling time mismatch, fig. 1 shows a typical front-end sample-and-hold circuit for a sub-ADC channel. In the sampling process, the clock signals cks and cksp _ bst respectively control the switch S2And S1And (5) closing. The clock signal cksp _ bst is turned off before cks, thereby determining the sampling time. Sampling bandwidth is controlled by switch on resistance (S)2And S1Sum of resistances) and a capacitance CSAnd (4) jointly determining.
Note that the sample bias voltage Vb_sampDetermined by the input common mode voltage of the operational amplifier, which is VDDLevel around/2, VDDFor the supply voltage, this makes the switch S1Is very difficult to design. One good way to do this is to use NMOS (N-type metal-oxide-semiconductor) switches for S1(NMOS has much smaller on-resistance than PMOS), and then a bootstrap switch (bootstrap switch) circuit is used to generate a signalA high level is VDD+Vb_sampSo that S is1There is a smaller on-resistance.
FIG. 2 is a circuit diagram of a conventional voltage-bootstrapped switch, assuming the capacitance of the cksp _ bst-driven switch is CLIgnoring parasitic capacitances, the high level of cksp _ bst, VH _ ckspbst, can be expressed as:
Figure BDA0001510743100000021
thus under load CLAnd a supply voltage VDDWhen determined, the high level output by the clock signal cksp _ bst is output by the capacitor CBAnd (4) directly determining. It should be noted that the falling time of cksp _ bst, or the delay of the falling edge between cksp and cksp _ bst, and the transistor MRIs related to the on-resistance of.
It is further noted that in such a conventional voltage-bootstrapped sampling switch, cksp _ bst and cksp are completely in phase, so each sub-ADC channel needs a separate clock signal cksp to generate cksp _ bst to drive the sampling switch, as shown in fig. 3 (for simplicity, only two channels are taken as an example), where ck _ ADC is the system clock. This has a problem in that an additional clock circuit such as a phase-locked loop is required to generate the clock signal cksp of a plurality of phases in the time-interleaved ADC. This not only increases the complexity of the design, but also increases the jitter (jitter) of the output clock; in addition, the accuracy of the clock circuit is limited, and a very large timing skew is caused between cksp of each channel.
Disclosure of Invention
The invention aims to overcome the defects that a voltage bootstrap sampling switch circuit adopted by a sub-ADC channel in a time-interleaved ADC in the prior art is complex in structure, large in output clock jitter and large in time sequence deviation among clock signals of each channel, and provides a bootstrap sampling switch circuit, a sampling hold circuit and a time-interleaved ADC, wherein the bootstrap sampling switch circuit, the sampling hold circuit and the time-interleaved ADC can simplify an additional clock circuit so as to improve time sequence matching among channels.
The invention solves the technical problems through the following technical scheme:
the invention provides a bootstrap sampling switch circuit, which is used for a time-interleaved ADC (analog-to-digital converter), and comprises a charge pump, a first capacitor, a first NMOS (N-channel metal oxide semiconductor) tube and a first PMOS (P-channel metal oxide semiconductor) tube, and is characterized in that the bootstrap sampling switch circuit also comprises a first clock input end, a gating input end, a clock output end, a duty ratio adjusting circuit, a synchronous circuit, a second NMOS tube and a third NMOS tube;
the gating input end is used for accessing a sampling selection signal of a sub-ADC of the time-interleaved ADC, the first clock input end is used for accessing a system clock of the time-interleaved ADC, the clock output end is used for outputting a sampling clock signal, and the sampling clock signal is used for controlling a sampling switch of a sampling holding circuit of the sub-ADC;
the duty ratio adjusting circuit comprises a first input end and a first output end, the first input end is electrically connected with the first clock input end, and the duty ratio adjusting circuit is used for increasing the duty ratio of a signal input by the first input end and outputting the signal to the first output end; the period of the signal output by the first output end is the same as that of the signal accessed by the first input end, and the falling edge of the signal output by the first output end is consistent with that of the signal accessed by the first input end;
the synchronous circuit comprises a data input end, a second clock input end and a data output end, wherein the data input end is electrically connected with the gating input end, and the second clock input end is electrically connected with the first clock input end; the data output end is electrically connected with the input end of the charge pump and the grid electrode of the second NMOS tube; the synchronous circuit is used for synchronously triggering the signal input by the data input end by adopting the signal input by the second clock input end and outputting the synchronously triggered signal to the data output end;
the output end of the charge pump is electrically connected with the grid electrode of the first NMOS tube;
one end of the first capacitor and the source electrode of the second NMOS tube are electrically connected with the data output end;
the drain electrode of the first PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the second NMOS tube are electrically connected with the clock output end;
and the inverted signal output by the data output end is connected to the grid electrode of the third NMOS tube, and the source electrode of the third NMOS tube is grounded.
The bootstrap sampling switch circuit provided by the scheme is simple in structure, different from the traditional mode of generating the sampling clock signals of each sub-ADC channel through clock circuits such as a phase-locked loop, the traditional mode of generating the sampling clock signals by adopting a frequency division circuit is completely abandoned, the sampling clock signals are generated by using the system clock of the time-interleaved ADC and the sampling selection signals of the sub-ADC channels generated by the digital platform as combinational logic, and the signals output by the first output ends of the sub-ADC channels are generated by the same system clock through the combinational logic, so that the jitter is greatly reduced. In addition, the signal output by the first output end is shared by a plurality of sub-ADC channels, so that the time sequence mismatch among the sub-ADC channels is greatly reduced.
In the scheme, two important signals are involved, one is a signal output by the first output end, the signal is obtained by adjusting the duty ratio of a system clock, and the signal only has a narrow low pulse. And the other is a sampling selection signal of the sub-ADC channel of the time-interleaved ADC accessed by the strobe input end, and the signal determines whether the corresponding sub-ADC channel in the time-interleaved ADC is selected to be used for sampling, so that the working sequence of each sub-ADC channel of the time-interleaved ADC is determined. The time-interleaved ADC comprises M sub-ADCs, the sampling rate of the whole ADC is fs, the frequency of the signal is fs/M, the width of a high pulse is 1/fs, and the signal is sampled and delayed by a system clock after being connected into the synchronous circuit, so that the signal output by the data output end is generated, and the rising edge and the falling edge of the signal are both positioned in the low level of the signal output by the first output end.
Preferably, the source of the first NMOS transistor, the other end of the first capacitor, and the source of the first PMOS transistor are electrically connected, and the drain of the first NMOS transistor, the gate of the first PMOS transistor, and the charge pump are all connected to a bias voltage.
In this scheme, the high level of the signal output by the clock output end of the bootstrap sampling switch circuit is the sum of the power supply voltage and the bias voltage.
Preferably, the duty cycle adjusting circuit further includes an inverting delay and a nand gate, an input end of the nand gate and an input end of the inverting delay are electrically connected to the first input end, an output end of the inverting delay is electrically connected to another input end of the nand gate, and an output end of the nand gate is electrically connected to the first output end.
In this scheme, the duty ratio adjusting circuit performs a reverse delay on the system clock signal input through the first input terminal, and then performs a nand operation with the original signal to generate an output signal to the first output terminal.
Preferably, the synchronization circuit is a D flip-flop.
In this scheme, the synchronization circuit is implemented by a D flip-flop, a D terminal of the D flip-flop is the data input terminal, a CK terminal of the D flip-flop is the second clock input terminal, and a Q terminal of the D flip-flop is the data output terminal.
Preferably, the D flip-flop includes a D input terminal, a CK input terminal, a Q output terminal and
Figure BDA0001510743100000053
an output, the D input electrically connected with the data input, the CK input electrically connected with the second clock input, the Q output electrically connected with the data output, the Q output
Figure BDA0001510743100000054
The output end is connected to the grid electrode of the third NMOS tube.
In the scheme, the D trigger comprises two output ends, namely a forward output end and a reverse output end, and the reverse output end is directly connected to the grid electrode of the third NMOS tube.
Preferably, the second NMOS transistor is an NMOS transistor array of binary size, each NMOS transistor in the NMOS transistor array is an array NMOS transistor, a gate of the array NMOS transistor is electrically connected to an output terminal of an and gate, an input terminal of the and gate is electrically connected to the data output terminal, and another input terminal of the and gate is connected to a first control signal, where the first control signal is used to control whether the corresponding array NMOS transistor is selected.
In the scheme, the size of the on-resistance of the NMOS tube array can be adjusted through the first control signal, and the time parameter of the falling edge of the sampling clock signal output by the clock output end can be further conveniently adjusted, so that the speed of the falling edge of the signal is changed, and the adjustment of the time sequence deviation of each sub-ADC channel is further realized.
Preferably, the first capacitor is a binary capacitor array, and an equivalent capacitance value of the binary capacitor array is adjustable.
In the scheme, the high level of the sampling clock signal output by the clock output end is adjusted by adjusting the equivalent capacitance value of the first capacitor, and the adjustment of the sampling bandwidth of each sub-ADC channel is further realized.
Preferably, each array capacitor in the binary capacitor array is controlled by a second control signal to determine whether to select, the selected array capacitor charges or discharges with the signal output by the first output terminal when the signal output by the data output terminal is high, and the unselected array capacitors are grounded.
In the scheme, the second control signal is controlled by an external digital platform, namely whether each array capacitor in the binary capacitor array is selected or not is controlled, so that the adjustment of the equivalent capacitance value of the first capacitor is realized, and the adjustment of the high level of the sampling clock signal output by the clock output end is further realized.
The invention also provides a sample-and-hold circuit, which is used for a sub-ADC in a time-interleaved ADC, and is characterized in that the sample-and-hold circuit comprises a sampling switch and the bootstrap sampling switch circuit, and the sampling clock signal output by the clock output end is used for controlling the sampling switch.
The invention also provides a time-interleaved ADC, which comprises a plurality of sub-ADCs and is characterized in that each sub-ADC comprises the sampling hold circuit.
The positive progress effects of the invention are as follows: the bootstrap sampling switch circuit, the sampling hold circuit and the time-interleaved ADC provided by the invention generate sampling clock signals by using a system clock of the time-interleaved ADC and a sampling selection signal of a sub-ADC channel generated by a digital platform as combinational logic through an innovative bootstrap sampling switch circuit. Furthermore, the sampling bandwidth can be adjusted by adjusting the high level of the output sampling clock signal; and adjusting the falling edge of the output sampling clock signal so as to adjust the sampling time deviation among the sub ADC channels.
Drawings
Fig. 1 is a circuit diagram of a typical front-end sample-and-hold circuit for a sub-ADC.
Fig. 2 is a circuit diagram of a conventional voltage bootstrapped sampling switch.
Fig. 3 is a timing diagram of the system clock ck _ ADC and cksp when the time-interleaved ADC of fig. 2 includes two sub-ADCs.
Fig. 4 is a circuit diagram of a bootstrap sampling switch circuit according to embodiment 1 of the present invention.
FIG. 5 shows a second NMOS transistor R in FIG. 4varA circuit diagram of a binary sized NMOS transistor array is employed.
FIG. 6 shows the first capacitor C in FIG. 4varA circuit diagram of a binary capacitor array is used.
Fig. 7 is a timing diagram of the sampling clock signals generated in embodiment 1 of the present invention.
Fig. 8 is a timing diagram of the signal cksp _ new output from the first output terminal in embodiment 1 of the present invention.
FIG. 9 shows a second NMOS transistor R in embodiment 2 of the present inventionvarCircuit diagram of adopted NMOS tube array with binary size。
Fig. 10 is a circuit diagram of a sample-and-hold circuit according to embodiment 3 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 4, this embodiment provides a bootstrap sampling switch circuit for a time-interleaved ADC, where the bootstrap sampling switch circuit includes a charge pump 3 and a first capacitor CvarThe clock comprises a first NMOS tube N1, a first PMOS tube P1, a first clock input end 4, a gating input end 5, a clock output end 6, a duty ratio adjusting circuit 1, a synchronous circuit 2 and a second NMOS tube RvarAnd a third NMOS transistor Mpd。
The strobe input terminal 5 is configured to access a sampling selection signal sel < i > of an i-th sub-ADC channel of the time-interleaved ADC, the first clock input terminal 4 is configured to access a system clock ck _ ADC of the time-interleaved ADC, the clock output terminal 6 is configured to output a sampling clock signal cksp _ bst < i >, and the sampling clock signal cksp _ bst < i > is configured to control a sampling switch of a sample-and-hold circuit of the i-th sub-ADC of the time-interleaved ADC.
The duty ratio adjusting circuit 1 includes a first input end 101, a first output end 102, an inverse delay unit 103 and a nand gate 104, wherein the first input end 101 is electrically connected to the first clock input end 4, an input end of the nand gate 104 and an input end of the inverse delay unit 103 are electrically connected to the first input end 101, an output end of the inverse delay unit 103 is electrically connected to another input end of the nand gate 104, and an output end of the nand gate 104 is electrically connected to the first output end 102. The duty ratio adjusting circuit 1 is configured to increase a duty ratio of a signal input by the first input end 101 and output the increased duty ratio to the first output end 102; the signal cksp _ new output by the first output terminal 102 has the same period as the signal switched in by the first input terminal 101, and the falling edge of the signal output by the first output terminal 102 coincides with the rising edge of the signal switched in by the first input terminal 101.
The synchronous circuit 2 comprises a data input terminal 201, a second clock input terminal 202 and a data output terminal 203, wherein the data input terminal 201 is electrically connected with the strobe input terminal 5, and the second clock input terminal 202 is electrically connected with the first clock input terminal 4; the data output end 203, the input end 301 of the charge pump 3 and the second NMOS transistor RvarThe grid of the grid is electrically connected; the synchronous circuit 2 is configured to perform synchronous triggering on the signal input by the data input end 201 by using the signal input by the second clock input end 202, and output the signal after synchronous triggering to the data output end 203. In this embodiment, the synchronous circuit 2 is implemented by using a D flip-flop, which includes a D input terminal, a CK input terminal, and a Q output terminal, where the D input terminal is electrically connected to the data input terminal 201, the CK input terminal is electrically connected to the second clock input terminal 202, and the Q output terminal is electrically connected to the data output terminal 203.
The output end 302 of the charge pump 3 is electrically connected with the gate of the first NMOS transistor N1.
The first capacitor CvarOne end of the second NMOS tube RvarIs electrically connected to the data output terminal.
The drain electrode of the first PMOS tube and the third NMOS tube MpdAnd the second NMOS transistor RvarIs electrically connected to the clock output terminal 6.
The signal sel _ int output by the data output terminal 203 is inverted to obtain a sel _ int _ n signal, which is connected to the third NMOS transistor MpdThe third NMOS tube MpdIs grounded. In this embodiment, the sel _ int _ n signal is implemented by means of a phase inverter in the charge pump 3, and the synchronous circuit 2 may also be implemented by using a D flip-flop having two output terminals, a forward output terminal and a reverse output terminal, where the reverse output terminal is directly connected to the third NMOS transistor MpdMay also be between the data output terminal 203 and the third NMOS transistor MpdAn inverter is directly connected between the gates of the two transistors.
The source of the first NMOS transistor N1Pole, said first capacitor CvarThe other end of the first PMOS transistor P1 is electrically connected to the source of the first PMOS transistor P1, and the drain of the first NMOS transistor N1, the gate of the first PMOS transistor P1 and the charge pump 3 are all connected to a bias voltage pwr.
In this embodiment, the second NMOS transistor RvarThe binary-sized NMOS transistor array shown in fig. 5 is adopted, each NMOS transistor in the NMOS transistor array is an array NMOS transistor N3, the gate of the array NMOS transistor N3 is electrically connected to the output terminal of an and gate, one input terminal of the and gate is electrically connected to the data output terminal 203, that is, a signal sel _ int is accessed, and the other input terminal of the and gate is accessed to a first control signal adj _ td [0 ]]To adj _ td [ n ]]The first control signal is used to control whether the corresponding array NMOS transistor N3 is selected. For the ith sub-ADC channel, the sampling time can be adjusted by adjusting the sampling clock signal cksp _ bst<i>Is adjusted by the falling edge of the signal. The embodiment adopts the method that the sampling clock signal cksp _ bst is adjusted<i>The falling edge of the sub-ADC channel is fast or slow, thereby changing the sampling time of the sub-ADC channel. By changing the second NMOS transistor RvarThe on-resistance of the sampling clock signal cksp _ bst can be conveniently adjusted<i>Thereby changing the speed of the falling edge. In addition, the second NMOS tube RvarThe conduction of the sub-ADC channel is controlled by the sel _ int signal, and when the sel _ int signal is low, the sub-ADC channel is not selected, and the sub-ADC channel controls the second NMOS transistor RvarIs turned off and passes through the third NMOS transistor MpdSampling the clock signal cksp _ bst<i>Stably pulled to the ground.
In this embodiment, the first capacitor CvarThe capacitance value of the binary capacitor array is adjustable. As shown in FIG. 6, each array capacitor C1 in the binary capacitor array is driven by a second control signal adj<0>To adj<n>And controlling whether the selected array capacitor C1 is selected, when the signal sel _ int output by the data output terminal 203 is high, the selected array capacitor C1 is charged or discharged along with the signal cksp _ new output by the first output terminal 102, and the unselected array capacitor C1 is grounded.
In this embodiment, a timing diagram of generating the sampling clock signal cksp _ bst < i > by using the system clock ck _ ADC and the sampling selection signal sel < i > of the time-interleaved ADC as combinational logic is shown in fig. 7, which only shows waveform diagrams of signals sel <0>, sel _ int <0> and cksp _ bst <0> corresponding to the sub-ADC No. 0.
The bootstrap sampling switch circuit provided by this embodiment has a simple structure, and is different from a conventional method of generating sampling clock signals of each sub-ADC channel through clock circuits such as a phase-locked loop, and the like, and completely discards a conventional method of generating a sampling clock by using a frequency division circuit, but generates a sampling clock signal cksp _ bst < i > by using a system clock ck _ ADC of a time-interleaved ADC and a sampling selection signal sel < i > of a sub-ADC channel generated by a digital platform as combinational logic, and a signal cksp _ new output by a first output terminal 102 used by each sub-ADC channel in this embodiment is generated by the same system clock ck _ ADC through combinational logic, thereby greatly reducing jitter. In addition, the signal cksp _ new output by the first output terminal is shared by a plurality of sub-ADC channels, so that the timing mismatch among the sub-ADC channels is greatly reduced.
In this embodiment, two important signals are involved, one is the signal cksp _ new output from the first output terminal 102, which is obtained by duty cycle adjustment of the system clock ck _ adc, as shown in fig. 8, and has only a very narrow low pulse, where the signal ckn _ adc is the signal output from the inverse delay unit 103 in fig. 4, and the delay between the signal and the system clock ck _ adc is td. Another is the sampling selection signal sel of the sub-ADC channel of the time-interleaved ADC accessed by the strobe input terminal 5<i>The signal determines whether the corresponding sub-ADC channel in the time-interleaved ADC is selected for sampling, thereby determining the working sequence of each sub-ADC channel of the time-interleaved ADC. Sampling selection signal sel<i>After being switched in the synchronization circuit 2, the clock signal is sampled and delayed by the system clock ck _ adc, so that the signal sel _ int output by the data output terminal 203 is generated and the rising and falling edges of the signal are both in the low level of the signal cksp _ new output by the first output terminal 102.
In this embodiment, the bootstrap sampling switchThe sampling clock signal cksp _ bst output by the clock output terminal 6 of the off-circuit<i>Is a power supply voltage VDDAnd the sum of the bias voltages pwr.
In this embodiment, the second NMOS transistor RvarThe on-resistance of the sampling clock signal cksp _ bst can be adjusted by the first control signal, and the sampling clock signal cksp _ bst output by the clock output terminal 6 can be further conveniently adjusted<i>The time parameter of the falling edge of the signal is changed, so that the speed of the falling edge of the signal is changed, and the adjustment of the time sequence deviation of each sub-ADC channel is further realized.
In this embodiment, the first capacitor C is adjustedvarRealizes the sampling clock signal cksp _ bst output by the clock output end 6<i>The adjustment of the high level of the ADC further realizes the adjustment of the sampling bandwidth of each sub-ADC channel. In this embodiment, the second control signal is controlled by an external digital platform, that is, whether each array capacitor in the binary capacitor array is selected is controlled, so as to implement the first capacitor CvarThe equivalent capacitance value of the clock output end 6 is adjustable, and the sampling clock signal cksp _ bst output by the clock output end 6 is further realized<i>High level adjustment.
Example 2
The difference between this embodiment and embodiment 1 is that the first capacitor CvarIs realized by using a circuit as shown in fig. 9. In contrast to fig. 6, fig. 9 shows the control of the first capacitance C by controlling the reset level of the capacitance during the reset phase, i.e. when the sel _ int _ n signal is highvarThe equivalent capacitance value of (c). If the array capacitor C1 is selected, i.e., the corresponding second control signal is high, then the lower plate of the capacitor is grounded during reset, and the upper plate is charged to the bias voltage pwr, so that the voltage of the array capacitor C1 is pwr. If the array capacitor C1 is not selected, then its lower plate is connected to pwr and its upper plate is pwr during reset, so the voltage of the capacitor is 0, similar to the absence of the array capacitor C1.
Example 3
As shown in fig. 10, the present embodiment provides a sample-and-hold circuit for a sub-ADC in a time-interleaved ADCThe sample-and-hold circuit comprises a sampling switch S3And the bootstrapped sampling switch circuit of embodiment 1, wherein the sampling clock signal cksp _ bst output by the clock output terminal<i>For controlling the sampling switch S3。
Example 4
This embodiment provides a time-interleaved ADC comprising a plurality of sub-ADCs, each of which comprises the sample-and-hold circuit of embodiment 3.
The time-interleaved ADC provided in this embodiment is different from the conventional method of generating the sampling clock signal of each sub-ADC channel through a clock circuit such as a phase-locked loop, and in this embodiment, the signal output by the first output end of each sub-ADC channel is generated by the same system clock through combinational logic, so that jitter is greatly reduced. In addition, the signal output by the first output end is shared by a plurality of sub-ADC channels, so that the time sequence mismatch among the sub-ADC channels is greatly reduced.
In this embodiment, the first capacitor C is adjustedvarRealizes the sampling clock signal cksp _ bst output by the clock output end<i>The adjustment of the high level of the ADC further realizes the adjustment of the sampling bandwidth of each sub-ADC channel.
In this embodiment, the second NMOS transistor RvarThe magnitude of the on-resistance can be adjusted by the first control signal, and further, the sampling clock signal cksp _ bst output by the clock output end can be conveniently adjusted<i>The time parameter of the falling edge of the signal is changed, so that the speed of the falling edge of the signal is changed, and the adjustment of the time sequence deviation of each sub-ADC channel is further realized.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (9)

1. A bootstrap sampling switch circuit is used for a time-interleaved ADC (analog to digital converter), and comprises a charge pump, a first capacitor, a first NMOS (N-channel metal oxide semiconductor) tube and a first PMOS (P-channel metal oxide semiconductor) tube, and is characterized in that the bootstrap sampling switch circuit further comprises a first clock input end, a gating input end, a clock output end, a duty ratio adjusting circuit, a synchronous circuit, a second NMOS tube and a third NMOS tube;
the gating input end is used for accessing a sampling selection signal of a sub-ADC of the time-interleaved ADC, the first clock input end is used for accessing a system clock of the time-interleaved ADC, the clock output end is used for outputting a sampling clock signal, and the sampling clock signal is used for controlling a sampling switch of a sampling holding circuit of the sub-ADC;
the duty ratio adjusting circuit comprises a first input end and a first output end, the first input end is electrically connected with the first clock input end, and the duty ratio adjusting circuit is used for increasing the duty ratio of a signal input by the first input end and outputting the signal to the first output end; the period of the signal output by the first output end is the same as that of the signal accessed by the first input end, and the falling edge of the signal output by the first output end is consistent with that of the signal accessed by the first input end;
the synchronous circuit comprises a data input end, a second clock input end and a data output end, wherein the data input end is electrically connected with the gating input end, and the second clock input end is electrically connected with the first clock input end; the data output end is electrically connected with the input end of the charge pump and the grid electrode of the second NMOS tube; the synchronous circuit is used for synchronously triggering the signal input by the data input end by adopting the signal input by the second clock input end and outputting the synchronously triggered signal to the data output end;
the output end of the charge pump is electrically connected with the grid electrode of the first NMOS tube;
one end of the first capacitor and the source electrode of the second NMOS tube are electrically connected with the data output end;
the drain electrode of the first PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the second NMOS tube are electrically connected with the clock output end;
the signal output by the data output end is inverted and then is connected to the grid electrode of the third NMOS tube, and the source electrode of the third NMOS tube is grounded;
the duty ratio adjusting circuit further comprises a reverse delayer and a NAND gate, wherein one input end of the NAND gate and the input end of the reverse delayer are electrically connected with the first input end, the output end of the reverse delayer is electrically connected with the other input end of the NAND gate, and the output end of the NAND gate is electrically connected with the first output end.
2. The bootstrapped sampling switch circuit of claim 1, wherein a source of the first NMOS transistor, another end of the first capacitor, and a source of the first PMOS transistor are electrically connected, and a drain of the first NMOS transistor, a gate of the first PMOS transistor, and the charge pump are all biased.
3. The bootstrapped sampled switch circuit of claim 1, wherein the synchronization circuit is a D flip-flop.
4. The bootstrapped sampled switch circuit of claim 3, wherein the D flip-flop comprises a D input, a CK input, a Q output, and
Figure FDA0002659201490000021
an output, the D input electrically connected with the data input, the CK input electrically connected with the second clock input, the Q output electrically connected with the data output, the Q output
Figure FDA0002659201490000022
The output end is connected to the grid electrode of the third NMOS tube.
5. The bootstrapped sampling switch circuit of claim 1, wherein the second NMOS transistor is a binary-sized NMOS transistor array, each NMOS transistor in the NMOS transistor array is an array NMOS transistor, a gate of the array NMOS transistor is electrically connected to an output terminal of an and gate, one input terminal of the and gate is electrically connected to the data output terminal, another input terminal of the and gate is connected to a first control signal, and the first control signal is used to control whether a corresponding array NMOS transistor is selected.
6. The bootstrapped sampled switch circuit of claim 1, wherein the first capacitor is a binary capacitor array, an equivalent capacitance value of the binary capacitor array being adjustable.
7. The bootstrapped sampled switch circuit of claim 6, wherein each array capacitor of said binary capacitor array is controlled by a second control signal to select, wherein said selected array capacitor is charged or discharged with a signal output from said first output terminal when a signal output from said data output terminal is high, and said unselected array capacitors are grounded.
8. A sample-and-hold circuit for a sub-ADC in an ADC of the time-interleaved type, the sample-and-hold circuit comprising a sample switch and a bootstrapped sample switch circuit as claimed in any one of claims 1 to 7, the sample clock signal output by the clock output for controlling the sample switch.
9. A time-interleaved ADC comprising a plurality of sub-ADCs, wherein each of said sub-ADCs comprises the sample-and-hold circuit of claim 8.
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