CN110429930A - Lower reset circuit and power supply device - Google Patents
Lower reset circuit and power supply device Download PDFInfo
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- CN110429930A CN110429930A CN201910809852.8A CN201910809852A CN110429930A CN 110429930 A CN110429930 A CN 110429930A CN 201910809852 A CN201910809852 A CN 201910809852A CN 110429930 A CN110429930 A CN 110429930A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Abstract
The present invention relates to a kind of lower reset circuit and power supply devices, when the input voltage of linear voltage regulator is less than predetermined voltage threshold, output reset signal, and by latch module latch reset signal, keep reset signal effective when electric under input voltage.Finally, the first switch end and second switch end of semiconductor switch pipe is connected by when the controlled end of semiconductor switch pipe receives reset signal.It is released the output end charge of linear voltage regulator by semiconductor switch pipe, accelerates electric discharge.The speed and reliability of electric discharge are improved while reducing the volume of reset circuit based on this.
Description
Technical field
The present invention relates to electronic circuit technology fields, more particularly to a kind of lower reset circuit and power supply device.
Background technique
Integrated circuit voltage regulator of the linear voltage regulator as a new generation, it is possible to provide stable supply voltage is widely used
In MCU system.Traditional linear voltage regulator generally has ena-bung function, when a system is powered up, under the action of enable signal,
Linear voltage regulator works in effective status.When system is powered down or linear voltage regulator work is in sleep state, linear voltage regulator
Power tube be turned off, output load capacitance is discharged by load resistance and feedback resistance.When load capacitance is larger, load is electric
When resistance and feedback resistance are all bigger, discharge time can be long.Normally, discharge time is usually the magnitude of second.At this point, such as
When high-frequency switching or shake occurs in fruit enable signal, the power tube of linear voltage regulator can quickly be connected and to output loading electricity
Hold constantly charging, since discharge time is long, will result in output voltage and be continuously increased.When charge accumulation to a certain extent
It will cause device failure relevant to output voltage, linear voltage regulator is negative in device and system including linear voltage regulator itself
Carry device.
In traditional linear voltage regulator, the lower reset of linear voltage regulator is met generally by RC reset circuit.
However, being easy to occupy excessive circuit layout, it is difficult to adapt to increasingly developed modern work since the volume of RC reset circuit is larger
Skill requirement.
Summary of the invention
Based on this, it is necessary to it is larger for the volume of RC reset circuit, it is easy to occupy excessive circuit layout, it is difficult to adapt to
Increasingly developed modern crafts requirement provides a kind of lower reset circuit and power supply device.
A kind of lower reset circuit, comprising:
Voltage detection module；Voltage detection module is used to detect the input voltage of linear voltage regulator, is less than in input voltage
When predetermined voltage threshold, output reset signal；
Latch module；Latch module is used for latch reset signal；
Semiconductor switch pipe；The controlled end of semiconductor switch pipe be used to access it is latched after reset signal, semiconductor opens
The first switch end for closing pipe is used to access the output voltage of linear voltage regulator, and the second switch end of semiconductor switch pipe is for connecting
Common end；Semiconductor switch pipe is used to that semiconductor switch pipe to be connected when the controlled end of semiconductor switch pipe accesses reset signal
First switch end and second switch end.
Above-mentioned lower reset circuit, when the input voltage of linear voltage regulator is less than predetermined voltage threshold, output resets letter
Number, and by latch module latch reset signal, keep reset signal effective when electric under input voltage.Finally, by half
When the controlled end of conductor switching tube receives reset signal, the first switch end and second switch end of semiconductor switch pipe is connected.
It is released the output end charge of linear voltage regulator by semiconductor switch pipe, accelerates electric discharge.Based on this, in the body for reducing reset circuit
While product, the speed and reliability of electric discharge are improved.
In one of the embodiments, further include:
Voltage domain conversion module；Voltage domain conversion module is used to reset signal being converted to output voltage.
Voltage detection module includes: in one of the embodiments,
Electrical level judging unit；Electrical level judging unit is less than predetermined voltage threshold for detecting input voltage, in input voltage
When export first switch signal, input voltage be greater than predetermined voltage threshold when export second switch signal；
Partial pressure unit；Partial pressure unit one end is for accessing input voltage；
Controlled switch；The other end of the first switch end connection partial pressure unit of controlled switch, the second switch of controlled switch
End is for connecting common end；Controlled switch for when receiving first switch signal be connected controlled switch first switch end and
Otherwise second switch end disconnects the first switch end and second switch end of controlled switch；
Non- gate cell；The first switch end of the input terminal connection controlled switch of non-gate cell, the output end of non-gate cell are used
In output reset signal.
Electrical level judging unit includes: in one of the embodiments,
First PMOS tube；The source electrode of first PMOS tube is for accessing input voltage, the grid connection first of the first PMOS tube
The drain electrode of PMOS tube；
Second PMOS tube；The source electrode of second PMOS tube connects the drain electrode of the first PMOS tube, the grid connection of the second PMOS tube
The drain electrode of second PMOS tube, the drain electrode of the second PMOS tube is for exporting first switch signal or second switch signal；
Third PMOS tube；The source electrode of third PMOS tube connects the drain electrode of the second PMOS tube, the grid connection of third PMOS tube
The drain electrode of third PMOS tube, the drain electrode of third PMOS tube is for connecting common end.
Controlled switch includes: in one of the embodiments,
First NMOS tube；The other end of the drain electrode connection partial pressure unit of first NMOS tube, the source electrode of the first NMOS tube are used for
Connect common end；The grid of first NMOS tube is for receiving first switch signal or second switch signal.
Non- gate cell includes Schmitt trigger in one of the embodiments,.
Voltage domain conversion module includes: in one of the embodiments,
4th PMOS tube；The source electrode of 4th PMOS tube is for accessing input voltage, and the grid of the 4th PMOS tube is for accessing
Reset signal.
5th PMOS tube；The source electrode of 5th PMOS tube is for accessing output voltage, the grid connection the 4th of the 5th PMOS tube
The drain electrode of PMOS tube；
6th PMOS tube；The source electrode of 6th PMOS tube is for accessing output voltage, the grid connection the 5th of the 6th PMOS tube
The drain electrode of PMOS tube, the controlled end of the drain electrode connection semiconductor switch pipe of the 6th PMOS tube；
Second NMOS tube；The grid of second NMOS tube connects the grid of the 4th PMOS tube, the drain electrode connection of the second NMOS tube
The drain electrode of 4th PMOS tube, the source electrode of the second NMOS tube is for connecting common end；
Third NMOS tube；The grid of third NMOS tube connects the grid of the 5th PMOS tube, the drain electrode connection of third NMOS tube
The drain electrode of 5th PMOS tube, the source electrode of third NMOS tube is for connecting common end；
4th NMOS tube；The grid of 4th NMOS tube connects the grid of the 6th PMOS tube, the drain electrode connection of the 4th NMOS tube
The drain electrode of 6th PMOS tube, the source electrode of the 4th NMOS tube is for connecting common end.
Latch module includes: in one of the embodiments,
7th PMOS tube；The source electrode of 7th PMOS tube is for accessing input voltage；
8th PMOS tube；The source electrode of 8th PMOS tube is for accessing input voltage；
9th PMOS tube；The drain electrode of drain electrode the 8th PMOS tube of connection of 9th PMOS tube, the source electrode connection of the 9th PMOS tube
The grid of 7th PMOS tube；
Tenth PMOS tube；The grid of tenth PMOS tube is for accessing reset signal, and the source electrode of the tenth PMOS tube is for accessing
Input voltage, the drain electrode of drain electrode the 9th PMOS tube of connection of the tenth PMOS tube；
11st PMOS tube；The source electrode of 11st PMOS tube connects for accessing input voltage, the grid of the 11st PMOS tube
Connect the drain electrode of the 7th PMOS tube；
12nd PMOS tube；The drain electrode of drain electrode the 11st PMOS tube of connection of 12nd PMOS tube, the 12nd PMOS tube
Source electrode connects the source electrode of the 9th PMOS tube；
13rd PMOS tube；The source electrode of 13rd PMOS tube connects for accessing input voltage, the grid of the 13rd PMOS tube
Connect the source electrode of the 12nd PMOS tube, the grid of drain electrode the 8th PMOS tube of connection of the 13rd PMOS tube, the leakage of the 13rd PMOS tube
Pole is also used to export the reset signal after latching；
14th PMOS tube；The source electrode of 14th PMOS tube connects for accessing input voltage, the drain electrode of the 14th PMOS tube
The grid of the 12nd PMOS tube is connect, the grid of the 14th PMOS tube connects the grid of the 9th PMOS tube；
5th NMOS tube；The drain electrode of drain electrode the 7th PMOS tube of connection of 5th NMOS tube, the grid connection of the 5th NMOS tube
The grid of 7th PMOS tube, the source electrode of the 5th NMOS tube is for connecting common end；
6th NMOS tube；The source electrode of 6th NMOS tube connects the source electrode of the 9th PMOS tube, the grid connection of the 6th NMOS tube
The drain electrode of 14th PMOS tube；
7th NMOS tube；The drain electrode of drain electrode the 6th NMOS tube of connection of 7th NMOS tube, the grid connection of the 7th NMOS tube
The drain electrode of 13rd PMOS tube, the source electrode of the 7th NMOS tube is for connecting common end；
8th NMOS tube；The source electrode of 8th NMOS tube connects the source electrode of the 12nd PMOS tube, and the grid of the 8th NMOS tube connects
Connect the grid of the 14th PMOS tube；
9th NMOS tube；The drain electrode of drain electrode the 8th NMOS tube of connection of 9th NMOS tube, the grid connection of the 9th NMOS tube
The drain electrode that 7th PMOS is closed, the source electrode of the 9th NMOS tube is for connecting common end；
Tenth NMOS tube；The drain electrode of drain electrode the 13rd PMOS tube of connection of tenth NMOS tube, the grid of the tenth NMOS tube connect
The grid of the 13rd PMOS tube is connect, the source electrode of the tenth NMOS tube is for connecting common end；
11st NMOS tube；The drain electrode of drain electrode the 14th PMOS tube of connection of 11st NMOS tube, the 11st NMOS tube
Grid connects the grid of the 14th PMOS tube, and the source electrode of the 11st NMOS tube is for connecting common end.
Semiconductor switch pipe includes the 12nd NMOS tube in one of the embodiments,；
The grid of 12nd NMOS tube is for accessing reset signal, and the drain electrode of the 12nd NMOS tube is for accessing output electricity
Pressure, the source electrode of the 12nd NMOS tube is for connecting common end.
A kind of power supply device, the lower reset circuit including linear voltage regulator and any of the above-described embodiment.
Above-mentioned power supply device, when the input voltage of linear voltage regulator is less than predetermined voltage threshold, output reset signal, and
By latch module latch reset signal, keep reset signal effective when electric under input voltage.Finally, by being opened in semiconductor
When the controlled end of pass pipe receives reset signal, the first switch end and second switch end of semiconductor switch pipe is connected.Pass through half
Conductor switching tube is released the output end charge of linear voltage regulator, and electric discharge is accelerated.Based on this, the same of the volume of reset circuit is being reduced
When, improve the speed and reliability of electric discharge.
Detailed description of the invention
Fig. 1 is the lower reset circuit function structure chart of an embodiment；
Fig. 2 is the voltage detection module structure chart of an embodiment；
Fig. 3 is the voltage detection module circuit diagram of an embodiment；
Fig. 4 is the latch module circuit diagram of an embodiment；
Fig. 5 is the lower reset circuit function structure chart of another embodiment；
Fig. 6 is the voltage domain conversion module circuit diagram of an embodiment；
Fig. 7 is the power supply device modular structure schematic diagram of an embodiment.
Specific embodiment
Purpose, technical solution and technical effect for a better understanding of the present invention, below in conjunction with drawings and examples
Further explaining illustration is carried out to the present invention.State simultaneously, embodiments described below for explaining only the invention, not
For limiting the present invention.
The embodiment of the invention provides a kind of lower reset circuits.
Fig. 1 is the lower reset circuit function structure chart of an embodiment, as shown in Figure 1, replying by cable under an embodiment
Position circuit includes module 100 to 102:
Voltage detection module 100；Voltage detection module is used to detect the input voltage VDD1 of linear voltage regulator, in input electricity
When VDD1 being pressed to be less than predetermined voltage threshold, output reset signal；
Wherein, the input terminal voltage of linear voltage regulator is input voltage VDD1, and the output end voltage of linear voltage regulator is defeated
Voltage VDD2 out.Voltage detection module 100 detects the input voltage VDD1 of linear voltage regulator, is less than in input voltage VDD1 default
When voltage threshold, output reset signal.Wherein, input voltage VDD1 is less than the input of predetermined voltage threshold characterization linear voltage regulator
Hold under-voltage, electric under system board level power supply, input voltage VDD1 can be continued to decline.
Fig. 2 is the voltage detection module structure chart of an embodiment in one of the embodiments, as shown in Fig. 2, voltage
Detection module 100 includes module 200 to 203:
Electrical level judging unit 200；Electrical level judging unit is less than pre- for detecting input voltage VDD1 in input voltage VDD1
If exporting first switch signal when voltage threshold, the output second switch letter when input voltage VDD1 is greater than predetermined voltage threshold
Number；
Wherein, electrical level judging unit 200 accesses input voltage VDD1, when input voltage VDD1 is less than predetermined voltage threshold
Export first switch signal, i.e. reset signal.Second switch signal is exported when input voltage VDD1 is greater than predetermined voltage threshold.
Fig. 3 is the voltage detection module circuit diagram of an embodiment in one of the embodiments, as shown in figure 3, level
Judging unit 200 includes:
First PMOS tube MP1；The source electrode of first PMOS tube MP1 is used to access input voltage VDD1, the first PMOS tube MP1's
Grid connects the drain electrode of the first PMOS tube MP1；
Second PMOS tube MP2；The source electrode of second PMOS tube MP2 connects the drain electrode of the first PMOS tube MP1, the second PMOS tube
The grid of MP2 connects the drain electrode of the second PMOS tube MP2, and the drain electrode of the second PMOS tube MP2 is for exporting first switch signal or the
Two switching signals；
Third PMOS tube MP3；The source electrode of third PMOS tube MP3 connects the drain electrode of the second PMOS tube MP2, third PMOS tube
The drain electrode of the grid connection third PMOS tube MP3 of MP3, the drain electrode of third PMOS tube MP3 is for connecting common end VSS.
As shown in figure 3, when input voltage VDD1 is less than predetermined voltage threshold, the first PMOS tube MP1 and the second PMOS tube
MP2 conducting, third PMOS tube MP3 shutdown, input voltage VDD1 are exported as first switch signal.It is less than in input voltage VDD1
When predetermined voltage threshold, the first PMOS tube MP1 and the second PMOS tube MP2 conducting, third PMOS tube MP3 shutdown, input voltage
VDD1 is exported as first switch signal.When input voltage VDD1 is greater than predetermined voltage threshold, the first PMOS tube MP1, second
PMOS tube MP2 conducting and third PMOS tube MP3 conducting, common end VSS voltage are exported as second switch signal.
Partial pressure unit 201；Partial pressure unit one end is for accessing input voltage VDD1；
In one of the embodiments, as shown in figure 3, partial pressure unit 201 includes resistance R1.
Controlled switch 202；The other end of the first switch end connection partial pressure unit of controlled switch, the second of controlled switch open
Guan Duan is for connecting common end VSS；Controlled switch is opened for the first of controlled switch to be connected when receiving first switch signal
Otherwise Guan Duan and second switch end disconnect the first switch end and second switch end of controlled switch；
Wherein, controlled switch 202 is when receiving first switch signal, first switch end and the conducting of second switch end.
When receiving second switch signal, first switch end and the shutdown of second switch end.
In one of the embodiments, as shown in figure 3, controlled switch 202 includes:
First NMOS tube MN1；The other end of the drain electrode connection partial pressure unit of first NMOS tube MN1, the first NMOS tube MN1's
Source electrode is for connecting common end VSS；The grid of first NMOS tube MN1 is for receiving first switch signal or second switch signal.
Wherein, when receiving first switch signal, i.e. input voltage VDD1, the first NMOS tube MN1 meets turn-on condition,
First NMOS tube MN1 conducting.Common end VSS signal is exported to non-gate cell 203.
Non- gate cell 203；The first switch end of the input terminal connection controlled switch of non-gate cell, the output end of non-gate cell
For output reset signal.
Wherein, the signal that non-gate cell 203 is exported for the first switch end of reverse phase controlled switch.As shown in figure 3, defeated
When entering voltage VDD1 less than predetermined voltage threshold, non-gate cell 203 exports the inversion signal of common end VSS signal.
In one of the embodiments, as shown in figure 3, non-gate cell includes Schmitt trigger SMIT.
Latch module 101；Latch module is used for latch reset signal；
Wherein, latch module 101 is used for latch reset signal.Since input voltage VDD1 is continued to decline, by latching mould
Block 101 keeps reset signal effective during input voltage VDD1 declines, and prevents from leaking electricity.
Latch module 101 selects latch or latch cicuit in one of the embodiments,.
Fig. 4 is the latch module circuit diagram of an embodiment, as shown in figure 4, latch module 101 includes:
7th PMOS tube MP7；The source electrode of 7th PMOS tube MP7 is for accessing input voltage VDD1；
8th PMOS tube MP8；The source electrode of 8th PMOS tube MP8 is for accessing input voltage VDD1；
9th PMOS tube MP9；The drain electrode of the 8th PMOS tube MP8 of drain electrode connection of 9th PMOS tube MP9, the 9th PMOS tube
The source electrode of MP9 connects the grid of the 7th PMOS tube MP7；
Tenth PMOS tube MP10；The grid of tenth PMOS tube MP10 is for accessing reset signal POR, the tenth PMOS tube MP10
Source electrode for accessing input voltage VDD1, the drain electrode of the 9th PMOS tube MP9 of drain electrode connection of the tenth PMOS tube MP10；
11st PMOS tube MP11；The source electrode of 11st PMOS tube MP11 is for accessing input voltage VDD1, and the 11st
The grid of PMOS tube MP11 connects the drain electrode of the 7th PMOS tube MP7；
12nd PMOS tube MP12；The drain electrode of the 11st PMOS tube MP11 of drain electrode connection of 12nd PMOS tube MP12, the
The source electrode of 12 PMOS tube MP12 connects the source electrode of the 9th PMOS tube MP9；
13rd PMOS tube MP13；The source electrode of 13rd PMOS tube MP13 is for accessing input voltage VDD1, and the 13rd
The grid of PMOS tube MP13 connects the source electrode of the 12nd PMOS tube MP12, and the drain electrode of the 13rd PMOS tube MP13 connects the 8th PMOS
The grid of pipe MP8, the drain electrode of the 13rd PMOS tube MP13 are also used to export the reset signal after latching；
14th PMOS tube MP14；The source electrode of 14th PMOS tube MP14 is for accessing input voltage VDD1, and the 14th
The grid of the 12nd PMOS tube MP12 of drain electrode connection of PMOS tube MP14, the grid of the 14th PMOS tube MP14 connect the 9th PMOS
The grid of pipe MP9；
5th NMOS tube MN5；The drain electrode of the 7th PMOS tube MP7 of drain electrode connection of 5th NMOS tube MN5, the 5th NMOS tube
The grid of MN5 connects the grid of the 7th PMOS tube MP7, and the source electrode of the 5th NMOS tube MN5 is for connecting common end VSS；
6th NMOS tube MN6；The source electrode of 6th NMOS tube MN6 connects the source electrode of the 9th PMOS tube MP9, the 6th NMOS tube
The grid of MN6 connects the drain electrode of the 14th PMOS tube MP14；
7th NMOS tube MN7；The drain electrode of the 6th NMOS tube MN6 of drain electrode connection of 7th NMOS tube MN7, the 7th NMOS tube
The grid of MN7 connects the drain electrode of the 13rd PMOS tube MP13, and the source electrode of the 7th NMOS tube MN7 is for connecting common end VSS；
8th NMOS tube MN8；The source electrode of 8th NMOS tube MN8 connects the source electrode of the 12nd PMOS tube MP12, the 8th NMOS
The grid of pipe MN8 connects the grid of the 14th PMOS tube MP14；
9th NMOS tube MN9；The drain electrode of the 8th NMOS tube MN8 of drain electrode connection of 9th NMOS tube MN9, the 9th NMOS tube
The grid of MN9 connects the drain electrode that the 7th PMOS is closed, and the source electrode of the 9th NMOS tube MN9 is for connecting common end VSS；
Tenth NMOS tube MN10；The drain electrode of the 13rd PMOS tube MP13 of drain electrode connection of tenth NMOS tube MN10, the tenth
The grid of NMOS tube MN10 connects the grid of the 13rd PMOS tube MP13, and the source electrode of the tenth NMOS tube MN10 is for connecting common end
VSS；
11st NMOS tube MN11；The drain electrode of the 14th PMOS tube MP14 of drain electrode connection of 11st NMOS tube MN11, the
The grid of 11 NMOS tube MN11 connects the grid of the 14th PMOS tube MP14, and the source electrode of the 11st NMOS tube MN11 is for connecting
Common end VSS.
Semiconductor switch pipe 102；The controlled end of semiconductor switch pipe is for accessing reset signal, and the of semiconductor switch pipe
One switch terminals are used to access the output voltage VDD2 of linear voltage regulator, and the second switch end of semiconductor switch pipe is public for connecting
Hold VSS；Semiconductor switch pipe is used for when the controlled end of semiconductor switch pipe accesses reset signal, conducting semiconductor switch pipe
First switch end and second switch end.
Wherein, the reset signal after latch module 101 latches is exported to semiconductor switch 102, semiconductor switch 102 by
After controlling end reception reset signal, the first switch end of semiconductor switch pipe and the conducting of second switch end, output voltage VDD2 is through half
The output of conductor switching tube 102 is released output voltage VDD2 by semiconductor switch pipe 102, completes electric discharge to common end VSS.
Wherein, latch module 101 includes triode or metal-oxide-semiconductor.Semiconductor switch pipe includes in one of the embodiments,
12nd NMOS tube；
The grid of 12nd NMOS tube is for accessing reset signal, and the drain electrode of the 12nd NMOS tube is for accessing output voltage
VDD2, the source electrode of the 12nd NMOS tube is for connecting common end VSS.
When the grid of 12nd NMOS tube receives reset signal, the 12nd NMOS transistor conduction, output voltage VDD2 is through
12 NMOS tubes complete electric discharge.
Fig. 5 is the lower reset circuit function structure chart of another embodiment in one of the embodiments, such as Fig. 5 institute
Show, the lower reset circuit of another embodiment further includes voltage domain conversion module 300；Voltage domain conversion module 300 is used for will
Reset signal is converted to output voltage VDD2.
Wherein, reset signal is converted to output voltage VDD2 by voltage domain conversion module 300, defeated to solve linear voltage regulator
Enter voltage domain between end and output end to convert, guarantees that reset signal can drive semiconductor switch pipe 102 to be connected.
Fig. 6 is the voltage domain conversion module circuit diagram of an embodiment in one of the embodiments, as shown in fig. 6, electric
Pressure domain conversion module 300 include:
4th PMOS tube MP4；The source electrode of 4th PMOS tube MP4 is used to access input voltage VDD1, the 4th PMOS tube MP4's
Grid is for accessing reset signal.
5th PMOS tube MP5；The source electrode of 5th PMOS tube MP5 is used to access output voltage VDD2, the 5th PMOS tube MP5's
Grid connects the drain electrode of the 4th PMOS tube MP4；
6th PMOS tube MP6；The source electrode of 6th PMOS tube MP6 is used to access output voltage VDD2, the 6th PMOS tube MP6's
Grid connects the drain electrode of the 5th PMOS tube MP5, the controlled end of the drain electrode connection semiconductor switch pipe of the 6th PMOS tube MP6；
Second NMOS tube MN2；The grid of second NMOS tube MN2 connects the grid of the 4th PMOS tube MP4, the second NMOS tube
The drain electrode of the 4th PMOS tube MP4 of drain electrode connection of MN2, the source electrode of the second NMOS tube MN2 is for connecting common end VSS；
Third NMOS tube MN3；The grid of third NMOS tube MN3 connects the grid of the 5th PMOS tube MP5, third NMOS tube
The drain electrode of the 5th PMOS tube MP5 of drain electrode connection of MN3, the source electrode of third NMOS tube MN3 is for connecting common end VSS；
4th NMOS tube MN4；The grid of 4th NMOS tube MN4 connects the grid of the 6th PMOS tube MP6, the 4th NMOS tube
The drain electrode of the 6th PMOS tube MP6 of drain electrode connection of MN4, the source electrode of the 4th NMOS tube MN4 is for connecting common end VSS.
As shown in fig. 6, after the grid access reset signal of the 4th PMOS tube MP4, the 6th PMOS tube MP6 conducting, the 4th
NMOS tube MN4 shutdown, output voltage VDD2 are exported to the controlled end of semiconductor switch pipe 102.
Above-mentioned lower reset circuit, when the input voltage VDD1 of linear voltage regulator is less than predetermined voltage threshold, output is multiple
Position signal, and by 101 latch reset signal of latch module, keep reset signal effective when electric at input voltage VDD1.Most
Afterwards, by the way that when the controlled end of semiconductor switch pipe 102 receives reset signal, the first of conducting semiconductor switch pipe 102 is opened
Guan Duan and second switch end.It is released the output end charge of linear voltage regulator by semiconductor switch pipe 102, accelerates electric discharge.It is based on
This improves the speed and reliability of electric discharge while reducing the volume of reset circuit.
The embodiment of the present invention also provides a kind of power supply device.
Fig. 7 is the power supply device modular structure schematic diagram of an embodiment, as shown in fig. 7, the power supply of an embodiment fills
Set the lower reset circuit 401 including linear voltage regulator 400 and any of the above-described embodiment.
Above-mentioned power supply device, when the input voltage VDD1 of linear voltage regulator 400 is less than predetermined voltage threshold, output resets
Signal, and by 101 latch reset signal of latch module, keep reset signal effective when electric at input voltage VDD1.Finally,
By the way that the first switch end of semiconductor switch pipe 102 is connected when the controlled end of semiconductor switch pipe 102 receives reset signal
With second switch end.It is released the output end charge of linear voltage regulator 400 by semiconductor switch pipe 102, accelerates electric discharge.It is based on
This improves the speed and reliability of electric discharge while reducing the volume of reset circuit.
Each technical characteristic of above embodiments can be combined arbitrarily, for simplicity of description, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, the combination of these technical characteristics be not present lance
Shield all should be considered as described in this specification.
Only several embodiments of the present invention are expressed for above embodiments, and the description thereof is more specific and detailed, but can not
Therefore it is construed as limiting the scope of the patent.It should be pointed out that for those of ordinary skill in the art, In
Under the premise of not departing from present inventive concept, various modifications and improvements can be made, and these are all within the scope of protection of the present invention.
Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of lower reset circuit characterized by comprising
Voltage detection module；The voltage detection module is used to detect the input voltage of linear voltage regulator, in the input voltage
When less than predetermined voltage threshold, output reset signal；
Latch module；The latch module is for latching the reset signal；
Semiconductor switch pipe；The controlled end of the semiconductor switch pipe be used for access it is latched after the reset signal, it is described
The first switch end of semiconductor switch pipe is used to access the output voltage of the linear voltage regulator, and the of the semiconductor switch pipe
Two switch terminals are for connecting common end；The semiconductor switch pipe, which is used to access in the controlled end of the semiconductor switch pipe, to be resetted
When signal, the first switch end and second switch end of the semiconductor switch pipe is connected.
2. lower reset circuit according to claim 1, which is characterized in that further include:
Voltage domain conversion module；The voltage domain conversion module is used to the reset signal being converted to the output voltage.
3. lower reset circuit according to claim 1, which is characterized in that the voltage detection module includes:
Electrical level judging unit；The electrical level judging unit is less than default for detecting the input voltage in the input voltage
First switch signal is exported when voltage threshold, and second switch signal is exported when the input voltage is greater than predetermined voltage threshold；
Partial pressure unit；Described partial pressure unit one end is for accessing the input voltage；
Controlled switch；The first switch end of the controlled switch connects the other end of the partial pressure unit, the controlled switch
Second switch end is for connecting common end；The controlled switch be used to be connected when receiving the first switch signal it is described by
The first switch end and second switch end for controlling switch, otherwise disconnect the first switch end and second switch end of the controlled switch；
Non- gate cell；The input terminal of the non-gate cell connects the first switch end of the controlled switch, the non-gate cell
Output end is for exporting the reset signal.
4. lower reset circuit according to claim 3, which is characterized in that the electrical level judging unit includes:
First PMOS tube；The source electrode of first PMOS tube is for accessing the input voltage, the grid of first PMOS tube
Connect the drain electrode of first PMOS tube；
Second PMOS tube；The source electrode of second PMOS tube connects the drain electrode of first PMOS tube, second PMOS tube
Grid connects the drain electrode of second PMOS tube, and the drain electrode of second PMOS tube is for exporting first switch signal or second opening
OFF signal；
Third PMOS tube；The source electrode of the third PMOS tube connects the drain electrode of second PMOS tube, the third PMOS tube
Grid connects the drain electrode of the third PMOS tube, and the drain electrode of the third PMOS tube is for connecting common end.
5. lower reset circuit according to claim 3, which is characterized in that the controlled switch includes:
First NMOS tube；The drain electrode of first NMOS tube connects the other end of the partial pressure unit, first NMOS tube
Source electrode is for connecting common end；The grid of first NMOS tube is for receiving the first switch signal or second switch letter
Number.
6. lower reset circuit according to claim 3, which is characterized in that the non-gate cell includes Schmitt triggering
Device.
7. lower reset circuit according to claim 2, which is characterized in that the voltage domain conversion module includes:
4th PMOS tube；The source electrode of 4th PMOS tube is for accessing the input voltage, the grid of the 4th PMOS tube
For accessing the reset signal；
5th PMOS tube；The source electrode of 5th PMOS tube is for accessing the output voltage, the grid of the 5th PMOS tube
Connect the drain electrode of the 4th PMOS tube；
6th PMOS tube；The source electrode of 6th PMOS tube is for accessing the output voltage, the grid of the 6th PMOS tube
The drain electrode of the 5th PMOS tube is connected, the drain electrode of the 6th PMOS tube connects the controlled end of the semiconductor switch pipe；
Second NMOS tube；The grid of second NMOS tube connects the grid of the 4th PMOS tube, second NMOS tube
Drain electrode connects the drain electrode of the 4th PMOS tube, and the source electrode of second NMOS tube is for connecting common end；
Third NMOS tube；The grid of the third NMOS tube connects the grid of the 5th PMOS tube, the third NMOS tube
Drain electrode connects the drain electrode of the 5th PMOS tube, and the source electrode of the third NMOS tube is for connecting common end；
4th NMOS tube；The grid of 4th NMOS tube connects the grid of the 6th PMOS tube, the 4th NMOS tube
Drain electrode connects the drain electrode of the 6th PMOS tube, and the source electrode of the 4th NMOS tube is for connecting common end.
8. according to claim 1 to lower reset circuit described in 7 any one, which is characterized in that the latch module includes:
7th PMOS tube；The source electrode of 7th PMOS tube is for accessing the input voltage；
8th PMOS tube；The source electrode of 8th PMOS tube is for accessing the input voltage；
9th PMOS tube；The drain electrode of 9th PMOS tube connects the drain electrode of the 8th PMOS tube, the 9th PMOS tube
Source electrode connects the grid of the 7th PMOS tube；
Tenth PMOS tube；The grid of tenth PMOS tube is for accessing the reset signal, the source electrode of the tenth PMOS tube
For accessing the input voltage, the drain electrode of the tenth PMOS tube connects the drain electrode of the 9th PMOS tube；
11st PMOS tube；The source electrode of 11st PMOS tube is for accessing the input voltage, the 11st PMOS tube
Grid connect the drain electrode of the 7th PMOS tube；
12nd PMOS tube；The drain electrode of drain electrode connection the 11st PMOS tube of 12nd PMOS tube, the described 12nd
The source electrode of PMOS tube connects the source electrode of the 9th PMOS tube；
13rd PMOS tube；The source electrode of 13rd PMOS tube is for accessing the input voltage, the 13rd PMOS tube
Grid connect the source electrode of the 12nd PMOS tube, the drain electrode of the 13rd PMOS tube connects the grid of the 8th PMOS tube
Pole, the drain electrode of the 13rd PMOS tube are also used to export the reset signal after latching；
14th PMOS tube；The source electrode of 14th PMOS tube is for accessing the input voltage, the 14th PMOS tube
Drain electrode connect the grid of the 12nd PMOS tube, the grid of the 14th PMOS tube connects the grid of the 9th PMOS tube
Pole；
5th NMOS tube；The drain electrode of 5th NMOS tube connects the drain electrode of the 7th PMOS tube, the 5th NMOS tube
Grid connects the grid of the 7th PMOS tube, and the source electrode of the 5th NMOS tube is for connecting common end；
6th NMOS tube；The source electrode of 6th NMOS tube connects the source electrode of the 9th PMOS tube, the 6th NMOS tube
Grid connects the drain electrode of the 14th PMOS tube；
7th NMOS tube；The drain electrode of 7th NMOS tube connects the drain electrode of the 6th NMOS tube, the 7th NMOS tube
Grid connects the drain electrode of the 13rd PMOS tube, and the source electrode of the 7th NMOS tube is for connecting common end；
8th NMOS tube；The source electrode of 8th NMOS tube connects the source electrode of the 12nd PMOS tube, the 8th NMOS tube
Grid connect the grid of the 14th PMOS tube；
9th NMOS tube；The drain electrode of 9th NMOS tube connects the drain electrode of the 8th NMOS tube, the 9th NMOS tube
Grid connects the drain electrode that the 7th PMOS is closed, and the source electrode of the 9th NMOS tube is for connecting common end；
Tenth NMOS tube；The drain electrode of tenth NMOS tube connects the drain electrode of the 13rd PMOS tube, the tenth NMOS tube
Grid connect the grid of the 13rd PMOS tube, the source electrode of the tenth NMOS tube is for connecting common end；
11st NMOS tube；The drain electrode of drain electrode connection the 14th PMOS tube of 11st NMOS tube, the described 11st
The grid of NMOS tube connects the grid of the 14th PMOS tube, and the source electrode of the 11st NMOS tube is for connecting common end.
9. according to claim 1 to lower reset circuit described in 7 any one, which is characterized in that the semiconductor switch pipe
Including the 12nd NMOS tube；
The grid of 12nd NMOS tube is for accessing the reset signal, and the drain electrode of the 12nd NMOS tube is for accessing
The output voltage, the source electrode of the 12nd NMOS tube is for connecting common end.
10. a kind of power supply device, which is characterized in that including linear voltage regulator and as claimed in any one of claims 1 to 9
Lower reset circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910809852.8A CN110429930A (en) | 2019-08-29 | 2019-08-29 | Lower reset circuit and power supply device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910809852.8A CN110429930A (en) | 2019-08-29 | 2019-08-29 | Lower reset circuit and power supply device |
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ID=68418106
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| CN201910809852.8A Pending CN110429930A (en) | 2019-08-29 | 2019-08-29 | Lower reset circuit and power supply device |
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