CN103856189B - Pulsed flip-flop - Google Patents
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- CN103856189B CN103856189B CN201210507608.4A CN201210507608A CN103856189B CN 103856189 B CN103856189 B CN 103856189B CN 201210507608 A CN201210507608 A CN 201210507608A CN 103856189 B CN103856189 B CN 103856189B
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Abstract
A kind of pulsed flip-flop, respond first and second clock signal, latch data input signal, to be converted into data output signal, pulsed flip-flop comprises pulse generator and latch unit, pulse generator comprises the first phase inverter and signal delay circuit, in order to receive the first clock signal and to produce the second clock signal；And latch unit comprises transfer circuit, latch circuit and control circuit.Latch unit responds first and second clock signal, and in order to latch data input signal and export data output signal, wherein transfer circuit is in order to transmit data input signal；Latch circuit is electrically connected at transfer circuit, in order to receiving and latch data input signal, and exports data output signal；And control circuit is electrically connected at latch circuit, in order to provide the Push And Release of Control of Voltage latch circuit.
Description
Technical field
The invention relates to a kind of flip-flop (flip-flop, FF), and in particular to a kind of pulsed flip-flop.
Background technology
In recent years, due to various portable and consumption electronic products (for example: smart mobile phone, digital camera, notebook
Computer and the sensing system etc. of medical application) universal, the deisgn approach low-power of electronic product, low-work voltage and low
The design of electric leakage.
Flip-flop (flip-flop, FF) is a kind of circuit elements storing data according to the edge-triggered of clock signal
Part, the dynamic power that general flip-flop is consumed and leakage current account for the 40 ~ 60% of total system, are highly energy-consuming, height
The component of electric leakage.
Pulsed flip-flop (pulse-based flip-flop) is by a pulse generator (pulse generator) and a latch unit
(data latch) is formed, and typically when designing pulsed flip-flop, reduces only emphatically dynamic power, and cannot drop simultaneously
Low-leakage current and operating voltage.For example, with dynamic circuit (dynamic circuit), dominoes circuit (domino
Circuit) the pulsed flip-flop and designed by pre-charge circuit (pre-charged circuit) is all difficult under low-work voltage
To maintain correct logic running.
Additionally, the latch unit in most pulsed flip-flops often uses two phase inverters docking (that is output of a phase inverter
End is connected on the input of another phase inverter), easily there is the situation that electric current is competed when writing data.
Therefore, design the pulsed flip-flop of low-power, low-work voltage and Low dark curient, and avoid occurring electric current competing
Situation about striving, has its necessity.
Content of the invention
One aspect of the present invention is to provide a kind of pulsed flip-flop, utilizes the design of control circuit in latch unit in it,
Block the DC current path in latch unit, reduce power consumption and leakage current.
One embodiment of the invention with regard to a kind of pulsed flip-flop, pulsed flip-flop response the first clock signal and the
Two clock signals, latch data input signal, be converted to data output signal to enter data into signal, pulsed is just
Anti-device comprises pulse generator and latch unit.Pulse generator is in order to receive the first clock signal and to produce the second clock pulse
Signal, it comprises the first phase inverter and signal delay circuit, and the first phase inverter is in order to receive the first clock signal defeated
Go out the second clock signal；Signal delay circuit is electrically connected at the first phase inverter, in order to receive the second clock signal and to prolong
Slow second clock signal.Latch unit response the first clock signal and the second clock signal, in order to latch data input letter
Number and export data output signal, it comprises transfer circuit, latch circuit and control circuit, and transfer circuit is in order to pass
Delivery data input signal；Latch circuit is electrically connected at transfer circuit, in order to receiving and latch data input signal, and
And output data output signal；Control circuit is electrically connected at latch circuit, in order to provide Control of Voltage latch circuit
Push And Release.
Brief description
Fig. 1 is according to a kind of pulse generator circuit figure depicted in one embodiment of the invention.
Fig. 2 is according to the clock signal waveform diagram depicted in one embodiment of the invention.
Fig. 3 is according to a kind of data latching device circuit diagram depicted in one embodiment of the invention.
Fig. 4 is according to a kind of data output signal waveform diagram depicted in one embodiment of the invention.
Fig. 5 is according to a kind of data output signal waveform diagram depicted in another embodiment of the present invention.
[main element symbol description]
100: pulse generator
120th, the 140th, the 345th, the 350th, the 355th, 380: phase inverter
160: signal delay circuit
300: latch unit
320: control circuit
340: latch circuit
360: transfer circuit
365th, the 370th, 375: switch element
Detailed description of the invention
Hereafter institute accompanying drawings is coordinated to elaborate for embodiment, but the embodiment being provided be not used to limit the present invention
The scope being covered, and the description of structure operation is not used to limit its order performing, any is reconfigured by element
Structure, is produced the device with impartial effect, is all the scope that the present invention is covered.Additionally, it is graphic only with explanation
For the purpose of, and not according to life size mapping.
It is commonly error or the model of exponential quantity with regard to " about " used herein, " about " or " substantially "
Enclose within 20 percent, be preferably within 10, be more preferably then within 5 percent.Literary composition
If without clearly stating in, its mentioned numerical value all regards as approximation, i.e. such as " about ", " about " or " substantially "
Represented error or scope.
The following embodiment of the present invention discloses a kind of pulsed flip-flop, and it reduces leakage current by way of transistor stacks,
Therefore having extremely low dynamic power consumption, this pulsed flip-flop simultaneously designs for low electricity in the way of static circuit
The working environment of pressure.
Pulsed flip-flop comprises a pulse generator (pulse generator) and a data latching device (data latch), rings
Answer the first clock signal CLK and the second clock signal CLKB, latch data input signal D, and enter data into
Signal D is converted to data output signal Q.Following pulse generator and the data latching device of being respectively directed to is made specifically
Bright.
Fig. 1 is according to a kind of pulse generator circuit figure depicted in one embodiment of the invention.Pulse generator 100 wraps
Containing the first phase inverter 120 and signal delay circuit 160, it is in order to receive the first clock signal CLK and to produce second
Clock signal CLKB, wherein the second clock signal CLKBPhase place be phase place anti-phase of the first clock signal CLK.
First phase inverter 120 further includes the 9th nmos pass transistor MN9, and the first phase inverter 120 in order to receive first when
Arteries and veins signal CLK simultaneously exports the second clock signal CLKB, signal delay circuit 160 is electrically connected at the first phase inverter
120, in order to receive the second clock signal CLKBAnd postpone the second clock signal CLKB。
Above-mentioned signal delay circuit 160 comprises the second phase inverter 140 and the first nmos pass transistor MN1, its
In the second phase inverter 140 comprise the tenth nmos pass transistor MN10 and the 7th PMOS transistor MP7, and
Two phase inverters 140 are electrically connected at the first phase inverter 120, in order to receive the second clock signal CLKB, and a NMOS
The grid (gate) of transistor MN1 is electrically connected at the output of the second phase inverter 140, in order to the second phase inverter 140
Jointly act on to postpone the second clock signal CLKB。
From the foregoing, pulse generator can receive the first clock signal CLK and produce the second clock pulse that is anti-phase and that postpone
Signal CLKB.For the sake of for convenience of description, referring to Fig. 1 and Fig. 2, Fig. 2 is according to one embodiment of the invention
Depicted clock signal waveform diagram.
As shown in Figure 2, the first clock signal CLK was logic low originally, through the first phase inverter 120 shown in Fig. 1
The second clock signal CLK of logic high is produced after receptionB, make the transistor MN10 in the second phase inverter 140
The state being on.Owing to the drain electrode of transistor MN10 and the grid of transistor MN1 connect, now transistor
MN1 is the state closed.When the first positive edge of clock signal CLK trigger and by logic low conversion to logically high electricity
At ordinary times, the second clock signal CLKBShould be changed to logic low by logic high, but because of the second phase inverter 140
And the common effect of transistor MN1, and postpone the second clock signal CLKBChange to the time of logic low.
More specifically, trigger when the first positive edge of clock signal CLK and changed to logic high by logic low
When, the transistor MN9 in the first phase inverter is converted to conducting state by closed mode, now because of transistor MN1 still
Do not turn on, cause the second clock signal CLKBThe drain charge to transistor MN1 in discharge process, and make crystal
The current potential of pipe MN1 rises, and then causes the electric current flowing through transistor MN9 less and less, therefore the second clock signal
CLKBSlowly conversion is to logic low.Due to the second clock signal CLKBConversion is delayed to the speed of logic low
Slowly, power supply supply current potential VDDSlow to the transistor MP7 charging in the second phase inverter 140, and transistor MP7
Drain electrode connect with the grid of transistor MN1, delay crystal pipe MN1 conducting time, just postpone again the second clock pulse
Signal CLKBChange to the time of logic low.
As in figure 2 it is shown, as the first clock signal CLK and the second clock signal CLKBWhen being all logic high,
Both can be considered as a pulse signal, be positioned at data latching device thereafter with control, in this regard, have more detailed below
Explanation.
Fig. 3 is according to a kind of data latching device circuit diagram depicted in one embodiment of the invention.Latch unit 300 responds
One clock signal CLK and the second clock signal CLKB, in order to latch data input signal D and export data output
Signal Q, it comprises transfer circuit the 360th, latch circuit 340 and control circuit 320.Transfer circuit 360 is in order to pass
Delivery data input signal D, latch circuit 340 is electrically connected at transfer circuit 360, defeated in order to receive simultaneously latch data
Enter signal D, and export data output signal Q.And control circuit 320 is electrically connected at latch circuit 340, use
To provide the switch of Control of Voltage latch circuit 340.
When data input signal D input is to latch unit 300, control circuit 320 controls latch circuit 340 makes its nothing
Charging current path, it is to avoid produce the situation of current drain when data input signal D input is to latch unit 300, with
Under will be described in more detail for this.
As it is shown on figure 3, control circuit 320 comprise first, second, third and the 4th PMOS transistor MP1,
MP2, MP3 and MP4.The grid of the first PMOS transistor MP1 is anti-phase in data input signal in order to receive
The inverted data input signal DB of D, and its source electrode (source) be electrically connected at power supply supply current potential VDD.Second
The grid of PMOS transistor MP2 is in order to receiving data input signal D, and its source electrode is electrically connected at power supply supply electricity
Position VDD。
The grid of the 3rd PMOS transistor MP3 is in order to receiving the first clock signal CLK, and its source electrode is electrically connected with
In the drain electrode of the drain electrode (drain) of transistor MP1 or transistor MP2, its drain electrode is electrically connected at transistor MP2's
Drain electrode or the drain electrode of transistor MP1.And the grid of the 4th PMOS transistor MP4 is in order to receive the second clock signal
CLKB, and its source electrode is electrically connected at the source electrode of transistor MP3, its drain electrode is electrically connected at the leakage of transistor MP3
Pole.
Then, latch circuit 340 comprises the 3rd phase inverter the 345th, the 4th phase inverter 350 and the 5th phase inverter 355.
The input of the 3rd phase inverter 345 is electrically connected at first node Q1, and its output is electrically connected at Section Point
Q2, and the 4th phase inverter 350 docks with the 3rd phase inverter 345, that is the input of the 4th phase inverter 350 electrically connects
It is connected to Section Point Q2, and its output is electrically connected at first node Q1.The input electricity of the 5th phase inverter 355
Property is connected to first node Q1, and its output is in order to export data output signal Q.
Wherein the 3rd phase inverter 345 comprises the 5th PMOS transistor MP5 and the second nmos pass transistor MN2,
5th PMOS transistor MP5 is series at the transistor MP1 in control circuit 320, and the second nmos pass transistor
MN2 is series at transistor MP5, and its grid is electrically connected at the grid of transistor MP5, and its source electrode is connected to ground connection
Voltage VSS.In addition, the 4th phase inverter 350 comprises the 6th PMOS transistor MP6 and the 3rd NMOS crystal
Pipe MN3, the 6th PMOS transistor MP6 is series at the transistor MP2 in control circuit 320, and the 3rd NMOS
Transistor MN3 is series at transistor MP6, and its grid is electrically connected at the grid of transistor MP6, and its source electrode connects
In ground voltage VSS。
Then comprise the first switch element the 365th, second switch element the 370th, the 3rd switch element as transfer circuit 360
375 and hex inverter 380, the first switch element 365 is electrically connected at first node Q1, believes in the first clock pulse
Number CLK and the second clock signal CLKBOpen when being all logic high；Second switch element 370 is electrically connected with
In Section Point Q2, also in the first clock signal CLK and the second clock signal CLKBWhen being all logic high
Open.3rd switch element 375 be electrically coupled to the output of second switch element the 370th, hex inverter 380 with
And ground voltage VSS, open when data input signal D is logic low.And the input of hex inverter 380
End is in order to receiving data input signal D, and its output is electrically connected at the first switch element 365.
More specifically, the first switch element 365 can comprise the 4th nmos pass transistor MN4 and the 5th NMOS
Transistor MN5, wherein the grid of transistor MN4 is in order to receiving the first clock signal CLK, and transistor MN5
Grid in order to receive the second clock signal CLKB.Second switch element 370 can comprise the 6th nmos pass transistor
MN6 and the 7th nmos pass transistor MN7, wherein the grid of transistor MN6 is in order to receive the first clock signal
CLK, and the grid of transistor MN7 is in order to receive the second clock signal CLKB.3rd switch element 375 can be
Eight nmos pass transistor MN8, and its grid is in order to receive the oppisite phase data that hex inverter 380 output is exported
Input signal DB.
As the first clock signal CLK and the second clock signal CLKBIt is all logic high, and when data input letter
When number D is also for logic high, the first switch element 365 and second switch element 370 can turn on, the 3rd switch
Element 375 is then controlled by the inverted data input signal DB of logic low and closes.Due to the first switch element 365
Conducting, the voltage level of first node Q1 is equal to the voltage level of hex inverter 380 output, and now counts
It is logic high according to input signal D, therefore the voltage level of hex inverter 380 output is logic low, the
The voltage level of one node Q1 is also logic low.
For control circuit 320, transistor MP1, MP2, MP3 and MP4 are inputted by oppisite phase data respectively
Signal DB, data input signal D, the first clock signal CLK and the second clock signal CLKBControlled, because of
This is as the first clock signal CLK and the second clock signal CLKBIt is all logic high, and work as data input signal
When D is also for logic high, transistor MP1 turns on, and transistor MP2, MP3 and MP4 are all open circuit.
Ask for an interview Fig. 3, when transistor MP1 and MP5 is respectively by inverted data input signal DB and first node
When Q1 control is opened, Section Point Q2 can supply current potential V because of power supplyDDTo transistor MP1 and MP5 institute shape
Become path and be converted to logic high, then by transistor MN3 open.Therefore, transistor MP1, MP5 with
And MN3 is conducting state, there is no DC current (direct current, DC) and supply current potential V from power supplyDDIt flow to ground connection
Current potential VSS.And the data input signal D of logic high through hex inverter the 380th, the first switch element 365 with
And the 5th after phase inverter 355, from the data output signal Q of the output output logic high of the 5th phase inverter 355.
Owing to the transistor MP2 in control circuit 320 is closed mode, and the first node Q1 control of logic low
Transistor MN2 processed closes, and the Section Point Q2 control transistor MP6 of logic high closes, therefore latch circuit
340 without DC current path, does not produces charging current and causes electric current conflict, can be applicable to the system of low-work voltage.
Fig. 4 is data output signal waveform diagram when data input signal is logic high.As shown in Figure 4,
As the first clock signal CLK and the second clock signal CLKBIt also is all logic high and data input signal D
During for logic high, as explained above, data output signal Q is from the output institute of the 5th phase inverter 355 of Fig. 3
Output, is converted to logic high from logic low.
On the other hand, for the sake of for convenience of description, referring to Fig. 3 and Fig. 5.As the first clock signal CLK and
Second clock signal CLKBIt is all logic high, and when data input signal D is logic low, in Fig. 3
Second switch element 370 can turn on, the 3rd switch element 375 is by the inverted data input signal DB of logic high
Control is also switched on.Owing to second switch element 370 turns on, the voltage level of Section Point Q2 is logic low,
The grid of transistor MP6 is controlled and turns on.
For control circuit 320, transistor MP1, MP2, MP3 and MP4 are inputted by oppisite phase data respectively
Signal DB, data input signal D, the first clock signal CLK and the second clock signal CLKBControlled, because of
This is as the first clock signal CLK and the second clock signal CLKBIt is all logic high, and work as data input signal
When D is logic low, transistor MP2 turns on, and transistor MP1, MP3 and MP4 are all open circuit.
Ask for an interview Fig. 3, when transistor MP2 and MP6 is controlled by data input signal D and Section Point Q2 respectively
When making opened, first node Q1 can supply current potential V because of power supplyDDFormed to transistor MP2 and MP6
Path and be converted to logic high, by transistor MN2 open.Therefore, transistor MP2, MP6 and MN2
For conducting state, there is no DC current and supply current potential V from power supplyDDIt flow to earthing potential VSS.And now first node
The voltage level of Q1 is logic high, therefore the data i.e. producing logic low through the 5th phase inverter 355 after anti-phase are defeated
Go out signal Q.
Owing to the transistor MP1 in control circuit 320 is closed mode, and the Section Point Q2 control of logic low
Transistor MN3 processed closes, and the first node Q1 control transistor MP5 of logic high closes, therefore latch unit 340
Path without DC current, does not produces charging current and causes electric current conflict, can be applicable to the system of low-work voltage.
Fig. 5 is data output signal waveform diagram when data input signal is logic low.As shown in Figure 5,
As the first clock signal CLK and the second clock signal CLKBIt is all logic high and data input signal D is
During logic low, as explained above, data output signal Q is defeated from the output institute of the 5th phase inverter 355 of Fig. 3
Go out, be converted to logic low from logic high.
In sum, the present invention discloses a kind of pulsed flip-flop, and it comprises pulse generator and latch unit.Pulse
Generator uses five transistors to realize, effectively reduces electronic circuit layout area and cost, and in latch unit
Control circuit coordinate the design of transfer circuit also to block DC current path, effectively reduce operation power and leakage current,
And can be applicable to the system of low-work voltage.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any is familiar with this skill
Person, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations, the therefore protection of the present invention
Scope ought be as the criterion depending on the defined person of appended claims.
Claims (11)
1. a pulsed flip-flop, response one first clock signal and one second clock signal, breech lock one data are defeated
Entering signal, so that this data input signal is converted to a data output signal, this pulsed flip-flop comprises:
One pulse generator, in order to receive this first clock signal and to produce this second clock signal, this pulse generator
Comprise:
One first phase inverter, in order to receive this first clock signal and to export this second clock signal；
One signal delay circuit, is electrically connected at this first phase inverter, in order to receive this second clock signal and to prolong
This second clock signal slow；And
One latch unit, responds this first clock signal and this second clock signal, in order to this data input signal of breech lock
And export this data output signal, this latch unit comprises:
One transfer circuit, in order to transmit this data input signal；
One latch circuit, is electrically connected at this transfer circuit, in order to receiving and this data input signal of breech lock, and
And export this data output signal；And
One control circuit, is electrically connected at this latch circuit, in order to provide this latch circuit of Control of Voltage open with
Closing, this control circuit comprises:
One first PMOS transistor, the grid of this first PMOS transistor is anti-phase in this data in order to receive
One inverted data input signal of input signal, and the source electrode of this first PMOS transistor be electrically connected at one electricity
Current potential is supplied in source；
One second PMOS transistor, the grid of this second PMOS transistor is in order to receive this data input letter
Number, and the source electrode of this second PMOS transistor be electrically connected at this power supply supply current potential；
One the 3rd PMOS transistor, the grid of the 3rd PMOS transistor is in order to receive this first clock pulse letter
Number, and the source electrode of the 3rd PMOS transistor be electrically connected at this first PMOS transistor drain electrode or should
The drain electrode of the second PMOS transistor, when the source electrode of the 3rd PMOS transistor be electrically connected at this first
During the drain electrode of PMOS transistor, the drain electrode of the 3rd PMOS transistor is electrically connected at the 2nd PMOS
The drain electrode of transistor, when the source electrode of the 3rd PMOS transistor is electrically connected at this second PMOS transistor
Drain electrode when, the drain electrode of the 3rd PMOS transistor is electrically connected at the drain electrode of this first PMOS transistor；
And
One the 4th PMOS transistor, the grid of the 4th PMOS transistor is in order to receive this second clock pulse letter
Number, and the source electrode of the 4th PMOS transistor is electrically connected at the source electrode of the 3rd PMOS transistor, should
The drain electrode of the 4th PMOS transistor is electrically connected at the drain electrode of the 3rd PMOS transistor.
2. pulsed flip-flop as claimed in claim 1, it is characterised in that this signal delay circuit comprises:
One second phase inverter, is electrically connected at this first phase inverter, in order to receive this second clock signal；And
One first nmos pass transistor, the grid of this first nmos pass transistor is electrically connected at this second phase inverter
Output, in order to this this second clock signal of common delayed action of the second phase inverter.
3. pulsed flip-flop as claimed in claim 2, it is characterised in that the phase place of this second clock signal is for being somebody's turn to do
The phase place of the first clock signal anti-phase.
4. pulsed flip-flop as claimed in claim 1, it is characterised in that this latch circuit comprises:
One the 3rd phase inverter, the input of the 3rd phase inverter is electrically connected at a first node, and the 3rd phase inverter
Output be electrically connected at a Section Point；And
One the 4th phase inverter, the input of the 4th phase inverter is electrically connected at this Section Point, and the 4th phase inverter
Output be electrically connected at this first node.
5. pulsed flip-flop as claimed in claim 4, it is characterised in that the 3rd phase inverter comprises:
One the 5th PMOS transistor, is series at this first PMOS transistor；And
One second nmos pass transistor, is series at the 5th PMOS transistor, and this second nmos pass transistor
Grid is electrically connected at the grid of the 5th PMOS transistor, and the source electrode of this second nmos pass transistor is connected to one
Ground voltage.
6. pulsed flip-flop as claimed in claim 5, it is characterised in that the 4th phase inverter comprises:
One the 6th PMOS transistor, is series at this second PMOS transistor；And
One the 3rd nmos pass transistor, is series at the 6th PMOS transistor, and the 3rd nmos pass transistor
Grid is electrically connected at the grid of the 6th PMOS transistor, and the source electrode of the 3rd nmos pass transistor is connected to this
Ground voltage.
7. pulsed flip-flop as claimed in claim 6, it is characterised in that this latch circuit further includes:
One the 5th phase inverter, the input of the 5th phase inverter is electrically connected at this first node, and the 5th phase inverter
Output in order to export this data output signal.
8. pulsed flip-flop as claimed in claim 7, it is characterised in that this transfer circuit comprises:
One first switch element, is electrically connected at this first node, this first switch element in this first and this second
Clock signal is opened when being all logic high；And
One hex inverter, the input of this hex inverter is in order to receiving this data input signal, and the 6th is anti-phase
The output of device is electrically connected at this first switch element.
9. pulsed flip-flop as claimed in claim 8, it is characterised in that when this first and this second clock pulse letter
It number is all logic high, and when this data input signal is also for logic high, this first switching elements conductive,
This first PMOS transistor, the 5th PMOS transistor and the 3rd nmos pass transistor are also conducting state.
10. pulsed flip-flop as claimed in claim 8, it is characterised in that this transfer circuit further includes:
One second switch element, is electrically connected at this Section Point, this second switch element in this first and this second
Clock signal is opened when being all logic high；And
One the 3rd switch element, be electrically coupled to this second switch element, this hex inverter this output and should
Ground voltage, the 3rd switch element is opened when this data input signal is logic low.
11. pulsed flip-flops as claimed in claim 10, it is characterised in that when this first and this second clock pulse
Signal is all logic high, and when this data input signal is logic low, this second switch element and should
3rd switching elements conductive, this second PMOS transistor, the 6th PMOS transistor and the 2nd NMOS
Transistor is also conducting state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210507608.4A CN103856189B (en) | 2012-11-30 | 2012-11-30 | Pulsed flip-flop |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210507608.4A CN103856189B (en) | 2012-11-30 | 2012-11-30 | Pulsed flip-flop |
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| CN103856189A CN103856189A (en) | 2014-06-11 |
| CN103856189B true CN103856189B (en) | 2016-11-09 |
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| KR102596875B1 (en) * | 2016-11-23 | 2023-11-01 | 삼성전자주식회사 | Flip flop |
| US10879899B2 (en) * | 2017-08-15 | 2020-12-29 | Realtek Semiconductor Corp. | Clock buffer and method thereof |
| TWI658697B (en) * | 2018-08-02 | 2019-05-01 | 崛智科技有限公司 | Data latch circuit and pulse signal generator thereof |
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| US8373483B2 (en) * | 2011-02-15 | 2013-02-12 | Nvidia Corporation | Low-clock-energy, fully-static latch circuit |
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|---|---|---|---|---|
| US6075748A (en) * | 1997-11-28 | 2000-06-13 | Mosaid Technologies Incorporated | Address counter cell |
| US7237164B1 (en) * | 2004-04-15 | 2007-06-26 | Marvell International Ltd. | Area optimized edge-triggered flip-flop for high-speed memory dominated design |
| CN101127517A (en) * | 2006-08-16 | 2008-02-20 | 联发科技股份有限公司 | Adjustable delay compensation circuit |
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| Title |
|---|
| A Low-Power Radix-4 Viterbi Decoder Based on DCVSPG Pulsed Latch with Sharing Technique;Xin-Ru Lee等;《Circuits and Systems (APCCAS)》;20101209;第1203页至1206页 * |
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| Publication number | Publication date |
|---|---|
| CN103856189A (en) | 2014-06-11 |
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