CN103856189A - Pulse-based flip-flop - Google Patents
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- CN103856189A CN103856189A CN201210507608.4A CN201210507608A CN103856189A CN 103856189 A CN103856189 A CN 103856189A CN 201210507608 A CN201210507608 A CN 201210507608A CN 103856189 A CN103856189 A CN 103856189A
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Abstract
A pulse-based flip-flop responses to first and second clock pulse signals and latch a data input signal so as to convert the data input signal to a data output signal. The pulse-based flip-flop contains a pulse generator and a data latch. The pulse generator contains a first inverter and a signal delay circuit and is used for receiving the first clock pulse signal and generating the second clock pulse signal. The data latch contains a transfer circuit, a latch circuit and a control circuit. The data latch responses to first and second clock pulse signals and is used for latching a data input signal and outputting a data output signal. The transfer circuit is used for transferring the data input signal. The latch circuit is electrically connected with the transfer circuit and is used for receiving and latching the data input signal and outputting the data output signal. The control circuit is electrically connected with the latch circuit and is used for providing voltage to control on/off of the latch circuit.
Description
Technical field
The invention relates to a kind of flip-flop (flip-flop, FF), and relate to especially a kind of pulsed flip-flop.
Background technology
In recent years, for example, due to popularizing of various Portables and consumption electronic products (: the sensing system of smart mobile phone, digital camera, notebook computer and medical application etc.), the design of deisgn approach low-power, low-work voltage and the low electric leakage of electronic product.
Flip-flop (flip-flop, FF) be a kind of circuit element data being stored according to the edge-triggered of clock signal, dynamic power and leakage current that general flip-flop consumes account for 40 ~ 60% of total system, are the circuit element of highly energy-consuming, high electric leakage.
Pulsed flip-flop (pulse-based flip-flop) is made up of a pulse generator (pulse generator) and a latch unit (data latch), generally in the time of design pulsed flip-flop, only reduce emphatically dynamic power, and cannot reduce leakage current and operating voltage simultaneously.For example, under low-work voltage, be all difficult to dynamic circuit (dynamic circuit), dominoes circuit (domino circuit) and the designed pulsed flip-flop of pre-charge circuit (pre-charged circuit) the logic running that remains correct.
In addition normal two inverter docking (that is the output of an inverter is connected on the input of another inverter), the easy situation that electric current competition occurs in the time of data writing of using of the latch unit in most pulsed flip-flops.
Therefore, the pulsed flip-flop of design low-power, low-work voltage and low electric leakage, and avoid the situation that electric current is competed occurs, there is its necessity.
Summary of the invention
An aspect of the present invention is that a kind of pulsed flip-flop is being provided, and utilizes the design of control circuit in latch unit in it, and the direct current path in blocking-up latch unit, reduces power consumption and leakage current.
One embodiment of the invention is about a kind of pulsed flip-flop, pulsed flip-flop responds the first clock signal and the second clock signal, latch data input signal, so that data input signal is converted to data output signal, pulsed flip-flop comprises pulse generator and latch unit.Pulse generator is in order to receive the first clock signal and to produce the second clock signal, and it comprises the first inverter and signal delay circuit, and the first inverter is in order to receive the first clock signal and to export the second clock signal; Signal delay circuit is electrically connected at the first inverter, in order to receive the second clock signal and to postpone the second clock signal.Latch unit responds the first clock signal and the second clock signal, and in order to latch data input signal and export data output signal, it comprises transfer circuit, latch circuit and control circuit, and transfer circuit is in order to transmit data input signal; Latch circuit is electrically connected at transfer circuit, in order to receive and latch data input signal, and output data output signal; Control circuit is electrically connected at latch circuit, in order to the Push And Release of voltage control latch circuit to be provided.
Accompanying drawing explanation
Fig. 1 is a kind of pulse generator circuit diagram illustrating according to one embodiment of the invention.
Fig. 2 is the clock signal waveform schematic diagram illustrating according to one embodiment of the invention.
Fig. 3 is a kind of data latching device circuit diagram illustrating according to one embodiment of the invention.
Fig. 4 is a kind of data output signal waveform schematic diagram illustrating according to one embodiment of the invention.
Fig. 5 is a kind of data output signal waveform schematic diagram illustrating according to another embodiment of the present invention.
[main element symbol description]
100: pulse generator
120,140,345,350,355,380: inverter
160: signal delay circuit
300: latch unit
320: control circuit
340: latch circuit
360: transfer circuit
365,370,375: switch element
Embodiment
Below coordinate appended graphic elaborating for embodiment, but the scope that the embodiment providing is not contained in order to limit the present invention, and the description of structure running is non-in order to limit the order of its execution, any structure being reconfigured by element, the device with impartial effect that produces, is all the scope that the present invention is contained.In addition, graphic only for the purpose of description, do not map according to life size.
About " approximately " used herein, " approximately " generally typically refer to " roughly " error of numerical value or scope in 20 percent, be preferably in 10, be in 5 percent more preferably.Wen Zhongruo is without clearly stating, and its mentioned numerical value is all regarded as approximation, as " approximately ", " approximately " or " roughly " represented error or scope.
The following embodiment of the present invention discloses a kind of pulsed flip-flop, and its mode stacking by transistor reduces leakage current, therefore has extremely low dynamic power consumption, and this pulsed flip-flop also designs the operational environment for low-voltage in the mode of static circuit.
Pulsed flip-flop comprises a pulse generator (pulse generator) and a data latching device (data latch), response the first clock signal CLK and the second clock signal CLK
b, latch data input signal D, and data input signal D is converted to data output signal Q.Following elaborating for pulse generator and data latching device respectively.
Fig. 1 is a kind of pulse generator circuit diagram illustrating according to one embodiment of the invention.Pulse generator 100 comprises the first inverter 120 and signal delay circuit 160, and it is in order to receive the first clock signal CLK and to produce the second clock signal CLK
b, wherein the second clock signal CLK
bphase place be phase place anti-phase of the first clock signal CLK.The first inverter 120 more comprises the 9th nmos pass transistor MN9, and the first inverter 120 is in order to receive the first clock signal CLK and to export the second clock signal CLK
b, signal delay circuit 160 is electrically connected at the first inverter 120, in order to receive the second clock signal CLK
band postpone the second clock signal CLK
b.
Above-mentioned signal delay circuit 160 comprises the second inverter 140 and the first nmos pass transistor MN1, wherein the second inverter 140 comprises the tenth nmos pass transistor MN10 and the 7th PMOS transistor MP7, and the second inverter 140 is electrically connected at the first inverter 120, in order to receive the second clock signal CLK
b, and the grid of the first nmos pass transistor MN1 (gate) is electrically connected at the output of the second inverter 140, in order to the second inverter 140 actings in conjunction to postpone the second clock signal CLK
b.
From the above, pulse generator can receive the first clock signal CLK and produce the second clock signal CLK anti-phase and that postpone
b.For convenience of description, referring to Fig. 1 and Fig. 2, Fig. 2 is the clock signal waveform schematic diagram illustrating according to one embodiment of the invention.
As shown in Figure 2, the first clock signal CLK was logic low originally, produced the second clock signal CLK of logic high after the first inverter 120 shown in Fig. 1 receives
b, make transistor MN10 in the second inverter 140 state in conducting.Because the drain electrode of transistor MN10 and the grid of transistor MN1 join, now transistor MN1 is the state of closing.While being converted to logic high when the positive edge triggering of the first clock signal CLK by logic low, the second clock signal CLK
bshould be converted to logic low by logic high, but because of the acting in conjunction of the second inverter 140 and transistor MN1, and postpone the second clock signal CLK
bbe converted to the time of logic low.
More specifically, while being converted to logic high when the positive edge triggering of the first clock signal CLK by logic low, transistor MN9 in the first inverter is converted to conducting state by closed condition, now because of not yet conducting of transistor MN1, causes the second clock signal CLK
bdrain charge to transistor MN1 in discharge process, and make the current potential of transistor MN1 increase, and then the electric current of the transistor MN9 that causes flowing through is more and more less, therefore the second clock signal CLK
bslowly be converted to logic low.Due to the second clock signal CLK
bthe speed that is converted to logic low is slow, power supply supply current potential V
dDto the transistor MP7 charging in the second inverter 140 slowly, and the grid of the drain electrode of transistor MP7 and transistor MN1 joins, and the time of delay crystal pipe MN1 conducting, just postpones again the second clock signal CLK
bbe converted to the time of logic low.
As shown in Figure 2, as the first clock signal CLK and the second clock signal CLK
bwhile being all logic high, both can be considered as to a pulse signal, to control the data latching device being positioned at thereafter, to this, below have more detailed description.
Fig. 3 is a kind of data latching device circuit diagram illustrating according to one embodiment of the invention.Latch unit 300 responds the first clock signal CLK and the second clock signal CLK
b, in order to latch data input signal D and export data output signal Q, it comprises transfer circuit 360, latch circuit 340 and control circuit 320.Transfer circuit 360 is in order to transmit data input signal D, and latch circuit 340 is electrically connected at transfer circuit 360, in order to receive and latch data input signal D, and output data output signal Q.And control circuit 320 is electrically connected at latch circuit 340, in order to the switch of voltage control latch circuit 340 to be provided.
In the time that data input signal D inputs to latch unit 300, control circuit 320 is controlled latch circuit 340 makes it without charging current path, avoid the situation that generation current consumes in the time that data input signal D inputs to latch unit 300, below will be described in more detail for this.
As shown in Figure 3, control circuit 320 comprises first, second, third and the 4th PMOS transistor MP1, MP2, MP3 and MP4.The grid of the one PMOS transistor MP1 is anti-phase in the oppisite phase data input signal DB of data input signal D in order to receive, and its source electrode (source) is electrically connected at power supply supply current potential V
dD.The grid of the 2nd PMOS transistor MP2 is in order to receive data input signal D, and its source electrode is electrically connected at power supply supply current potential V
dD.
The grid of the 3rd PMOS transistor MP3 is in order to receive the first clock signal CLK, and its source electrode is electrically connected at the drain electrode (drain) of transistor MP1 or the drain electrode of transistor MP2, its drain electrode is electrically connected at the drain electrode of transistor MP2 or the drain electrode of transistor MP1.And the grid of the 4th PMOS transistor MP4 is in order to receive the second clock signal CLK
b, and its source electrode is electrically connected at the source electrode of transistor MP3, and its drain electrode is electrically connected at the drain electrode of transistor MP3.
Then, latch circuit 340 comprises the 3rd inverter 345, the 4th inverter 350 and the 5th inverter 355.The input of the 3rd inverter 345 is electrically connected at first node Q1, and its output is electrically connected at Section Point Q2, and the 4th inverter 350 docks with the 3rd inverter 345, that is the input of the 4th inverter 350 is electrically connected at Section Point Q2, and its output is electrically connected at first node Q1.The input of the 5th inverter 355 is electrically connected at first node Q1, and its output is in order to export data output signal Q.
Wherein the 3rd inverter 345 comprises the 5th PMOS transistor MP5 and the second nmos pass transistor MN2, the 5th PMOS transistor MP5 is series at the transistor MP1 in control circuit 320, and the second nmos pass transistor MN2 is series at transistor MP5, its grid is electrically connected at the grid of transistor MP5, and its source electrode is connected in earthed voltage V
sS.In addition, the 4th inverter 350 comprises the 6th PMOS transistor MP6 and the 3rd nmos pass transistor MN3, the 6th PMOS transistor MP6 is series at the transistor MP2 in control circuit 320, and the 3rd nmos pass transistor MN3 is series at transistor MP6, its grid is electrically connected at the grid of transistor MP6, and its source electrode is connected in earthed voltage V
sS.
Comprise the first switch element 365, second switch element 370, the 3rd switch element 375 and hex inverter 380 as for 360 of transfer circuits, the first switch element 365 is electrically connected at first node Q1, in the first clock signal CLK and the second clock signal CLK
bwhile being all logic high, open; Second switch element 370 is electrically connected at Section Point Q2, also in the first clock signal CLK and the second clock signal CLK
bwhile being all logic high, open.The 3rd switch element 375 is electrically coupled to output and the earthed voltage V of second switch element 370, hex inverter 380
sS, in the time that data input signal D is logic low, open.And the input of hex inverter 380 is in order to receive data input signal D, and its output is electrically connected at the first switch element 365.
More specifically, the first switch element 365 can comprise the 4th nmos pass transistor MN4 and the 5th nmos pass transistor MN5, and wherein the grid of transistor MN4 is in order to receive the first clock signal CLK, and the grid of transistor MN5 is in order to receive the second clock signal CLK
b.Second switch element 370 can comprise the 6th nmos pass transistor MN6 and the 7th nmos pass transistor MN7, and wherein the grid of transistor MN6 is in order to receive the first clock signal CLK, and the grid of transistor MN7 is in order to receive the second clock signal CLK
b.The 3rd switch element 375 can be the 8th nmos pass transistor MN8, and the oppisite phase data input signal DB that exports in order to receive hex inverter 380 outputs of its grid.
As the first clock signal CLK and the second clock signal CLK
bbe all logic high, and in the time that data input signal D is also logic high, the first switch element 365 and the 370 meeting conductings of second switch element, the 3rd 375 of switch elements are subject to the oppisite phase data input signal DB of logic low control and close.Due to the first switch element 365 conductings, the voltage level of first node Q1 is equal to the voltage level of hex inverter 380 outputs, and now data input signal D is logic high, therefore the voltage level of hex inverter 380 outputs is logic low, the voltage level of first node Q1 is also logic low.
With control circuit 320, transistor MP1, MP2, MP3 and MP4 are subject to respectively oppisite phase data input signal DB, data input signal D, the first clock signal CLK and the second clock signal CLK
binstitute controls, therefore as the first clock signal CLK and the second clock signal CLK
bbe all logic high, and in the time that data input signal D is also logic high, transistor MP1 conducting, and transistor MP2, MP3 and MP4 are all and open circuit.
Ask for an interview Fig. 3, in the time that transistor MP1 and MP5 are subject to respectively oppisite phase data input signal DB and first node Q1 to control open, Section Point Q2 can supply current potential V because of power supply
dDthe path forming to transistor MP1 and MP5 and be converted to logic high, then transistor MN3 is opened.Therefore, transistor MP1, MP5 and MN3 are conducting state, there is no direct current (direct current, DC) from power supply supply current potential V
dDflow to earthing potential V
sS.And the data input signal D of logic high is after hex inverter 380, the first switch element 365 and the 5th inverter 355, from the data output signal Q of the output output logic high level of the 5th inverter 355.
Because the transistor MP2 in control circuit 320 is closed condition, and the first node Q1 of logic low controls transistor MN2 and closes, the Section Point Q2 of logic high controls transistor MP6 and closes, therefore latch circuit 340 is without direct current path, do not produce charging current and cause electric current conflict, can be applicable to the system of low-work voltage.
Fig. 4 is the data output signal waveform schematic diagram in the time that data input signal is logic high.As shown in Figure 4, as the first clock signal CLK and the second clock signal CLK
bwhile being all logic high and data input signal D also for logic high, as explained above, data output signal Q exports from the output of the 5th inverter 355 of Fig. 3, is converted to logic high from logic low.
On the other hand, for convenience of description for the purpose of, referring to Fig. 3 and Fig. 5.As the first clock signal CLK and the second clock signal CLK
bbe all logic high, and in the time that data input signal D is logic low, the second switch element 370 meeting conductings in Fig. 3, the 3rd switch element 375 is subject to the oppisite phase data input signal DB of logic high to control also conducting.Due to 370 conductings of second switch element, the voltage level of Section Point Q2 is logic low, and the grid of transistor MP6 is subject to its control and conducting.
With control circuit 320, transistor MP1, MP2, MP3 and MP4 are subject to respectively oppisite phase data input signal DB, data input signal D, the first clock signal CLK and the second clock signal CLK
binstitute controls, therefore as the first clock signal CLK and the second clock signal CLK
bbe all logic high, and in the time that data input signal D is logic low, transistor MP2 conducting, and transistor MP1, MP3 and MP4 are all and open circuit.
Ask for an interview Fig. 3, in the time that transistor MP2 and MP6 are subject to respectively data input signal D and Section Point Q2 to control open, first node Q1 can supply current potential V because of power supply
dDthe path forming to transistor MP2 and MP6 and be converted to logic high, opens transistor MN2.Therefore, transistor MP2, MP6 and MN2 are conducting state, there is no direct current from power supply supply current potential V
dDflow to earthing potential V
sS.And now the voltage level of first node Q1 is logic high, therefore produce the data output signal Q of logic low after the 5th inverter 355 is anti-phase.
Because the transistor MP1 in control circuit 320 is closed condition, and the Section Point Q2 of logic low controls transistor MN3 and closes, the first node Q1 of logic high controls transistor MP5 and closes, therefore latch unit 340 is without direct current path, do not produce charging current and cause electric current conflict, can be applicable to the system of low-work voltage.
Fig. 5 is the data output signal waveform schematic diagram in the time that data input signal is logic low.As shown in Figure 5, as the first clock signal CLK and the second clock signal CLK
bwhen being all logic high and data input signal D and being logic low, as explained above, data output signal Q exports from the output of the 5th inverter 355 of Fig. 3, is converted to logic low from logic high.
In sum, the present invention discloses a kind of pulsed flip-flop, and it comprises pulse generator and latch unit.Pulse generator uses five transistors to realize, effectively reduce electronic circuit layout area and cost, and control circuit in latch unit coordinates the design of transfer circuit also to block direct current path, effectively reduce operand power and leakage current, and can be applicable to the system of low-work voltage.
Although the present invention discloses as above with execution mode; so it is not in order to limit the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (12)
1. a pulsed flip-flop, response one first clock signal and one second clock signal, breech lock one data input signal, so that this data input signal is converted to a data output signal, this pulsed flip-flop comprises:
One pulse generator, in order to receive this first clock signal and to produce this second clock signal, this pulse generator comprises:
One first inverter, in order to receive this first clock signal and to export this second clock signal;
One signal delay circuit, is electrically connected at this first inverter, in order to receive this second clock signal and to postpone this second clock signal; And
One latch unit, responds this first clock signal and this second clock signal, and in order to this data input signal of breech lock and export this data output signal, this latch unit comprises:
One transfer circuit, in order to transmit this data input signal;
One latch circuit, is electrically connected at this transfer circuit, in order to receive and this data input signal of breech lock, and exports this data output signal; And
One control circuit, is electrically connected at this latch circuit, in order to the Push And Release of this latch circuit of voltage control to be provided.
2. pulsed flip-flop as claimed in claim 1, is characterized in that, this signal delay circuit comprises:
One second inverter, is electrically connected at this first inverter, in order to receive this second clock signal; And
One first nmos pass transistor, the grid of this first nmos pass transistor is electrically connected at the output of this second inverter, in order to postpone this second clock signal with this second inverter acting in conjunction.
3. pulsed flip-flop as claimed in claim 2, is characterized in that, the phase place of this second clock signal is phase place anti-phase of this first clock signal.
4. pulsed flip-flop as claimed in claim 1, is characterized in that, this control circuit comprises:
One the one PMOS transistor, the transistorized grid of a PMOS is anti-phase in an oppisite phase data input signal of this data input signal in order to receive, and the transistorized source electrode of a PMOS is electrically connected at a power supply supply current potential;
One the 2nd PMOS transistor, the transistorized grid of the 2nd PMOS is in order to receive this data input signal, and the transistorized source electrode of the 2nd PMOS is electrically connected at this power supply supply current potential;
One the 3rd PMOS transistor, the transistorized grid of the 3rd PMOS is in order to receive this first clock signal, and the transistorized source electrode of the 3rd PMOS is electrically connected at the transistorized drain electrode of a PMOS or the transistorized drain electrode of the 2nd PMOS, the transistorized drain electrode of the 3rd PMOS is electrically connected at the transistorized drain electrode of the 2nd PMOS or the transistorized drain electrode of a PMOS; And
One the 4th PMOS transistor, the transistorized grid of the 4th PMOS is in order to receive this second clock signal, and the transistorized source electrode of the 4th PMOS is electrically connected at the transistorized source electrode of the 3rd PMOS, the transistorized drain electrode of the 4th PMOS is electrically connected at the transistorized drain electrode of the 3rd PMOS.
5. pulsed flip-flop as claimed in claim 4, is characterized in that, this latch circuit comprises:
One the 3rd inverter, the input of the 3rd inverter is electrically connected at a first node, and the output of the 3rd inverter is electrically connected at a Section Point; And
One the 4th inverter, the input of the 4th inverter is electrically connected at this Section Point, and the output of the 4th inverter is electrically connected at this first node.
6. pulsed flip-flop as claimed in claim 5, is characterized in that, the 3rd inverter comprises:
One the 5th PMOS transistor, is series at a PMOS transistor; And
One second nmos pass transistor, is series at the 5th PMOS transistor, and the grid of this second nmos pass transistor is electrically connected at the transistorized grid of the 5th PMOS, and the source electrode of this second nmos pass transistor is connected in an earthed voltage.
7. pulsed flip-flop as claimed in claim 6, is characterized in that, the 4th inverter comprises:
One the 6th PMOS transistor, is series at the 2nd PMOS transistor; And
One the 3rd nmos pass transistor, is series at the 6th PMOS transistor, and the grid of the 3rd nmos pass transistor is electrically connected at the transistorized grid of the 6th PMOS, and the source electrode of the 3rd nmos pass transistor is connected in this earthed voltage.
8. pulsed flip-flop as claimed in claim 7, is characterized in that, this latch circuit more comprises:
One the 5th inverter, the input of the 5th inverter is electrically connected at this first node, and the output of the 5th inverter is in order to export this data output signal.
9. pulsed flip-flop as claimed in claim 8, is characterized in that, this transfer circuit comprises:
One first switch element, is electrically connected at this first node, this first switch element in this first and this second clock signal open while being all logic high; And
One hex inverter, the input of this hex inverter is in order to receive this data input signal, and the output of this hex inverter is electrically connected at this first switch element.
10. pulsed flip-flop as claimed in claim 9, it is characterized in that, when this first and this second clock signal be all logic high, and in the time that this data input signal is also logic high, this the first switch element conducting, a PMOS transistor, the 5th PMOS transistor and the 3rd nmos pass transistor are also conducting state.
11. pulsed flip-flops as claimed in claim 8, is characterized in that, this transfer circuit more comprises:
One second switch element, is electrically connected at this Section Point, this second switch element in this first and this second clock signal open while being all logic high; And
One the 3rd switch element, is electrically coupled to this output and this earthed voltage of this second switch element, this hex inverter, and the 3rd switch element is opened in the time that this data input signal is logic low.
12. pulsed flip-flops as claimed in claim 11, it is characterized in that, when this first and this second clock signal be all logic high, and in the time that this data input signal is logic low, this second switch element and the 3rd switch element conducting, the 2nd PMOS transistor, the 6th PMOS transistor and this second nmos pass transistor are also conducting state.
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| CN201210507608.4A CN103856189B (en) | 2012-11-30 | 2012-11-30 | Pulsed flip-flop |
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| CN109412562A (en) * | 2017-08-15 | 2019-03-01 | 瑞昱半导体股份有限公司 | Clock buffer circuit and its method |
| CN110798198A (en) * | 2018-08-02 | 2020-02-14 | 崛智科技有限公司 | Data latch circuit and pulse signal generator thereof |
| TWI716624B (en) * | 2016-11-23 | 2021-01-21 | 南韓商三星電子股份有限公司 | Flip-flop |
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Cited By (5)
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| TWI716624B (en) * | 2016-11-23 | 2021-01-21 | 南韓商三星電子股份有限公司 | Flip-flop |
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| CN110798198B (en) * | 2018-08-02 | 2023-07-04 | 崛智科技有限公司 | Data latch circuit and pulse signal generator thereof |
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| CN103856189B (en) | 2016-11-09 |
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