CN105811922A - Low-power retention flip-flop - Google Patents
Low-power retention flip-flop Download PDFInfo
- Publication number
- CN105811922A CN105811922A CN201510967966.7A CN201510967966A CN105811922A CN 105811922 A CN105811922 A CN 105811922A CN 201510967966 A CN201510967966 A CN 201510967966A CN 105811922 A CN105811922 A CN 105811922A
- Authority
- CN
- China
- Prior art keywords
- trigger
- signal
- latch
- coupled
- phase inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The embodiment of the invention discloses a low-power retention flip-flop which comprises an input end and an output end. The flip-flop includes a clock generation circuit, a master latch circuit, and a salve latch circuit. A first clock signal and a second clock signal which is inverted to the first clock signal are genderated at a first mode. The master latch circuit performs a first latch operation on an input signal from the input terminal according to the first and second clock signals to generate a first latched signal at a first node at the first mode. The salve latch circuit performs a second latch operation on the first latched signal according to the first and second clock signals to generate a second latched signal at a second node at the first mode, wherein the second latched signal couples to the output end of the flip-flop, and the salve latch circuit comprises a first inverter which comprises an input end coupled to a first node and an output end coupled to the second node, a first open gate coupled between the second node and the third node, and a second inverter which comprises an input end coupled to the third node and an output end coupled to the input end of the first inverter.
Description
Technical field
The present invention relates to trigger, particularly relate to a kind of low-power consumption and keep trigger (retentionflip-flop).
Background technology
Traditional maintenance trigger when it is powered on running well, typically keeps the storage device of the data stored for a kind of.When maintenance trigger being converted to sleep or battery saving mode, remain in that these data stored.At this time, some elements in trigger or device is kept still to be powered on keeping data.But, due to the efficiency of (induced) leakage current sensed in these elements or device and reduction, so these elements or device will consume power.So, by using the less element being powered on or device in sleep or battery saving mode, it is possible to the low power dissipation design of the trigger that is maintained.
Summary of the invention
In view of this, embodiments provide a kind of low-power consumption and keep trigger, it is possible to keep data by less power.
The invention provides a kind of trigger, containing input and outfan, including:
Clock generation circuit, for when described trigger is when first mode, producing the first clock signal and the second clock signal anti-phase with described first clock signal；
Master latch circuit, for when described trigger is when described first mode, according to described first clock signal and described second clock signal, performing the first latch operation to the input signal from described input, to produce the first latch signal at primary nodal point；And
From latch circuit, it is coupled to described primary nodal point, for when described trigger is when described first mode, according to described first clock signal and described second clock signal, described first latch signal is performed the second latch operation, to produce the second latch signal at secondary nodal point；
Wherein, described second latch signal is coupled to the outfan of described trigger, and described includes from latch circuit:
First phase inverter, containing being coupled to the input of described primary nodal point and being coupled to the outfan of described secondary nodal point；
First open gate, is coupled between described secondary nodal point and the 3rd node；And
Second phase inverter, containing being coupled to the input of described 3rd node and being coupled to the outfan of input of described first phase inverter.
Wherein, when described trigger is when the second pattern, described clock generation circuit is powered on；And
When described trigger is when described second pattern, described from latch circuit, described second phase inverter and described first open gate are all powered on, and described first phase inverter is not powered on.
Wherein, described clock generation circuit, described second phase inverter and described first open gate all include: multiple transistors；When described trigger is when described second pattern, the quantity sum of the transistor being powered in described clock generation circuit, described second phase inverter and described first open gate is 8.
Wherein, when described trigger is when described first mode, described from latch circuit according to described first clock signal and described second clock signal, by described second phase inverter and described first open gate, described second latch signal is performed the 3rd latch operation, produce the 3rd latch signal with the input at described first phase inverter.
Wherein, when described trigger is when described first mode, described clock generation circuit receives supply voltage；And
When described trigger is when described first mode, described from latch circuit, described first phase inverter, described second phase inverter and described first open gate are all powered on.
Wherein, farther include:
Input interface circuit, for when described trigger is when described first mode, receives external signal from the described input of described trigger, and transmits described external signal to described master latch circuit, using as described input signal；
Second open gate, is coupled between described input interface circuit and described master latch circuit, for when described trigger is when described first mode, to described input signal inversion；Wherein, it is transferred into described master latch circuit by the described input signal that described second open gate is anti-phase；
Third pass gate, is coupled in described primary nodal point and described between latch circuit, for when described trigger is when described first mode, receiving described first latch signal and described first latch signal is anti-phase；Wherein, be transferred into by described first latch signal that described third pass gate is anti-phase described from latch circuit；And
4th open gate, is coupled to described secondary nodal point, for when described trigger is when described first mode, receiving described second latch signal and described second latch signal is anti-phase；Wherein, the outfan of described trigger it is transferred into by described second latch signal that described 4th open gate is anti-phase.
The invention provides a kind of trigger, containing input and outfan, including:
Clock generation circuit, for when described trigger is when first mode, producing the first clock signal and the second clock signal anti-phase with described first clock signal；
Master latch circuit, for when described trigger is when described first mode, according to described first clock signal and described second clock signal, performing the first latch operation to the input signal from described input, to produce the first latch signal at primary nodal point；And
From latch circuit, it is coupled to described primary nodal point, for when described trigger is when described first mode, according to described first clock signal and described second clock signal, described first latch signal is performed the second latch operation, to produce the second latch signal at secondary nodal point；
Wherein, described second latch signal is coupled to the outfan of described trigger, and described includes from latch circuit:
First phase inverter, containing being coupled to the input of described primary nodal point and being coupled to the outfan of described secondary nodal point；
Second phase inverter, containing being coupled to the input of described secondary nodal point and being coupled to the outfan of the 3rd node；
First open gate, is coupled between described 3rd node and the input of described first phase inverter；And
The first transistor, containing being coupled to the control end of described 3rd node, being coupled to the first end of the first supply voltage and be coupled to the second end of described secondary nodal point.
Wherein, when described trigger is when the second pattern, described from latch circuit, described second phase inverter and described the first transistor are all powered on, and described first phase inverter and described first open gate are not all powered on.
Wherein, described second phase inverter includes: multiple transistors, and when described trigger is when described second pattern, the described number of transistors not being powered on from latch circuit is 3.
Wherein, when described trigger is when described first mode, described clock generation circuit is powered on, and
When described trigger is when described first mode, described described first phase inverter from latch circuit, described second phase inverter, described first open gate and described the first transistor are all powered on.
Wherein, when described the first transistor is realized by P-type transistor, described first voltage source provides supply voltage；
Or, when described the first transistor is realized by N-type transistor, described first voltage source provides with reference to ground voltage.
Wherein, described farther include from latch circuit:
Transistor seconds, containing being coupled to controlling end, being coupled to the first end of the second voltage source and be coupled to second end of the second end of described the first transistor of described 3rd node.
Wherein, when described trigger is when the second pattern, described from latch circuit, described second phase inverter, described the first transistor and described transistor seconds are all powered on, and described first phase inverter and described first open gate are not all powered on.
Wherein, described second phase inverter includes: multiple transistors, and when described trigger is when described second pattern, the quantity of the described transistor being powered on from latch circuit is 4.
Wherein, when described trigger is when described second pattern, described from latch circuit by described second phase inverter to described second latch signal perform the 3rd latch operation.
Wherein, when described trigger is when described first mode, described clock generation circuit is powered on；And
When described trigger is when described first mode, described from latch circuit, described first phase inverter, described second phase inverter, described first open gate, described the first transistor and described transistor seconds are all powered on.
Wherein, described the first transistor is realized by P-type transistor, and described transistor seconds is realized by N-type transistor, and described first voltage source provides supply voltage, and described second voltage source provides with reference to ground voltage.
Wherein, farther include:
Input interface circuit, for when described trigger is when described first mode, receives external signal from the input of described trigger and transmits described external signal to described master latch circuit, using as described input signal；
Second open gate, is coupled between described input interface circuit and described master latch circuit, for when described trigger is when described first mode, to described input signal inversion；Wherein, it is transferred into described master latch circuit by the described input signal that described second open gate is anti-phase；
Third pass gate, is coupled in described primary nodal point and described between latch circuit, for when described trigger is when described first mode, receiving described first latch signal and described first latch signal is anti-phase；Wherein, be transferred into by described first latch signal that described third pass gate is anti-phase described from latch circuit；And
4th open gate, is coupled to described secondary nodal point, for when described trigger is when described first mode, receiving described second latch signal, and described second latch signal is anti-phase；Wherein, the outfan of described trigger it is transferred into by described second latch signal that described 4th open gate is anti-phase.
The embodiment of the present invention provides the benefit that:
The embodiment of the present invention, owing to it adopts phase inverter to add the structure of open gate from latch circuit, or adopts phase inverter to add the structure of open gate and transistor, therefore by from the improvement of latch circuit, it is possible to keep data with less power.
Accompanying drawing explanation
Fig. 1 illustrates the exemplary embodiments keeping trigger；
Fig. 2 illustrates another exemplary embodiments keeping trigger；
Fig. 3 illustrates another exemplary embodiments further keeping trigger；
Fig. 4 illustrates another exemplary embodiments keeping trigger；And
Fig. 5 illustrates the relation between the supply of power supply and the generation of clock signal.
Detailed description of the invention
In order to make technical problem solved by the invention, technical scheme and beneficial effect clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.
Some vocabulary is employed to censure specific assembly in the middle of present specification and claim.Those skilled in the art are it is to be appreciated that hardware manufacturer may call same assembly with different nouns.This specification and claims are not using the difference of title as distinguishing in the way of assembly, but using assembly difference functionally as the criterion distinguished." including ", " comprising " mentioned in the middle of description and claim in the whole text is an open term, therefore should be construed to " include (containing) but be not limited to ".It addition, " coupling " word in this case includes any directly and indirectly electrical connection.Therefore, if first device described in literary composition is coupled to the second device, then represents this first device and can directly be electrically connected to this second device, or be indirectly electrically connected to this second device through other device or connection means.
Fig. 1 illustrates the exemplary embodiments keeping trigger.As shown in Figure 1, keep trigger 1 to have at least one input and outfan OUT10, and include: input interface circuit 10, master latch circuit 11, from latch circuit 12, clock generation circuit 13 and 14 and open gate (passgate) 15～17.In the embodiment in figure 1, this maintenance trigger 1 has given exemplarily two input IN10 and IN11.Clock generation circuit 13 includes: two phase inverters 130 and 131 of coupled in series.Clock generation circuit 14 includes: phase inverter 140.Input interface circuit 10 includes: two phase inverters 100 and 101.The input of phase inverter 100 is coupled to input IN10, and its outfan is coupled to node N10.The input of phase inverter 101 is coupled to input IN11, and its outfan is coupled to node N10.The input of open gate 15 is coupled to node N10, and its outfan is coupled to node N11.Master latch circuit 11 includes: phase inverter 110 and 111.The input of phase inverter 110 is coupled to node N11, and its outfan is coupled to node N12.The input of phase inverter 111 is coupled to node N12, and its outfan is coupled to node N11.The input of open gate 16 is coupled to node N12, and its outfan is coupled to node N13.
Include from latch circuit 12: two phase inverters 120 and 121, and open gate 122.The input of phase inverter 120 is coupled to node N13, and its outfan is coupled to node N14.Open gate 122 is coupled between node N14 and node N15.The input of phase inverter 121 is coupled to node N15, and its outfan is coupled to node N13.The input of open gate 17 is coupled to node N14, and its outfan is coupled to outfan OUT10.
In the present embodiment, phase inverter 100,101 and 111 is tristate inverter (tri-stateinverter).Open gate 15 and 16 can be realized by tristate inverter.
In the present embodiment, maintenance trigger 1 can in different patterns, such as normal mode and AD HOC (sleep or battery saving mode).When keeping trigger 1 to be operated in normal mode, input interface circuit 10, master latch circuit 11, from latch circuit 12, clock generation circuit 13 and 14 and open gate 15～17 be all powered on (powered).Namely, at normal mode, to input interface circuit 10, master latch circuit 11, from latch circuit 12, clock generation circuit 13 and 14 and open gate 15～17 element (such as transistor) provide the supply voltage for enabling the member to operating and with reference to ground voltage.In following, the operating keeping trigger 1 will be described.
At normal mode, input IN10 receives external signal S10, and input IN11 receives another external signal S11 anti-phase with this external signal S10.Clock generation circuit 13 receives clock signal CK, and clock generation circuit 14 receives clock signal TE.In detail, phase inverter 130 receives clock signal CK and clock signal CK is anti-phase to produce clock signal CKB.Phase inverter 131 receives clock signal CKB and clock signal CKB is anti-phase to produce clock signal CKT.Phase inverter 140 receives clock signal TE and clock signal TE is anti-phase to produce clock signal TEB.
At normal mode, in input interface circuit 10, clock signal TE and the TEB from clock generation circuit 14 controls phase inverter 100 and 101 with operating.By the control of clock signal TE and TEB, phase inverter 100 and 101 is anti-phase to external signal S10 and S11 at different time, to produce input signal S13.When phase inverter 100 according to clock signal TE and TEB to external signal S10 anti-phase time, produce anti-phase external signal S10 at node N10 place using as input signal S13.When phase inverter 101 according to clock signal TE and TEB to external signal S11 anti-phase time, produce anti-phase external signal S11 at node N10 place using as input signal S13.The open gate 15 controlled by clock signal CKB and CKT is to inputting the input signal S13 to node N11 that signal S13 is anti-phase and has transmitted anti-phase.
At normal mode, in master latch circuit 11, clock signal CKB and CKT controls phase inverter 111 with operating.Master latch circuit 11 receives the input signal S13 anti-phase by open gate 15, and performs latch operation by this anti-phase input signal S13 of phase inverter 110 and 111 pairs, to produce latch signal S14 at node N12.Input signal (i.e. this latch signal S14) is carried out anti-phase by the open gate 16 that subject clock signal CKB and CKT controls, and the latch signal S14 having transmitted anti-phase to node N13.
At normal mode, from latch circuit 12, open gate 122 subject clock signal CKB and CKT controls.Receive by the anti-phase latch signal S14 of open gate 16 from latch circuit 12, and by phase inverter 120 and 121 and open gate 122 the latch signal S14 that this is anti-phase is carried out latch operation, to produce latch signal S15 at node N14 place.This latch signal S15 is carried out anti-phase by open gate 17, and the latch signal S15 having transmitted anti-phase to outfan OUT10 using as keep trigger 1 output signal Sout10。
When keeping trigger 1 to be switched to AD HOC, such as sleep or battery saving mode, keep some elements in trigger 1 not to be powered on, and keep some elements in trigger 1 to be still powered on, with the last latch signal S15 produced at node N14 place before being held in AD HOC.In following, the operating keeping trigger 1 will be described.
In AD HOC, input interface circuit 10, master latch circuit 11, clock generation circuit 14 and open gate 15～17 are not powered on operating.Namely, in AD HOC, do not provide the supply voltage for enabling element to operate and with reference to ground voltage to input interface circuit 10, master latch circuit 11, clock generation circuit 14 and open gate 15～17, and these circuit or device are inoperative in producing corresponding signal, such as latch signal and clock signal.Such as, in AD HOC, clock generation circuit 14 stops producing clock signal TEB, and master latch circuit 11 stops input signal S13 is performed latch operation.Phase inverter 120 from latch circuit 12 is also be not powered on.In AD HOC, clock generation circuit 13 and the phase inverter from latch circuit 12 121 and open gate 122 are powered on.It is, provide supply voltage and with reference to ground voltage to phase inverter 121, open gate 122 and clock generation circuit 13.Phase inverter 121 and open gate 122 is passed through for performing latch operation at the node N14 last latch signal S15 produced before AD HOC, to produce latch signal S16 at node N13, thus keeping latch signal S15 from latch circuit 12.After keeping trigger 1 to be converted to normal mode, latch signal S16 is then anti-phase by phase inverter 120 and open gate 17, to produce output signal S at the outfan OUT10 keeping triggerout10。
In the present embodiment, phase inverter 121 and open gate 122 from latch circuit 12 all can be realized by multiple transistors, and the phase inverter 130 and 131 in clock generation circuit 13 all can be realized by multiple transistors.The quantity summation of the transistor being powered in AD HOC, phase inverter 121, open gate 122 and clock generation circuit 13 is 8.
In the above-described embodiments, the structure of input interface circuit 10, master latch circuit 11 and clock generation circuit 13 and 14 can be typical structure.According to the needs in the design keeping trigger 1, it is determined that the structure of input interface circuit 10, master latch circuit 11 and clock generation circuit 13 and 14.
Fig. 2 illustrates another exemplary embodiments keeping trigger.As in figure 2 it is shown, keep trigger 2 to have at least one input and outfan OUT20, and include: input interface circuit 20, master latch circuit 21, from latch circuit 22, clock generation circuit 23 and 24 and open gate 25～27.In the embodiment of fig. 2, this maintenance trigger 2 has two given input IN20 and IN21 exemplarily.Clock generation circuit 23 includes: two phase inverters 230 and 231 of coupled in series.Clock generation circuit 24 includes: phase inverter 240.Input interface circuit 20 includes: two phase inverters 200 and 201.The input of phase inverter 200 is coupled to input IN20, and its outfan is coupled to node N20.The input of phase inverter 201 is coupled to input IN21, and its outfan is coupled to node N20.The input of open gate 25 is coupled to node N20, and its outfan is coupled to node N21.Master latch circuit 21 includes: phase inverter 210 and 211.The input of phase inverter 210 is coupled to node N21, and its outfan is coupled to node N22.The input of phase inverter 211 is coupled to node N22, and its outfan is coupled to node N21.The input of open gate 26 is coupled to node N22, and its outfan is coupled to node N23.
Include from latch circuit 22: two phase inverters 220 and 221, open gate 222 and P-type transistor 223.The input of phase inverter 220 is coupled to node N23, and its outfan is coupled to node N24.The input of phase inverter 221 is coupled to node N24, and its outfan is coupled to node N25.Open gate 222 is coupled between node N25 and N23.The grid (control end) of P-type transistor 223 is coupled to node N25, and its source electrode (the first end) is coupled to voltage source 28, and its drain electrode (the second end) is coupled to node N24.In the present embodiment, P-type transistor 223 is realized by PMOS (P-typemetaloxidesemiconductor, P-type mos) transistor.The input of open gate 27 is coupled to node N24, and its outfan is coupled to outfan OUT10.
In the present embodiment, phase inverter 200,201 and 211 is tristate inverter.Open gate 25 and 26 is realized by tristate inverter.
In the present embodiment, maintenance trigger 2 can in different patterns, such as normal mode and AD HOC (sleep or battery saving mode).When keeping trigger 2 to operate at normal mode, input interface circuit 20, master latch circuit 21, from latch circuit 22, clock generation circuit 23 and 24 and open gate 25～27 be all powered on.Namely, at normal mode, to input interface circuit 20, master latch circuit 21, from latch circuit 22, clock generation circuit 23 and 24, and the element (such as transistor) in open gate 25～27 is provided which the supply voltage for enabling element to operate and with reference to ground voltage.In following, the operating keeping trigger 2 will be described.
At normal mode, input IN20 receives external signal S20, and input IN21 receives another external signal S21 anti-phase with this external signal S20.Clock generation circuit 23 receives clock signal CK, and clock generation circuit 24 receives clock signal TE.In detail, phase inverter 230 receives clock signal CK and clock signal CK is anti-phase to produce clock signal CKB.Phase inverter 231 receives clock signal CKB and clock signal CKB is anti-phase to produce clock signal CKT.Phase inverter 240 receives clock signal TE and clock signal TE is anti-phase to produce clock signal TEB.
At normal mode, in input interface circuit 20, phase inverter 200 and 201 is subject to the control of clock signal TE and the TEB from clock generation circuit 24 with operating.By the control of clock signal TE and TEB, phase inverter 200 and 201 is anti-phase to external signal S20 and S21 at different time, to produce input signal S23.When phase inverter 200 according to clock signal TE and TEB to external signal S20 anti-phase time, produce anti-phase external signal S20 at node N20 place using as input signal S23.When phase inverter 201 according to clock signal TE and TEB to external signal S21 anti-phase time, produce anti-phase external signal S21 at node N20 place as input signal S23.The open gate 25 that subject clock signal CKB and CKT controls is to inputting the input signal S23 to node N21 that signal S23 is anti-phase and has transmitted anti-phase.
At normal mode, in master latch circuit 21, the control of phase inverter 211 subject clock signal CKB and CKT is with operating.Master latch circuit 21 receives the input signal S23 anti-phase by open gate 25, and performs latch operation by this anti-phase input signal S23 of phase inverter 210 and 211 pairs, to produce latch signal S24 at node N22.The latch signal S24 of input is carried out anti-phase by the open gate 26 that subject clock signal CKB and CKT controls, and the latch signal S24 having transmitted anti-phase to node N23.
At normal mode, supply voltage VDD is provided by voltage source 28.From latch circuit 22, open gate 222 subject clock signal CKB and CKT controls.Receive by the anti-phase latch signal S24 of open gate 26 from latch circuit 22, and by phase inverter 220 and 221, open gate 222 and P-type transistor 223, this latch signal S24 is performed latch operation, to produce latch signal S25 at node N24.Open gate 27 is anti-phase to latch signal S25, and the latch signal S25 having transmitted anti-phase to outfan OUT20 using as keep trigger 2 output signal Sout20。
When keeping trigger 2 to be converted to AD HOC, such as sleep or battery saving mode, keep some elements in trigger 2 not to be powered on, and keep some elements in trigger 2 to be still powered on, with before being held in AD HOC at the node N24 last latch signal S25 produced.In following, the operating keeping trigger 2 will be described.
In AD HOC, input interface circuit 20, master latch circuit 21, clock generation circuit 23 and 24 and open gate 25～27 be not powered on operating.Namely, in AD HOC, not to input interface circuit 20, master latch circuit 21, clock generation circuit 23 and 24 and open gate 25～27 provide the supply voltage for enabling element to operate and with reference to ground voltage, and these circuit or device are inoperative in producing corresponding signal, such as latch signal and clock signal.Such as, in AD HOC, clock generation circuit 23 stops producing clock signal CKB and CKT, and clock generation circuit 24 stops producing clock signal TEB, and master latch circuit 21 stops input signal S23 is performed latch operation.Phase inverter 220 and open gate 222 from latch circuit 22 are also be not powered on.In AD HOC, phase inverter 221 and P-type transistor 223 from latch circuit 22 are powered on.It is, provide supply voltage and with reference to ground voltage to phase inverter 221 and P-type transistor 223, for instance, the supply voltage VDD that voltage source 28 provides.Phase inverter 221 and P-type transistor 223 is passed through for performing latch operation at the node N24 last latch signal S25 produced before AD HOC from latch circuit 22, to produce latch signal S26 (noting: latch signal S26 is the latch operation performed by phase inverter 221 and P-type transistor 223 and the signal produced in AD HOC) at node N24, keep thus realizing data.After keeping trigger 2 to be converted to normal mode, open gate 27 is then anti-phase to latch signal S26, to produce output signal S at the outfan OUT20 place keeping trigger 2out20.In the present embodiment, due to P-type transistor 223 and supply voltage VDD, so maintain the latch signal S25 with opposing high voltage potentials level in AD HOC.In other words, maintained before AD HOC at the outfan OUT20 output signal S with relative low voltage level (" 0 ") produced at AD HOC, phase inverter 221 and P-type transistor 223out20。
In the embodiment of fig. 2, the phase inverter 221 from latch circuit 22 can be realized by multiple transistors.In AD HOC, the quantity of the transistor being powered on from latch circuit 22 is 3.
In the above-described embodiments, the structure of input interface circuit 20, master latch circuit 21 and clock generation circuit 23 and 24 can be typical structure.According to the needs in the design keeping trigger 2, it is determined that the structure of input interface circuit 20, master latch circuit 21 and clock generation circuit 23 and 24.
Fig. 3 illustrates another exemplary embodiments further keeping trigger.The difference keeping trigger 2 shown in trigger 3 and Fig. 2 that keeps shown in Fig. 3 is in that the structure from latch circuit 22 and operating.In the fig. 3 embodiment, farther include from latch circuit 22: replace the N-type transistor 323 of the P-type transistor 223 of Fig. 2.The grid (control end) of this N-type transistor 323 is coupled to node N25, and its source electrode (the first end) is coupled to voltage source 28, and its drain electrode (the second end) is coupled to node N24.In the present embodiment, N-type transistor 323 is realized by nmos pass transistor.
At normal mode, provide by voltage source 28 with reference to ground voltage (GND).Receive by the anti-phase latch signal S24 of open gate 26 from latch circuit 22, and by phase inverter 220 and 221, open gate 222 and N-type transistor 323, this latch signal S24 is performed latch operation, to produce latch signal S25 at node N24.Latch signal S25 is carried out anti-phase by open gate 27, and the latch signal S25 having transmitted anti-phase to outfan OUT20 using as keep trigger 3 output signal Sout。
In AD HOC, input interface circuit 20, master latch circuit 21, clock generation circuit 23 and 24 and open gate 25～27 be not powered on.Phase inverter 220 from latch circuit 22 and open gate 222 are also without being powered on.But, phase inverter 221 and N-type transistor 323 from latch circuit 22 are powered on.It is, provide supply voltage and with reference to ground voltage to phase inverter 221 and N-type transistor 323, for instance, the reference ground voltage (GND) that voltage source 28 provides.Passing through phase inverter 221 and N-type transistor 323 for performing latch operation at the node N24 last latch signal S25 produced before AD HOC from latch circuit 22, to produce latch signal S26 at node N24, keeping thus realizing data.After keeping trigger 3 to be converted to normal mode, open gate 27 is then anti-phase to produce output signal S at the outfan OUT20 keeping trigger 3 to latch signal S26out20.In the present embodiment, due to N-type transistor 323 with reference to ground voltage GND, so keep the latch signal S25 with relative low voltage level in AD HOC.In other words, the output signal S with opposing high voltage potentials level (" 1 ") produced at outfan OUT20 place before AD HOC, phase inverter 221 and N-type transistor 323 are held in AD HOCout20。
In the fig. 3 embodiment, the phase inverter 221 from latch circuit 22 can be realized by multiple transistors.In AD HOC, the quantity of the transistor being powered on from latch circuit 22 is 3.
Fig. 4 illustrates the schematic diagram of another exemplary embodiments keeping trigger.The difference between trigger 2 that keeps shown in trigger 4 and Fig. 2 that keeps shown in Fig. 4 is in that the structure from latch circuit 22 and operating.In the fig. 4 embodiment, farther include from latch circuit 22: N-type transistor 423.The grid (control end) of N-type transistor 423 is coupled to node N25, and its source electrode (the first end) is coupled to voltage source 40, and its drain electrode (the second end) is coupled to the drain electrode of P-type transistor 223.In the present embodiment, N-type transistor 423 is realized by nmos pass transistor.N-type transistor 423 and P-type transistor 223 form phase inverter 424.
At normal mode, supply voltage VDD is provided by voltage source 28, provides by voltage source 40 with reference to meeting piezoelectric voltage GND.Receive by the anti-phase latch signal S24 of open gate 26 from latch circuit 22, and by phase inverter 220,221 and 424, and latch signal S24 is performed latch operation by open gate 222, to produce latch signal S25 at node N24.Latch signal S25 is carried out anti-phase by open gate 27, and the latch signal S25 having transmitted anti-phase to outfan OUT20 using as keep trigger 4 output signal Sout20。
In AD HOC, input interface circuit 20, master latch circuit 21, clock generation circuit 23 and 24 and open gate 25～27 all do not power on.Phase inverter 220 from latch circuit 22 and open gate 222 are also without powering on.But, the phase inverter 221 and 424 from latch circuit 22 powers on.It is, provide supply voltage and with reference to ground voltage to phase inverter 221 and 424, for instance, the reference ground voltage GND that the supply voltage VDD of voltage source 28 offer and voltage source 40 provide.From latch circuit 22 by phase inverter 221 and 424 for performing latch operation at the node N24 last latch signal S25 produced before AD HOC, to produce latch signal S26 at node N24, keep thus realizing data.After keeping trigger 4 to be converted to normal mode, open gate 27 is then anti-phase to latch signal S26, to produce output signal S at the outfan OUT20 place keeping trigger 4out20。
In the fig. 4 embodiment, the phase inverter 221 and 424 from latch circuit 22 all can be realized by multiple transistors.In AD HOC, the quantity of the transistor being powered on from latch circuit 22 is 4.
Embodiment according to Fig. 2～4, clock generation circuit 23 and 24 is powered at normal mode, but clock generation circuit 23 and 24 is not powered in AD HOC.So, clock signal (such as CKB, CKT and TE) only activates after clock generation circuit 23 is powered on, namely after supply voltage offer to clock generation circuit 23 and 24.Fig. 5 illustrates the relation between the supply of power supply and the generation of clock signal.In Figure 5, labelling " 50 " represents the supply sequential of the power supply for clock generation circuit 23 or 24, it is, provide to the supply voltage of clock generation circuit 23 or 24 with reference to ground voltage.Labelling " 51 " represents the sequential of the generation of clock signal CKB/CKT or TEB.As it is shown in figure 5, for each in clock generation circuit 23 and 24, after clock comes across the supply of power supply.
According to above example, when keeping trigger to be in sleep or battery saving mode, the negligible amounts of the element (such as transistor) being powered on, thus reducing the power consumption kept for data.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all any amendment, equivalent replacement and improvement etc. made within the spirit and principles in the present invention, should be included within protection scope of the present invention.
Claims (18)
1. a trigger, containing input and outfan, it is characterised in that including:
Clock generation circuit, for when described trigger is when first mode, producing the first clock signal and the second clock signal anti-phase with described first clock signal；
Master latch circuit, for when described trigger is when described first mode, according to described first clock signal and described second clock signal, performing the first latch operation to the input signal from described input, to produce the first latch signal at primary nodal point；And
From latch circuit, it is coupled to described primary nodal point, for when described trigger is when described first mode, according to described first clock signal and described second clock signal, described first latch signal is performed the second latch operation, to produce the second latch signal at secondary nodal point；
Wherein, described second latch signal is coupled to the outfan of described trigger, and described includes from latch circuit:
First phase inverter, containing being coupled to the input of described primary nodal point and being coupled to the outfan of described secondary nodal point；
First open gate, is coupled between described secondary nodal point and the 3rd node；And
Second phase inverter, containing being coupled to the input of described 3rd node and being coupled to the outfan of input of described first phase inverter.
2. trigger as claimed in claim 1, it is characterised in that
When described trigger is when the second pattern, described clock generation circuit is powered on；And
When described trigger is when described second pattern, described from latch circuit, described second phase inverter and described first open gate are all powered on, and described first phase inverter is not powered on.
3. trigger as claimed in claim 2, it is characterised in that described clock generation circuit, described second phase inverter and described first open gate all include: multiple transistors；When described trigger is when described second pattern, the quantity sum of the transistor being powered in described clock generation circuit, described second phase inverter and described first open gate is 8.
4. trigger as claimed in claim 2, it is characterized in that, when described trigger is when described first mode, described from latch circuit according to described first clock signal and described second clock signal, by described second phase inverter and described first open gate, described second latch signal is performed the 3rd latch operation, produce the 3rd latch signal with the input at described first phase inverter.
5. trigger as claimed in claim 2, it is characterised in that
When described trigger is when described first mode, described clock generation circuit receives supply voltage；And
When described trigger is when described first mode, described from latch circuit, described first phase inverter, described second phase inverter and described first open gate are all powered on.
6. trigger as claimed in claim 1, it is characterised in that farther include:
Input interface circuit, for when described trigger is when described first mode, receives external signal from the described input of described trigger, and transmits described external signal to described master latch circuit, using as described input signal；
Second open gate, is coupled between described input interface circuit and described master latch circuit, for when described trigger is when described first mode, to described input signal inversion；Wherein, it is transferred into described master latch circuit by the described input signal that described second open gate is anti-phase；
Third pass gate, is coupled in described primary nodal point and described between latch circuit, for when described trigger is when described first mode, receiving described first latch signal and described first latch signal is anti-phase；Wherein, be transferred into by described first latch signal that described third pass gate is anti-phase described from latch circuit；And
4th open gate, is coupled to described secondary nodal point, for when described trigger is when described first mode, receiving described second latch signal and described second latch signal is anti-phase；Wherein, the outfan of described trigger it is transferred into by described second latch signal that described 4th open gate is anti-phase.
7. a trigger, containing input and outfan, it is characterised in that including:
Clock generation circuit, for when described trigger is when first mode, producing the first clock signal and the second clock signal anti-phase with described first clock signal；
Master latch circuit, for when described trigger is when described first mode, according to described first clock signal and described second clock signal, performing the first latch operation to the input signal from described input, to produce the first latch signal at primary nodal point；And
From latch circuit, it is coupled to described primary nodal point, for when described trigger is when described first mode, according to described first clock signal and described second clock signal, described first latch signal is performed the second latch operation, to produce the second latch signal at secondary nodal point；
Wherein, described second latch signal is coupled to the outfan of described trigger, and described includes from latch circuit:
First phase inverter, containing being coupled to the input of described primary nodal point and being coupled to the outfan of described secondary nodal point；
Second phase inverter, containing being coupled to the input of described secondary nodal point and being coupled to the outfan of the 3rd node；
First open gate, is coupled between described 3rd node and the input of described first phase inverter；And
The first transistor, containing being coupled to the control end of described 3rd node, being coupled to the first end of the first supply voltage and be coupled to the second end of described secondary nodal point.
8. trigger as claimed in claim 7, it is characterized in that, when described trigger is when the second pattern, described from latch circuit, described second phase inverter and described the first transistor are all powered on, and described first phase inverter and described first open gate are not all powered on.
9. trigger as claimed in claim 8, it is characterised in that described second phase inverter includes: multiple transistors, and when described trigger is when described second pattern, the described number of transistors not being powered on from latch circuit is 3.
10. trigger as claimed in claim 8, it is characterised in that
When described trigger is when described first mode, described clock generation circuit is powered on, and
When described trigger is when described first mode, described described first phase inverter from latch circuit, described second phase inverter, described first open gate and described the first transistor are all powered on.
11. trigger as claimed in claim 7, it is characterised in that when described the first transistor is realized by P-type transistor, described first voltage source provides supply voltage；
Or, when described the first transistor is realized by N-type transistor, described first voltage source provides with reference to ground voltage.
12. trigger as claimed in claim 7, it is characterised in that described farther include from latch circuit:
Transistor seconds, containing being coupled to controlling end, being coupled to the first end of the second voltage source and be coupled to second end of the second end of described the first transistor of described 3rd node.
13. trigger as claimed in claim 12, it is characterized in that, when described trigger is when the second pattern, described from latch circuit, described second phase inverter, described the first transistor and described transistor seconds are all powered on, and described first phase inverter and described first open gate are not all powered on.
14. trigger as claimed in claim 13, it is characterised in that described second phase inverter includes: multiple transistors, and when described trigger is when described second pattern, the quantity of the described transistor being powered on from latch circuit is 4.
15. the trigger as described in claim 8 or 13, it is characterised in that when described trigger is when described second pattern, described from latch circuit by described second phase inverter to described second latch signal perform the 3rd latch operation.
16. trigger as claimed in claim 13, it is characterised in that when described trigger is when described first mode, described clock generation circuit is powered on；And
When described trigger is when described first mode, described from latch circuit, described first phase inverter, described second phase inverter, described first open gate, described the first transistor and described transistor seconds are all powered on.
17. trigger as claimed in claim 12, it is characterised in that described the first transistor is realized by P-type transistor, and described transistor seconds is realized by N-type transistor, described first voltage source provides supply voltage, and described second voltage source provides with reference to ground voltage.
18. trigger as claimed in claim 7, it is characterised in that farther include:
Input interface circuit, for when described trigger is when described first mode, receives external signal from the input of described trigger and transmits described external signal to described master latch circuit, using as described input signal；
Second open gate, is coupled between described input interface circuit and described master latch circuit, for when described trigger is when described first mode, to described input signal inversion；Wherein, it is transferred into described master latch circuit by the described input signal that described second open gate is anti-phase；
Third pass gate, is coupled in described primary nodal point and described between latch circuit, for when described trigger is when described first mode, receiving described first latch signal and described first latch signal is anti-phase；Wherein, be transferred into by described first latch signal that described third pass gate is anti-phase described from latch circuit；And
4th open gate, is coupled to described secondary nodal point, for when described trigger is when described first mode, receiving described second latch signal, and described second latch signal is anti-phase；Wherein, the outfan of described trigger it is transferred into by described second latch signal that described 4th open gate is anti-phase.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562103729P | 2015-01-15 | 2015-01-15 | |
| US62/103,729 | 2015-01-15 | ||
| US14/922,192 US9825480B2 (en) | 2015-02-11 | 2015-10-25 | Apparatus for performing hybrid power control in an electronic device with aid of separated power output nodes for multi-purpose usage of boost |
| US14/922,192 | 2015-10-25 | ||
| US14/922,405 | 2015-10-26 | ||
| US14/922,405 US9948282B2 (en) | 2015-01-15 | 2015-10-26 | Low-power retention flip-flops |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105811922A true CN105811922A (en) | 2016-07-27 |
Family
ID=56465660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510967966.7A Pending CN105811922A (en) | 2015-01-15 | 2015-12-21 | Low-power retention flip-flop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105811922A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110289846A (en) * | 2019-06-27 | 2019-09-27 | 北京大学深圳研究生院 | A kind of trigger keeping function with data |
| CN110719088A (en) * | 2018-07-13 | 2020-01-21 | 瑞昱半导体股份有限公司 | Clock generating circuit and hybrid circuit |
| CN111213207A (en) * | 2017-10-13 | 2020-05-29 | 美光科技公司 | Apparatus and method for providing multi-phase clock signals |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7649393B2 (en) * | 2007-06-20 | 2010-01-19 | Kawasaki Microelectronics, Inc. | Semiconductor integrated circuit having active and sleep modes and non-retention flip-flop that is initialized when switching from sleep mode to active mode |
| US8274319B2 (en) * | 2009-08-06 | 2012-09-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102215033B (en) * | 2010-04-12 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Retention flip-flop |
-
2015
- 2015-12-21 CN CN201510967966.7A patent/CN105811922A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7649393B2 (en) * | 2007-06-20 | 2010-01-19 | Kawasaki Microelectronics, Inc. | Semiconductor integrated circuit having active and sleep modes and non-retention flip-flop that is initialized when switching from sleep mode to active mode |
| US8274319B2 (en) * | 2009-08-06 | 2012-09-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102215033B (en) * | 2010-04-12 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Retention flip-flop |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111213207A (en) * | 2017-10-13 | 2020-05-29 | 美光科技公司 | Apparatus and method for providing multi-phase clock signals |
| CN111213207B (en) * | 2017-10-13 | 2023-11-14 | 美光科技公司 | Apparatus and method for providing multiphase clock signals |
| CN110719088A (en) * | 2018-07-13 | 2020-01-21 | 瑞昱半导体股份有限公司 | Clock generating circuit and hybrid circuit |
| CN110719088B (en) * | 2018-07-13 | 2023-04-07 | 瑞昱半导体股份有限公司 | Clock generating circuit and hybrid circuit |
| CN110289846A (en) * | 2019-06-27 | 2019-09-27 | 北京大学深圳研究生院 | A kind of trigger keeping function with data |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7576582B2 (en) | Low-power clock gating circuit | |
| US7616041B2 (en) | Data retention in operational and sleep modes | |
| US8242826B2 (en) | Retention flip-flop | |
| US20100176892A1 (en) | Ultra Low Power Oscillator | |
| US9184733B2 (en) | Low power architectures | |
| CN106664078B (en) | Multi-threshold CMOS (complementary Metal oxide semiconductor) sequential circuit based on low-leakage shadow latch | |
| US7548103B2 (en) | Storage device having low power mode and methods thereof | |
| CN103684355A (en) | Clock gating latch, method of operation thereof and integrated circuit employing same | |
| TW200410493A (en) | MTCMOS flip-flop circuit capable of retaining data in sleep mode | |
| KR100487654B1 (en) | Low power flip-flop circuit | |
| EP3462274B1 (en) | Semiconductor devices for sensing voltages | |
| CN109154855B (en) | Unified retention trigger architecture and control | |
| CN105811922A (en) | Low-power retention flip-flop | |
| TW201421907A (en) | Pulse-based flip flop | |
| US8884669B2 (en) | Electronic device with power mode control buffers | |
| KR101165730B1 (en) | Data retention circuit | |
| JP5310794B2 (en) | Low leakage voltage detection circuit | |
| US9948282B2 (en) | Low-power retention flip-flops | |
| CN107731257B (en) | Data recovery circuit and device with data recovery function | |
| KR102676329B1 (en) | Level shifter, and semiconductor device including the same | |
| KR100463246B1 (en) | Low power signal transmission circuit | |
| JPH1197984A (en) | Latch circuit | |
| KR102499010B1 (en) | Power gating circuit for holding data in logic block | |
| Jang et al. | Energy‐efficient leakage‐based oscillator with stacked structure for nW harvesters | |
| KR20010005004A (en) | Low power and stable flip flop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20200228 |
|
| AD01 | Patent right deemed abandoned |