JPH1197984A - Latch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a latch circuit which uses no complicated external control signal, has a small circuit scale, and operates with a low voltage. SOLUTION: The feedback loop of a logic gate 2 having a power switch transistor 1 consists of a data holding circuit 6 having power switch transistors 8 and 10, an inverter 5 having a power switch transistor 4, and a transmission gate 7 and this latch circuit controls the transistors 1, 4, 8, and 10 and transmission gate 7 with external control signals SL and *SL; and the threshold voltages of the transistors constituting the logic gate 2 is set to less than those of the transistors 1, 4, 8, and 10 and inverters 5, 9, and 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
V) The present invention relates to a latch circuit operable below.

[0002]

2. Description of the Related Art MOS having two kinds of threshold voltages, high and low
FIG. 7 shows a conventional latch circuit composed of FETs (for example, Japanese Patent Application No. 5-268245). The logic circuit is a PMOS transistor 51 for a high threshold power switch.
And a logic gate 52 composed of low-threshold transistors, which are connected to each other via a pseudo power supply line 53. Further, a feedback loop of this logic circuit includes a CMOS inverter 54 composed of a low-threshold transistor and a transmission gate 5 composed of a low-threshold transistor, which are powered by a pseudo power supply line 53 whose voltage is VDDV.
5, the high-speed operation during operation and the low power consumption operation during sleep (standby) at the power supply voltage VDD of 1 V or less can be simultaneously performed.

Further, by connecting a transmission gate 56 composed of a high-threshold transistor and a data holding circuit 57 to the input side of the logic gate 52, data is held during standby. In particular, in the data holding circuit 57, by inserting a transmission gate 60 composed of a low threshold transistor between the CMOS inverters 58 and 59 composed of a high threshold transistor, data writing during standby can be facilitated. During operation, the data of the data holding circuit 57 does not fluctuate.

[0004]

However, in the latch circuit shown in FIG. 7, in addition to the control signal SL, complicated control signals B1 and B2 are required to control the transmission gates 55, 56 and 60. In addition, there is a problem in that six gates (12 elements) are required for data retention, and the circuit scale becomes large.

The present invention has been made in view of the above points, and an object of the present invention is to provide a latch circuit that can operate at a high speed and low power consumption at a voltage of 1 V or less and requires a complicated external control signal. And without increasing the number of elements.

[0006]

According to a first aspect of the present invention, a feedback loop of a logic gate having a first power switch transistor and a data holding circuit having a second power switch transistor are provided. An inverter having a third power switch transistor;
And a latch circuit comprising a transmission gate and controlling each of the power switch transistors and the transmission gate by an external control signal, wherein a threshold voltage of a transistor constituting the logic gate is controlled by the power The threshold voltages of the switching transistor, the transistor forming the data holding circuit, and the transistor forming the inverter were set lower than the threshold voltages. In a second aspect based on the first aspect, the data holding circuit is constituted by a pair of inverters each connected to the second power switch transistor, and an output of one inverter is connected to an input of the other inverter. Connecting, connecting a first transistor between the output of the one inverter and a low potential power supply, controlling the first transistor to conduct when the third power switch transistor is non-conductive, and The output of the other inverter is used as an input / output terminal of the data holding circuit. In a third aspect, in the first aspect,
The external control signal is configured to be input in the order of the first power switch transistor, the transmission gate, the second power switch transistor, and the third power switch transistor.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a diagram showing a configuration of a latch circuit according to a first embodiment of the present invention. In the present embodiment, a latch circuit is constituted by three types of MOS transistors having threshold voltages of high, medium and low. The logic circuit is a PMOS for a high threshold power switch applied by a VDD power supply.
A logic gate 2 composed of a transistor 1 (first power switch transistor) and a low-threshold transistor is connected to each other via a pseudo power supply line 3.

The feedback loop of the logic circuit includes a PMOS transistor 4 (third power switch transistor) for a high threshold power switch to which a power supply of VDD is applied and a C transistor comprising a middle threshold transistor.
It comprises a MOS inverter 5, a data holding circuit 6, and a transmission gate 7 composed of a middle threshold transistor.

The data holding circuit 6 includes a CMOS inverter 9 comprising a high threshold transistor having a high threshold power switch PMOS transistor 8 (second power switch transistor), and a high threshold power switch. And a CMOS inverter 11 composed of a high threshold transistor having a PMOS transistor 10 (second power switch transistor).

Next, the operation will be described. First, during operation (external control signal SL = Low level), power switch transistors 1 and 4 are turned on, inverter 5 and transmission gate 7 are activated, and input / output data of the logic circuit is held. . At this time, the data holding circuit 6 does not affect the feedback loop because the power switch transistors 8 and 10 are off.

Next, during standby (external control signal SL = High level), transistors 1 and 4 for power switch and transmission gate 7 are turned off, and transistors 8 and 10 for power switch are turned on.
Therefore, at this time, the data holding circuit 6 performs a latch operation, and holds the data of the feedback loop there. At this time, since the inverters 9 and 11 of the data holding circuit 6 are composed of high-threshold transistors and the transmission gate 7 and the inverter 5 are composed of middle-threshold transistors, the leakage current There is no fear of a sharp rise.

As described above, in the present embodiment, the data holding circuit 6 is provided in the feedback loop of the logic circuit.
Since data retention was directly controlled by the external control signal * SL (* represents inversion) by the power switch transistors 8 and 10, a data retention circuit was provided on the input side of the logic circuit, and complicated control was performed for the data retention. Unlike the conventional example,
No complicated control signals are required, and only 11 elements are required for data retention.

[Second Embodiment] FIG. 2 is a diagram showing a latch circuit according to a second embodiment. Here, in the data holding circuit 6, between the output side of the inverter 11 and the low-potential power supply (ground), the high threshold NMOS transistor 1 to which the inverted signal * SL of the control signal SL is applied to the gate.
2 (first transistor).

According to this circuit, during operation (control signal * S
(L = High level), the transistor 12 conducts, and the output side of the inverter 11 is fixed at the Low level, so that the output of the inverter 9 is completely in a high impedance state, and the data holding circuit 6 affects the feedback loop during operation. Can be reliably prevented. When the transistor 12 is not provided, when the input data of the inverter 11 goes low, the NM of the inverter 11
Since the OS transistor is non-conductive and the transistor is in operation, the transistor 10 is non-conductive, but any of them may be conductive for some reason, and the high impedance of the output of the inverter 9 may not be guaranteed. However, this problem is solved.

[Third Embodiment] FIG. 3 is a diagram showing a latch circuit according to a third embodiment. Here, the inverters 9A and 11A and the power switch transistors 8A and 10A of the data holding circuit 6 are constituted by transistors having a middle threshold voltage. As described above, by using the transistor having the middle threshold value, the operation can be performed even when the power supply voltage VDD becomes lower, and a decrease in an operation margin during standby can be suppressed.

[Fourth Embodiment] FIG. 4 is a diagram showing a latch circuit according to a fourth embodiment. Here, in the circuit shown in FIG. 3, the power switch transistor 4 of the inverter 5 is replaced with a transistor 4A having a middle threshold value, and the external control signals SL, SL ', * SL', S
L ”is changed from“ SL ”→“ SL ′, * SL ′ ”→“ SL ””
Are input (changed) in the order shown in FIG.

As described above, by providing a timing difference between the input of the control signal of each power switch transistor, it is possible to prevent a malfunction in writing data to the data holding circuit 6 and reading data from the data holding circuit 6. .

FIG. 5 shows the control signals SL ', * SL', *
FIG. 13 is a diagram showing a control signal generation circuit for generating SL ”.
The MOS transistor 21 has a voltage VDDV of the pseudo power supply line 3.
During operation (SL = Low level)
Is conducted. CMOS inverters 22 and 23 each composed of a middle threshold transistor whose operation / standby is controlled by the transistor 21 are connected to each other.
, A CMOS inverter 24 composed of a medium threshold transistor and a CMOS inverter 25 composed of a high threshold transistor are connected in succession.

As a result, the signal SL 'is output as a signal delayed by the two-stage inverters 22 and 23. The signal * SL 'is a three-stage inverter 22, 2 with respect to the signal SL.
Output as a signal delayed by 3, 24. Further, the signal * SL "is a four-stage inverter 2 with respect to the signal SL.
Output as a signal delayed by 2,23,24,25. Since the inverter 23 has a middle threshold value, when the transistor 21 is non-conductive (SL = High level), the output signal SL ′ becomes High level due to a leak current.

In this embodiment, in particular, since the first and second inverters 22 and 23 are controlled by the power switch transistor 21, the voltage VDDV of the pseudo power supply line 3 is particularly high.
Therefore, when switching from standby to operation, when the voltage VDDV of the pseudo power supply line 3 of the logic circuit rises slowly, data in the data holding circuit 6 is written from the input side of the logic circuit. A malfunction that is replaced can be prevented.

[Fifth Embodiment] FIG. 6 is a diagram showing a fifth embodiment. This allows the latch circuit of the present invention to
This is applied to an FF circuit. 31 is the master side, 32
Is a slave side, and 33 is a portion to which the latch circuit shown in FIG. 4 is applied as it is. Reference numerals 34 to 39 denote CMOS inverters using low threshold transistors, and reference numerals 40 to 43 denote transmission gates using low threshold transistors.

FIG. 6 shows a standby state (SL = High level).
Shows the case where the clock signal CK goes to the low level.
In this circuit, when the clock signal CK is at the low level,
Since the transmission gate 43 becomes conductive and data on the slave side is held, the latch circuit 33 of the present invention is provided on the slave side. In addition, a low-threshold transmission gate 43 operated by a clock is interposed between the transmission gate 7 having the middle threshold and the node 44 of the data holding circuit 6, so that only the low-threshold transistor is used. High-speed operation equivalent to that of the DFF circuit can be performed.

[0023]

As described above, according to the latch circuit of the present invention,
High-speed operation can be performed without using complicated external control signals, and the data holding circuit can be configured with a small number of gates, which suppresses an increase in area when configuring a circuit on a semiconductor substrate as compared with conventional circuits. can do.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a latch circuit according to a first embodiment.

FIG. 2 is a circuit diagram of a latch circuit according to a second embodiment.

FIG. 3 is a circuit diagram of a latch circuit according to a third embodiment.

FIG. 4 is a circuit diagram of a latch circuit according to a fourth embodiment.

FIG. 5 shows external control signals SL ′, * SL ′, and * S shown in FIG.
FIG. 14 is a generation circuit diagram for generating L ″.

6 is a circuit diagram of a DFF circuit to which the latch circuit shown in FIG. 4 is applied.

FIG. 7 is a circuit diagram of a conventional latch circuit.

[Explanation of symbols]

························· High-threshold power switch transistor 8A, 10A ··················· CMOS inverter 5, 9A, 11A, 22 to 25 ... medium threshold C
MOS inverters 12, 21, high-threshold transistors 7, medium-threshold transmission gates 2, low-threshold logic gates 3, pseudo power supply lines 6, etc. .Data holding circuit

Claims (3)

[Claims] 1. A feedback loop of a logic gate having a first power switch transistor includes a data holding circuit having a second power switch transistor, an inverter having a third power switch transistor, and a transmission gate. And a latch circuit for controlling each of the power switch transistors and the transmission gate with an external control signal, wherein a threshold voltage of a transistor forming the logic gate is set to each of the power switch transistors, A latch circuit, wherein a threshold voltage of a transistor forming a data holding circuit and a threshold voltage of a transistor forming the inverter are made lower. 2. The data holding circuit comprises a pair of inverters each having the second power switch transistor connected thereto, and the output of one of the inverters is connected to the input of the other inverter. Connecting a first transistor between the output of the inverter and the low potential power supply;
2. The transistor of claim 1, wherein the third power switch transistor is turned on when the third power switch transistor is off, and the output of the other inverter is used as an input / output terminal of the data holding circuit. Latch circuit. 3. The first power switch transistor, the transmission gate and the second power switch transistor, the third power switch transistor, and the third power switch transistor.
2. The latch circuit according to claim 1, wherein the input is performed at the timing of the power switch transistor.