CN108242921A - Latch and frequency divider - Google Patents

Abstract

Latch and frequency divider, latch include the first logic unit, the second logic unit, third logic unit, the 4th logic unit and control unit；First logic unit is identical with the second logical unit structure, third logic unit is identical with the 4th logical unit structure, and first logic unit and third logic unit be connected in series between reference power source and reference ground, the second logic unit and the 4th logic unit are connected in series between reference power source and reference ground；Control unit, suitable for first logic unit when the latch is in preset operating condition, is controlled to be disconnected with the current path where the third logic unit or the second logic unit with the current path where the 4th logic unit.Above-mentioned scheme can reduce power consumption of the latch of high speed two-divider circuit under static and dynamic operating condition.

Description

Latch and frequency divider

Technical field

The present invention relates to electronic circuit technology field, more particularly to a kind of latch and frequency divider.

Background technology

With the development of the communication technology, based on the high-speed frequency divider that razavi structures latch is realized, since it has speed The advantages of spending fast and broader bandwidth, is widely used.

The high-speed frequency divider circuit of two divided-frequency is made of two stage latch, and any of which latch is another latch Rear class unit.

But high speed two-divider of the prior art is whether under the conditions of quiescent operation or in dynamic duty item Under part, there is power consumption it is larger the problem of.

Invention content

What the embodiment of the present invention solved is the power consumption for the latch for how reducing high speed two-divider circuit.

To solve the above problems, an embodiment of the present invention provides a kind of latch, the latch includes the first logic list Member, the second logic unit, third logic unit, the 4th logic unit and control unit；First logic unit and described the Two logical unit structures are identical, and the third logic unit is identical with the 4th logical unit structure, and first logic unit And third logic unit is connected in series between reference power source and reference ground, second logic unit and the 4th logic Unit is connected in series between reference power source and reference ground；Described control unit, suitable for being in preset in the latch When under operating condition, first logic unit and the current path or the second logic where the third logic unit are controlled Current path where unit and the 4th logic unit disconnects.

Optionally, first logic unit includes the first PMOS tube；Second logic unit includes the second PMOS tube； The third logic unit includes the first NMOS tube and third NMOS tube；4th logic unit includes the second NMOS tube and the Four NMOS tubes；The grid end of first PMOS tube is coupled with clock signal input terminal, the source of first PMOS tube with it is described Reference power source couples, and drain terminal and the described control unit of first PMOS tube couple；The grid end of second PMOS tube and institute Input clock signal coupling is stated, source and the reference power source of second PMOS tube couple, the leakage of second PMOS tube End is coupled with described control unit；The drain terminal of first NMOS tube is coupled with inverting clock signal output terminal, and described first The grid end of NMOS tube is coupled with clock signal output terminal, and source and the reference ground of first NMOS tube couple；It is described The drain terminal of third NMOS tube is coupled with the inverting clock signal output terminal, and grid end and the prime clock of the third NMOS tube are believed The coupling of number output terminal, source and the reference ground of the third NMOS tube couple；The drain terminal of second NMOS tube and institute Clock signal output terminal coupling is stated, the grid end of second NMOS tube and the inverting clock signal output terminal couple, and described the The source of two NMOS tubes is coupled with the reference ground；The drain terminal of the third NMOS tube and the clock signal output terminal coupling It connects, grid end and the prime inverting clock signal output terminal of the third NMOS tube couple, the source of the third NMOS tube and institute State reference ground coupling.

Optionally, described control unit, the moment declined suitable for the input clock signal that is in the latch and The clock signal output terminal of the latch signal and inverting clock signal output terminal signal stabilization when, control described the One logic unit and the current path where the third logic unit or the second logic unit and the 4th logic unit place Current path disconnect.

Optionally, described control unit includes the first control subelement and the second control subelement；First control Unit, suitable in the signal stabilization of the signal of the clock signal output terminal and inverting clock signal output terminal, described in control First logic unit and the current path where third logic unit or the second logic unit and the electricity where the 4th logic unit Logical circulation road disconnects；The second control subelement, suitable for the moment declined in the input clock signal, control described first is patrolled Collect unit and the current path where third logic unit or the second logic unit and the current path where the 4th logic unit It disconnects.

Optionally, the first control subelement, suitable for the signal that export in the clock signal output terminal and it is described instead During the signal stabilization of clock signal output terminal output, first logic is controlled using the signal of the clock signal output terminal Current path where unit and third logic unit is disconnected or is controlled using the signal of the inverting clock signal output terminal Current path where second logic unit and the 4th logic unit disconnects.

Optionally, the second control subelement, suitable for the moment declined in the input clock signal, during using prime The clock signal of clock signal output end output controls first logic unit to break with the current path where third logic unit It opens or second logic unit and the 4th logic is controlled using the inverting clock signal of prime inversion clock output terminal output Current path where unit disconnects.

Optionally, the first control subelement includes third PMOS tube and the 4th PMOS tube；The third PMOS tube The drain terminal of source and first PMOS tube couples, and grid end and the clock signal output terminal of the third PMOS tube couple, The drain terminal of the third PMOS tube and the described second control subelement coupling；The source and described second of 4th PMOS tube The drain terminal coupling of PMOS tube, grid end and the inverting clock signal output terminal of the 4th PMOS tube couple, and the described 4th The drain terminal of PMOS tube and the described second control subelement coupling.

Optionally, the source of the third PMOS tube and the source of the 4th PMOS tube couple.

Optionally, the second control subelement includes the 5th PMOS tube and the 6th PMOS tube；5th PMOS tube Source and the described first control subelement coupling, grid end and the prime clock signal output terminal coupling of the 5th PMOS tube It connects, drain terminal and the inverting clock signal output terminal of the 5th PMOS tube couple；The source of 6th PMOS tube and institute The coupling of the first control subelement is stated, the grid end of the 6th PMOS tube is coupled with the prime inverting clock signal output terminal, institute The drain terminal and the clock signal output terminal for stating the 6th PMOS tube couple.

Optionally, the first control subelement includes the 7th PMOS tube and the 8th PMOS tube；7th PMOS tube Source is coupled with the reference power source, and grid end and the clock signal output terminal of the 7th PMOS tube couple, and the described 7th The drain terminal of PMOS tube and the source of first PMOS tube couple；The source of 8th PMOS tube and the reference power source coupling It connects, grid end and the inverting clock signal output terminal of the 8th PMOS tube couple, the drain terminal of the 8th PMOS tube and institute State the source coupling of the second PMOS tube.

Optionally, the second control subelement includes the 9th PMOS tube and the tenth PMOS tube；9th PMOS tube The drain terminal of source and the 7th PMOS tube couples, grid end and the prime clock signal output terminal coupling of the 9th PMOS tube It connects, drain terminal and the inverting clock signal output terminal of the 9th PMOS tube couple；The source of tenth PMOS tube and institute The drain terminal coupling of the 8th PMOS tube is stated, the grid end of the tenth PMOS tube is coupled with the prime inverting clock signal output terminal, The drain terminal of tenth PMOS tube is coupled with the clock signal output terminal.

Optionally, first logic unit includes the 5th NMOS tube, the second logic unit includes the 6th NMOS tube, third Logic unit includes the 11st PMOS tube and the 13rd PMOS tube, and the 4th logic unit includes the 12nd PMOS tube and the tenth Four PMOS tube；The source of 5th NMOS tube is coupled with the reference ground, when the grid end of the 5th NMOS tube and input Clock signal couples, and drain terminal and the described control unit of the 5th NMOS tube couple；The source of 6th NMOS tube with it is described Reference ground couples, and grid end and the input clock signal of the 6th NMOS tube couple, the drain terminal of the 6th NMOS tube It is coupled with described control unit；The source of 11st PMOS tube is coupled with the reference power source, the 11st PMOS tube Grid end and the clock signal output terminal couple, drain terminal and the inverting clock signal output terminal coupling of the 11st PMOS tube It connects；The source of 13rd PMOS tube is coupled with the reference power source, grid end and the prime clock of the 13rd PMOS tube Signal output end couples, and drain terminal and the inverting clock signal output terminal of the 13rd PMOS tube couple；12nd PMOS The source of pipe is coupled with the reference power source, grid end and the inverting clock signal output terminal coupling of the 12nd PMOS tube It connects, drain terminal and the clock signal output terminal of the 12nd PMOS tube couple；The source of 14th PMOS tube and institute Reference power source coupling is stated, the grid end of the 14th PMOS tube and the prime inverting clock signal output terminal couple, and described the The drain terminal of 14 PMOS tube is coupled with clock signal output terminal.

Optionally, described control unit, suitable for the moment risen in the input clock signal of the latch and in institute State the clock signal output terminal of latch signal and inverting clock signal output terminal signal stabilization when, control described first is patrolled Collect unit and the current path where the third logic unit or the second logic unit and the electricity where the 4th logic unit Logical circulation road disconnects.

Optionally, described control unit includes third control subelement and the 4th control subelement；Third control Unit, suitable in the signal stabilization of the signal of the clock signal output terminal and inverting clock signal output terminal, described in control First logic unit and the current path where third logic unit or the second logic unit and the electricity where the 4th logic unit Logical circulation road disconnects；The 4th control subelement, suitable for the moment risen in the input clock signal, control described first is patrolled Collect unit and the current path where third logic unit or the second logic unit and the current path where the 4th logic unit It disconnects.

Optionally, third control subelement, suitable for the signal that export in the clock signal output terminal and it is described instead During the signal stabilization of clock signal output terminal output, first logic is controlled using the signal of the clock signal output terminal Current path where unit and third logic unit is disconnected or is controlled using the signal of the inverting clock signal output terminal Current path where second logic unit and the 4th logic unit disconnects.

Optionally, the 4th control subelement, suitable for the moment risen in the input clock signal, during using prime The clock signal of clock signal output end output controls first logic unit to break with the current path where third logic unit It opens or second logic unit and the 4th logic is controlled using the inverting clock signal of prime inversion clock output terminal output Current path where unit disconnects.

Optionally, the third control subelement includes the 7th NMOS tube and the 8th NMOS tube；7th NMOS tube The drain terminal of source and the 5th NMOS tube couples, and grid end and the clock signal output terminal of the 7th NMOS tube couple, The drain terminal of 7th NMOS tube and the described 4th control subelement coupling；The source and the described 6th of 8th NMOS tube The drain terminal coupling of NMOS tube, grid end and the inverting clock signal output terminal of the 8th NMOS tube couple, and the described 8th The drain terminal of NMOS tube and the described 4th control subelement coupling.

Optionally, the source of the 7th NMOS tube and the drain terminal of the 8th NMOS tube couple.

Optionally, the 4th control subelement includes the 9th NMOS tube and the tenth NMOS tube；9th NMOS tube Source is coupled with third control son member, and grid end and the prime clock signal output terminal of the 9th NMOS tube couple, The drain terminal of 9th NMOS tube is coupled with the inverting clock signal output terminal；The source of tenth NMOS tube and described the Three control subelements couplings, the grid end of the tenth NMOS tube and the prime inverting clock signal output terminal couple, and described the The drain terminal of ten NMOS tubes is coupled with the clock signal output terminal.

Optionally, the third control subelement includes the 11st NMOS tube and the 12nd NMOS tube；Described 11st The source of NMOS tube is coupled with the reference ground, grid end and the clock signal output terminal coupling of the 11st NMOS tube It connects, the drain terminal of the 11st NMOS tube is coupled with the source of the 5th NMOS tube；The source of 12nd NMOS tube with The reference ground coupling, grid end and the inverting clock signal output terminal of the 12nd NMOS tube couple, and the described tenth The drain terminal of two NMOS tubes and the source of the 6th NMOS tube couple.

Optionally, the 4th control subelement includes the 13rd NMOS tube and the 14th NMOS tube；Described 13rd The source of NMOS tube and the drain terminal of the 5th NMOS tube couple, and grid end and the prime clock of the 13rd NMOS tube are believed The coupling of number output terminal, drain terminal and the inverting clock signal output terminal of the 13rd NMOS tube couple；Described 14th The source of NMOS tube and the drain terminal of the 6th NMOS tube couple, when the grid end of the 14th NMOS tube is with the prime reverse phase Clock signal output end couples, and drain terminal and the clock signal output terminal of the 14th NMOS tube couple.

The embodiment of the present invention additionally provides a kind of frequency divider, and the frequency divider includes two above-mentioned latch, wherein, institute It is defeated with the clock signal of another latch respectively to state the first input end of any latch and the second input terminal in two latch Outlet and the coupling of inverting clock signal output terminal.

Compared with prior art, technical scheme of the present invention has the following advantages that：

Above-mentioned scheme in the preset operating condition of latch, controls first in latch to patrol by control unit Collect unit and the current path where the third logic unit or the second logic unit and the electricity where the 4th logic unit Logical circulation road disconnects, thus the power consumption of latch can be reduced under the conditions of dynamic and quiescent operation, economizes on resources.

Further, it is the moment of input clock signal rising of 25% latch and the clock of output in duty ratio During signal stabilization, the first logic unit in latch and the electric current where the third logic unit are controlled by control unit Access or the second logic unit are disconnected with the current path where the 4th logic unit, thus can be in dynamic and quiescent operation Under the conditions of reduce latch power consumption, economize on resources.

Further, it is the moment of input clock signal rising of 75% latch and the clock of output in duty ratio During signal stabilization, the first logic unit in latch and the electric current where the third logic unit are controlled by control unit Access or the second logic unit are disconnected with the current path where the 4th logic unit, thus can be in dynamic and quiescent operation Under the conditions of reduce latch power consumption, economize on resources.

Description of the drawings

Fig. 1 is a kind of structure diagram of frequency divider；

Fig. 2 is the structure diagram for the latch that a kind of duty ratio in existing frequency divider is 25%；

Fig. 3 is the structure diagram for the latch that a kind of duty ratio in the embodiment of the present invention is 25%；

Fig. 4 is the structure diagram that a kind of duty ratio of the embodiment of the present invention is the control unit in 25% latch；

Fig. 5 is the structure diagram for the latch that another duty ratio in the embodiment of the present invention is 25%；

Fig. 6 is the structure diagram for the latch that another duty ratio in the embodiment of the present invention is 25%；

Fig. 7 is the structure diagram for the latch that another duty ratio in the embodiment of the present invention is 25%；

Fig. 8 is the structure diagram for the latch that a kind of duty ratio in frequency divider shown in FIG. 1 is 75%；

Fig. 9 is structural representation of a kind of duty ratio for the control unit in 75% latch in the embodiment of the present invention Figure；

Figure 10 is the structure diagram for the latch that another duty ratio in the embodiment of the present invention is 75%；

Figure 11 is the structure diagram for the latch that another duty ratio in the embodiment of the present invention is 75%；

Figure 12 is the structure diagram for the latch that another duty ratio in the embodiment of the present invention is 75%.

Specific embodiment

Shown in Figure 1, high speed two-divider of the prior art can include latch 101 and 102, wherein, lock Storage 101 and latch 102 rear class unit each other.The output signal frequency of high speed two-divider is the 1/2 of frequency input signal, It can realize the output of the orthogonal frequency division signal of 25% or 75% duty ratio.

Fig. 2 shows a kind of circuits for realizing the latch in the high speed two-divider of fractional frequency signal that duty ratio is 25% Structure diagram.It is shown in Figure 2.The latch include be coupled to reference power source VREF_1 and reference ground VREF_2 it Between the first logic unit 201 and the second logic unit 202.

When first logic unit 201 has the first clock signal input terminal CLK1, prime clock signal input terminal D and reverse phase Clock signal output end Qn, the second logic unit have second clock signal input part CLK2, prime inverting clock signal input terminal Dn and clock signal output terminal Q.

First logic unit 201 includes the first PMOS tube MP1, the first NMOS tube MN1 and third NMOS tube MN3.Second patrols It collects unit 202 and includes the second PMOS tube MP2, the second NMOS tube MN2 and the 4th NMOS tube MN4.Wherein：

The source of first PMOS tube MP1 and the second PMOS tube MP2 couple respectively with reference power source VREF_1, the first PMOS tube The grid end of MP1 and the second PMOS tube MP2 respectively with the first clock signal input terminal CLK1 and second clock signal input part CLK2 Coupling, the drain terminal of the first PMOS tube MP1 respectively with the first NMOS tube MN1 and the drain terminal and reverse phase of the third NMOS tube MN3 The grid end of clock signal output terminal Qn and the second NMOS tube MN2 couple, the drain terminal of the second PMOS tube MP2 respectively with the second NMOS tube The grid end coupling of the drain terminal and clock signal output terminal Q and the first NMOS tube MN1 of MN2 and the 4th NMOS tube MN4, first Source and ground wire the VREF_2 coupling of NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3 and the 4th NMOS tube MN4.

When the first clock signal input terminal CLK1 and second clock signal input part CLK2 are low level, the first PMOS tube MP1 and the second PMOS tube MP2 conductings, there are reference power source VREF_1 to inverting clock signal output terminal Qn and clock signal to export Hold the current path of Q.When to prime clock signal output terminal D and prime inverting clock signal output terminal Dn input differential signals When, for example, inputting low electricity to prime clock signal output terminal D input high levels, and to prime inverting clock signal output terminal Dn Usually, third NMOS tube MN3 and the 4th NMOS tube MN4 are respectively induced prime clock signal output terminal D and prime inversion clock The level difference value of signal output end Dn, it is defeated in clock signal respectively under the action of the first NMOS tube MN1 and the second NMOS tube MN2 Outlet Q and inverting clock signal output terminal Qn amplification outputs, it is ensured that clock signal output terminal Q/ inverting clock signal output terminals Qn Level respectively close to the level of reference power source VREF_1/ reference grounds VREF_2.

When to prime clock signal output terminal D input high levels, and input to prime inverting clock signal output terminal Dn low During level, third NMOS tube MN3 conductings, and the 4th NMOS tube MN4 ends, while causes the first NMOS tube MN1 conductings, second NMOS tube MN2 ends.At this point, there is the NMOS tube MN1/ thirds of the PMOS tube MP1 of reference power source VREF_1 → first → first There are DC powers for the DC channel namely latch of NMOS tube MN3 → reference ground VREF_2.

When the first clock signal input terminal CLK1 and second clock signal input part CLK2 are high level, i.e. VREF_3 When, the first PMOS tube MP1 and the second PMOS tube MP2 end, reference power source VREF_1 to clock signal output terminal Q and inversion clock Current path cut-off between signal output end Qn, the clock signal output terminal Q of latch and inverting clock signal output terminal Qn It is discharged respectively by third NMOS tube MN3 and the 4th NMOS tube MN4 so that clock signal output terminal Q and inverting clock signal are defeated Outlet Qn output clock signal level close to ground wire VREF_2 level.

And under dynamic condition when clock signal clk is high level, there is also reference power source VREF_1 to arrive for corresponding latch The current path of ground wire VREF_2 increases the dynamic power consumption of latch.

Therefore, in the prior art applied to the latch in high speed two-divider under the conditions of quiescent operation and dynamic duty Under the conditions of be respectively present quiescent dissipation and dynamic power consumption, seriously constrain the application of high speed two-divider.

To solve the above-mentioned problems in the prior art, technical solution used in the embodiment of the present invention passes through in latch During in static and dynamic condition, the first logic unit and the third logic unit in latch are controlled by control unit The current path at place or the second logic unit are disconnected with the current path where the 4th logic unit, thus can be in dynamic Power consumption with latch is reduced under the conditions of quiescent operation, economizes on resources.

It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

Fig. 3 shows a kind of structure diagram of latch of the embodiment of the present invention.Latch 300 as shown in Figure 3, including First logic unit 301, the second logic unit 302, third logic unit 303, the 4th logic unit 304 and control unit 305；

Wherein, the first logic unit 301 is identical with 302 structure of the second logic unit, and third logic unit 303 and the 4th is patrolled It is identical to collect 304 structure of unit.First logic unit 301 and third logic unit 303 be connected in series in reference power source VREF_1 and Between reference ground VREF_2；Second logic unit 302 and the 4th logic unit 304 be connected in series in reference power source VREF_1 and Between reference ground VREF_2.

Control unit 305 is coupled between the first logic unit 301 and third logic unit 303 and the second logic list Between 302 and the 4th logic unit 304 of member, suitable for the moment declined in the input clock signal of latch and in latch Clock signal output terminal signal and inverting clock signal output terminal signal stabilization when, the first logic unit 301 of control with Current path or the second logic unit 302 where third logic unit 303 lead to the electric current where the 4th logic unit 304 Road disconnects.

Fig. 4 shows a kind of structure diagram of control unit in the embodiment of the present invention.Control unit as shown in Figure 4 400, the first control subelement 401 and second can be included and control at least one of subelement 402, wherein：

First control subelement 401, suitable in the letter of the signal of clock signal output terminal and inverting clock signal output terminal When number stablizing, current path or the second logic unit where control the first logic unit and third logic unit are patrolled with the 4th Current path where collecting unit disconnects.In an embodiment of the present invention, the first control subelement 401, suitable in clock signal During the signal stabilization that the signal and inverting clock signal output terminal of output terminal output export, using the signal of clock signal output terminal Current path where controlling the first logic unit and third logic unit disconnects or using inverting clock signal output terminal Current path where signal controls the second logic unit and the 4th logic unit disconnects.

Second control subelement 402, suitable for the moment declined in input clock signal, controls the first logic unit and third Current path or the second logic unit where logic unit are disconnected with the current path where the 4th logic unit.In this hair In a bright embodiment, the second control subelement 402, suitable for the moment declined in input clock signal, using prime clock signal The clock signal of output terminal output controls the first logic unit to disconnect or use with the current path where third logic unit The inverting clock signal of prime inversion clock output terminal output controls the electric current where the second logic unit and the 4th logic unit Access disconnects.

Fig. 5 shows a kind of structure diagram of latch in the embodiment of the present invention.Latch as shown in Figure 5, can To include the first logic unit 501, the second logic unit 502, third logic unit 503, the 4th logic unit 504, Yi Ji One control subelement 505 and second controls subelement 504.

In specific implementation, the first logic unit 301 includes the first PMOS tube MP1, and the second logic unit includes second PMOS tube MP2, third logic unit 303 includes the first NMOS tube MN1 and third NMOS tube MN3, the 4th logic unit 504 include Second NMOS tube MN2 and the 4th NMOS tube MN4；First control subelement includes third PMOS tube MP3 and the 4th PMOS tube MP4； Second control subelement includes the 5th PMOS tube MP5 and the 6th PMOS tube MP6.

Wherein, the grid end of the first PMOS tube MP1 is coupled with input clock signal CLK, the source and ginseng of the first PMOS tube MP1 Power supply VREF_1 couplings are examined, the drain terminal of the first PMOS tube MP1 is coupled with the source of third PMOS tube MP3.

The grid end of third PMOS tube MP3 is coupled with clock signal output terminal Q, the drain terminal and the 5th of third PMOS tube MP3 The source coupling of PMOS tube MP5.

The grid end of 5th PMOS tube MP5 and the grid end of third NMOS tube MN3 couple, and with prime clock signal output terminal D Coupling, the coupling of the drain terminal of the drain terminal and third NMOS tube MN3 of the drain terminal of the 5th PMOS tube MP5 and the first NMOS tube MN1, and As inverting clock signal output terminal Qn.

The grid end of first NMOS tube MN1 is coupled with clock signal output terminal Q, the source and third of the first NMOS tube MN1 The source of NMOS tube MN3 is coupled with reference ground VREF_2.

The grid end of second PMOS tube MP2 is coupled with input clock signal CLK, source and the reference electricity of the second PMOS tube MP2 Source VREF_1 is coupled, and the drain terminal of the second PMOS tube MP2 and the source of the 4th PMOS tube MP4 couple.

The grid end of 4th PMOS tube MP4 is coupled with inverting clock signal output terminal Qn, the drain terminal of the 4th PMOS tube MP4 and the The source coupling of six PMOS tube MP6.

The grid end of 6th PMOS tube MP6 is coupled with the grid end of the 4th NMOS tube MN4, and is exported with prime inverting clock signal Hold Dn couplings, the coupling of the drain terminal of the drain terminal and the 4th NMOS tube MN4 of the drain terminal of the 6th PMOS tube MP6 and the second NMOS tube MN2 It connects, and as clock signal output terminal Q.

The grid end of second NMOS tube MN2 is coupled with inverting clock signal output terminal Qn, the source of the second NMOS tube MN2 and the The source of four NMOS tube MN4 is coupled with reference ground VREF_2.

The operation principle of latch shown in fig. 5 will be described in detail below.

Failing edge is in the input clock signal of clock signal input terminal CLK namely is converted into low level from high level Moment, the first PMOS tube MP1 and the second PMOS tube MP2 conducting.Meanwhile when prime clock signal output terminal D be low level, it is preceding Grade inverting clock signal output terminal Dn is high level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is low level, the 4th NMOS tube MN4 conductings.At the same time, the 6th PMOS tube MP6 is by so that Current path where two logic units and the 4th logic unit disconnects namely there is no from the second PMOS tube MP2 → 4 The current path of the NMOS tube MN4 of the PMOS tube MP6 of PMOS tube MP4 → the 6th → the 4th, can largely reduce latch Dynamic power consumption.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for high level, clock signal output terminal Q outputs Clock signal is the clock signal of low level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being low level, the 4th PMOS tube MP4 cut-offs, so that the second logic unit is led to the electric current where the 4th logic unit Road disconnects namely there is no from the NMOS tube MN4 of the PMOS tube MP6 of the PMOS tube MP4 of the second PMOS tube MP2 → the 4th → the 6th → the 4th Current path, can largely reduce the quiescent dissipation of latch.

Failing edge is in the input clock signal of clock signal input terminal CLK namely is converted into low level from high level Moment, the first PMOS tube MP1 and the second PMOS tube MP2 conducting.Meanwhile when prime clock signal output terminal D be high level, it is preceding Grade inverting clock signal output terminal Dn is low level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is low level, third NMOS tube MN3 conductings.At the same time, the 5th PMOS tube MP5 is by so that Current path where one logic unit and third logic unit disconnects namely there is no from the first PMOS tube MP1 → third The current path of the PMOS tube MP5 of PMOS tube MP3 → the 5th → third NMOS tube MN3, can largely reduce latch Dynamic power consumption.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for low level, clock signal output terminal Q outputs Clock signal is the clock signal of high level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being high level, third PMOS tube MP3 cut-offs, so that the first logic unit is led to the electric current where third logic unit Road disconnects namely there is no from the PMOS tube MP6 of the first PMOS tube MP2 → third PMOS tube MP4 → the 5th → third NMOS tube MN3 Current path, thus can largely reduce the quiescent dissipation of latch.

It follows that pass through third PMOS tube MP3 and the 4th PMOS tube MP4 and second in the first control subelement The 5th PMOS tube MP5 and the 6th PMOS tube MP6 in subelement are controlled, can respectively be controlled under static conditions and dynamic condition The corresponding access that system is located between reference power source VREF_1 and reference ground VREF_2 disconnects, therefore can reduce static state respectively Power consumption under condition and dynamic condition.

Fig. 6 shows a kind of structure diagram of latch in the embodiment of the present invention.Latch as shown in Figure 6, can To include the first logic unit 601, the second logic unit 602, third logic unit 603, the 4th logic unit 604, Yi Ji One control subelement 605 and second controls subelement 606.

Wherein, the first logic unit 601 includes the first PMOS tube MP1, and the second logic unit includes the second PMOS tube MP2, Third logic unit 603 includes the first NMOS tube MN1 and third NMOS tube MN3, and the 4th logic unit 604 includes the second NMOS tube MN2 and the 4th NMOS tube MN4；First control subelement 605 includes third PMOS tube MP3 and the 4th PMOS tube MP4；Second control Subelement 606 includes the 5th PMOS tube MP5 and the 6th PMOS tube MP6.

The grid end of first PMOS tube MP1 is coupled with input clock signal CLK, source and the reference electricity of the first PMOS tube MP1 Source VREF_1 is coupled, drain terminal and the source of third PMOS tube MP3 and the source of the 4th PMOS tube MP4 of the first PMOS tube MP1 Coupling.

The grid end of third PMOS tube MP3 is coupled with clock signal output terminal Q, the drain terminal and the 5th of third PMOS tube MP3 The source coupling of PMOS tube MP5.

The grid end of 5th PMOS tube MP5 and the grid end of third NMOS tube MN3 couple, and with prime clock signal output terminal D Coupling, the coupling of the drain terminal of the drain terminal and third NMOS tube MN3 of the drain terminal of the 5th PMOS tube MP5 and the first NMOS tube MN1, and As inverting clock signal output terminal Qn.

The grid end of first NMOS tube MN1 is coupled with clock signal output terminal Q, the source and third of the first NMOS tube MN1 The source of NMOS tube MN3 is coupled with reference ground VREF_2.

The grid end of second PMOS tube MP2 is coupled with input clock signal CLK, source and the reference electricity of the second PMOS tube MP2 Source VREF_1 is coupled, and the drain terminal of the second PMOS tube MP2 and the source of the 4th PMOS tube MP4 couple.

The grid end of 4th PMOS tube MP4 is coupled with inverting clock signal output terminal Qn, the drain terminal of the 4th PMOS tube MP4 and the The source coupling of six PMOS tube MP6.

The grid end of 6th PMOS tube MP6 is coupled with the grid end of the 4th NMOS tube MN4, and is exported with prime inverting clock signal Hold Dn couplings, the coupling of the drain terminal of the drain terminal and the 4th NMOS tube MN4 of the drain terminal of the 6th PMOS tube MP6 and the second NMOS tube MN2 It connects, and as clock signal output terminal Q.

The grid end of second NMOS tube MN2 is coupled with inverting clock signal output terminal Qn, the source of the second NMOS tube MN2 and the The source of four NMOS tube MN4 is coupled with reference ground VREF_2.

The operation principle of latch shown in fig. 6 will be described in detail below.

Failing edge is in the input clock signal of clock signal input terminal CLK namely is converted into low level from high level Moment, the first PMOS tube MP1 and the second PMOS tube MP2 conducting.Meanwhile when prime clock signal output terminal D be low level, it is preceding Grade inverting clock signal output terminal Dn is high level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is low level, the 4th NMOS tube MN4 conductings.At the same time, the 6th PMOS tube MP6 is by so that Current path where two logic units and the 4th logic unit disconnects namely there is no from the second PMOS tube MP2 → 4 The current path of the NMOS tube MN4 of the PMOS tube MP6 of PMOS tube MP4 → the 6th → the 4th, can largely reduce latch Dynamic power consumption.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for high level, clock signal output terminal Q outputs Clock signal is the clock signal of low level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being low level, the 4th PMOS tube MP4 cut-offs, so that the second logic unit is led to the electric current where the 4th logic unit Road disconnects namely there is no from the NMOS tube MN4 of the PMOS tube MP6 of the PMOS tube MP4 of the second PMOS tube MP2 → the 4th → the 6th → the 4th Current path, can largely reduce the quiescent dissipation of latch.

Failing edge is in the input clock signal of clock signal input terminal CLK namely is converted into low level from high level Moment, the first PMOS tube MP1 and the second PMOS tube MP2 conducting.Meanwhile when prime clock signal output terminal D be high level, it is preceding Grade inverting clock signal output terminal Dn is low level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is low level, third NMOS tube MN3 conductings.At the same time, the 5th PMOS tube MP5 is by so that Current path where one logic unit and third logic unit disconnects namely there is no from the first PMOS tube MP1 → third The current path of the PMOS tube MP5 of PMOS tube MP3 → the 5th → third NMOS tube MN3, can largely reduce latch Dynamic power consumption.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for low level, clock signal output terminal Q outputs Clock signal is the clock signal of high level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being high level, third PMOS tube MP3 cut-offs, so that the first logic unit is led to the electric current where third logic unit Road disconnects namely there is no from the PMOS tube MP6 of the first PMOS tube MP2 → third PMOS tube MP4 → the 5th → third NMOS tube MN3 Current path, can largely reduce the quiescent dissipation of latch.

It follows that pass through third PMOS tube MP3 and the 4th PMOS tube MP4 and second in the first control subelement The 5th PMOS tube MP5 and the 6th PMOS tube MP6 in subelement are controlled, can respectively be controlled under static conditions and dynamic condition The corresponding access that system is located between reference power source VREF_1 and reference ground VREF_2 disconnects, and can reduce static item respectively Power consumption under part and dynamic condition.

Fig. 7 shows the structure diagram of another latch in the embodiment of the present invention.Latch as shown in Figure 7, Can include the first logic unit 701, the second logic unit 702, third logic unit 703, the 4th logic unit 704 and First control subelement 705 and second controls subelement 706.

In specific implementation, the first logic unit 701 includes the first PMOS tube MP1, and the second logic unit 702 includes second PMOS tube MP2, third logic unit 703 includes the first NMOS tube MN1 and third NMOS tube MN3, the 4th logic unit 704 include Second NMOS tube MN2 and the 4th NMOS tube MN4；First control subelement 705 includes the 7th PMOS tube MP7 and the 8th PMOS tube MP8；Second control subelement 706 includes the 9th PMOS tube MP9 and the tenth PMOS tube MP10.

Wherein, the grid end of the first PMOS tube MP1 and input clock signal CLK are coupled, the source of the first PMOS tube MP1 and the The drain terminal coupling of seven PMOS tube MP7, the drain terminal of the first PMOS tube MP1 and the source of the 9th PMOS tube MP9 couple.

The grid end of 7th PMOS tube MP7 is coupled with clock signal output terminal Q, source and the reference electricity of the 7th PMOS tube MP7 Source VREF_1 is coupled；

The grid end of 9th PMOS tube MP9 is coupled with prime clock signal output terminal D, the drain terminal of the 9th PMOS tube MP9 with it is anti- Clock signal output terminal Dn is coupled.

The grid end of second PMOS tube MP2 is coupled with input clock signal CLK, the source and the 8th of the second PMOS tube MP2 The drain terminal coupling of PMOS tube MP8, the drain terminal of the second PMOS tube MP2 and the source of the tenth PMOS tube MP10 couple.

The source of 8th PMOS tube MP8 is coupled with reference power source VREF_1, the grid end and inversion clock of the 8th PMOS tube MP8 Signal output end Qn is coupled.

The grid end of tenth PMOS tube MP10 is coupled with prime inverting clock signal output terminal Dn, the leakage of the tenth PMOS tube MP10 End is coupled with clock signal output terminal Q.

The control process of quiescent dissipation and dynamic power consumption will be explained in detail in the latch described in Fig. 7 below：

Failing edge is in the input clock signal of clock signal input terminal CLK namely is converted into low level from high level Moment, the first PMOS tube MP1 and the second PMOS tube MP2 conducting.Meanwhile when prime clock signal output terminal D be low level, it is preceding Grade inverting clock signal output terminal Dn is high level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is low level, the 4th NMOS tube MN4 conductings, the tenth PMOS tube MP10 is by so that the second logic list Member disconnected with the current path where the 4th logic unit namely there is no from the PMOS tube MP2 of the 8th PMOS tube MP8 → second → The current path of the NMOS tube MN4 of tenth PMOS tube MP10 → the 4th, so as to largely reduce the dynamic of latch Power consumption.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for high level, clock signal output terminal Q outputs Clock signal is the clock signal of low level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being low level, the 8th PMOS tube MP8 cut-offs, so that the second logic unit is led to the electric current where the 4th logic unit Road disconnects namely the electricity from the NMOS tube MN4 of the PMOS tube MP10 of the PMOS tube MP2 of the 8th PMOS tube MP8 → second → the tenth → the 4th Logical circulation road can largely reduce the quiescent dissipation of latch.

Failing edge is in the input clock signal of clock signal input terminal CLK namely is converted into low level from high level Moment, the first PMOS tube MP1 and the second PMOS tube MP2 conducting.Meanwhile when prime clock signal output terminal D be high level, it is preceding Grade inverting clock signal output terminal Dn is low level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is low level, the first NMOS tube MN1 conductings, third NMOS tube MN3 is by so that the first logic unit It is disconnected with the current path where third logic unit namely there is no from PMOS tube MP1 → the of the 7th PMOS tube MP7 → first The current path of nine PMOS tube MP9 → third NMOS tube MN3 can largely reduce the dynamic power consumption of latch.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for low level, clock signal output terminal Q outputs Clock signal is the clock signal of high level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being high level, the 7th PMOS tube MP7 cut-offs, so that the first logic unit is led to the electric current where third logic unit Road disconnects namely there is no from the PMOS tube MP9 of the PMOS tube MP1 of the 7th PMOS tube MP7 → first → the 9th → third NMOS tube MN3 Current path, thus can largely reduce the quiescent dissipation of latch.

It follows that pass through the 7th PMOS tube MP7 and the 8th PMOS tube MP8 and second in the first control subelement The 9th PMOS tube MP9 and the tenth PMOS tube MP10 in subelement are controlled, can respectively be controlled under static conditions and dynamic condition The corresponding access that system is located between reference power source VREF_1 and reference ground VREF_2 disconnects, therefore can reduce static state respectively Power consumption under condition and dynamic condition.

It is above-mentioned that the structure of latch that duty ratio is 25% is described, it below will be to latch that duty ratio is 75% The structure of device is described in detail.

Fig. 8 shows the electrical block diagram that a kind of duty ratio of the prior art is 75% latch.Refer to Fig. 8 It is shown, it is described to latch 801 He of the first logic unit for including being coupled to VREF_2 between reference power source VREF_1 and reference ground Second logic unit 802.

When first logic unit 801 has the first clock signal input terminal CLK1, prime clock signal input terminal D and reverse phase Clock signal output end Qn, the second logic unit have second clock signal input part CLK2, prime inverting clock signal input terminal Dn and clock signal output terminal Q.

First logic unit 801 includes the 5th NMOS tube MN5, the 11st PMOS tube MP11 and the 13rd PMOS tube MP13. Second logic unit 802 includes the 6th NMOS tube MN6, the 12nd PMOS tube MP12 and the 14th PMOS tube MP14, wherein：

The source of 5th NMOS tube MN5 and the source of the 6th NMOS tube MN6 couple respectively with reference ground VREF_2, and the 5th The grid end of NMOS tube MN5 and the grid end of the 6th NMOS tube MN6 are believed respectively with the first clock signal input terminal CLK1 and second clock Number input terminal CLK2 coupling, the drain terminal of the 5th NMOS tube MN5 respectively with the 11st PMOS tube MP11 and the 13rd PMOS tube MP13 Drain terminal and the grid end of inverting clock signal output terminal Qn and the 12nd PMOS tube MP12 coupling, the leakage of the 6th NMOS tube MN6 End respectively with the 12nd PMOS tube MP12 and the drain terminal of the 14th PMOS tube MP14 and clock signal output terminal Q and the 11st The grid end coupling of PMOS tube MP11, the 11st PMOS tube MP11, the 12nd PMOS tube MP12, the 13rd PMOS tube MP13 and the tenth The source of four PMOS tube MP14 is coupled with reference power source VREF_1.

When the level signal that the first clock signal input terminal CLK1 and second clock signal input part CLK2 is inputted is height During level, the 5th NMOS tube MN5 and six NMOS tube MN6 conducting.At this point, when the electricity of prime clock signal input terminal D inputs Ordinary mail number be low level, and prime inverting clock signal input terminal Dn input level signal be high level when, the 13rd PMOS Pipe MP13 is connected, and the 14th PMOS tube MP14 ends, while causes the 11st PMOS tube MP11 conductings, the 12nd PMOS tube MP12 ends.At this point, there is from reference power source VREF_1 → the 13rd PMOS tube MP13 → five of the 11st PMOS tube MP11/ There is DC powers for the DC channel namely latch of metal-oxide-semiconductor MN5 → reference ground VREF_2.

When the level signal that the first clock signal input terminal CLK1 and second clock signal input part CLK2 is inputted is low During level, the 5th six NMOS tube MN6 cut-offs of NMOS tube MN5 and, the clock signal output terminal Q and inversion clock of latch inhale The rear output terminal Qn that receives is charged respectively by the 13rd PMOS tube MP13 and the 14th PMOS tube MP14 so that clock signal output terminal Q and inverting clock signal output terminal Qn exports the high level signal close to reference power source VREF_1.

When latch in a dynamic condition when, and the first clock signal input terminal CLK1 and second clock signal input part CLK2 input level signal from low transition be high level when, there is also from reference power source VREF_1 to reference ground for latch The current path of line VREF_2 namely the dynamic power consumption for increasing latch.

Therefore, in the prior art applied to the latch that duty ratio in high speed two-divider is 75% in quiescent operation condition Quiescent dissipation and dynamic power consumption are respectively present under lower and dynamic operating condition, seriously constrains the application of high speed two-divider.

To solve the above-mentioned problems in the prior art, technical solution used in the embodiment of the present invention passes through control unit The moment risen in the input clock signal of latch and the signal and inversion clock of clock signal output terminal in latch During the signal stabilization of signal output end, the first logic unit of control is patrolled with the current path where third logic unit or second Current path where collecting unit and the 4th logic unit disconnects, and can eliminate power consumption of the latch under the conditions of quiescent operation, And the dynamic power consumption under dynamic operating condition is reduced simultaneously.

Continue to participate in Fig. 3, the latch 300 of the embodiment of the present invention a kind of 75%, including the first logic unit 301, second Logic unit 302, third logic unit 303, the 4th logic unit 304 and control unit 305.

Wherein, the first logic unit 301 is identical with 302 structure of the second logic unit, and third logic unit 303 and the 4th is patrolled It is identical to collect 304 structure of unit.First logic unit 301 and third logic unit 303 be connected in series in reference power source VREF_1 and Between reference ground VREF_2；Second logic unit 302 and the 4th logic unit 304 be connected in series in reference power source VREF_1 and Between reference ground VREF_2.

Control unit 305 is coupled between the first logic unit 301 and third logic unit 303 and the second logic list Between 302 and the 4th logic unit 304 of member, and suitable for the moment risen in the input clock signal of latch and latching During the signal stabilization of the signal of the clock signal output terminal of device and inverting clock signal output terminal, the first logic unit 301 is controlled With the current path where third logic unit 303 or the electric current where the second logic unit 302 and the 4th logic unit 304 Access disconnects.

Fig. 9 shows a kind of structure diagram of control unit in the embodiment of the present invention.Control list as shown in Figure 9 Member 900 can include third control subelement 901 and the 4th and control at least one of subelement 902, wherein：

Third controls subelement 901, suitable in the letter of the signal of clock signal output terminal and inverting clock signal output terminal When number stablizing, current path or the second logic unit where control the first logic unit and third logic unit are patrolled with the 4th Current path where collecting unit disconnects.

In an embodiment of the present invention, third control subelement 901, suitable for the signal that is exported in clock signal output terminal and Inverting clock signal output terminal output signal stabilization when, using clock signal output terminal signal control the first logic unit and Current path where third logic unit disconnects or controls the second logic list using the signal of inverting clock signal output terminal Current path where member and the 4th logic unit disconnects.

4th control subelement 902, suitable for the moment risen in input clock signal, controls the first logic unit and third Current path or the second logic unit where logic unit are disconnected with the current path where the 4th logic unit.

In an embodiment of the present invention, the 4th control subelement 902, suitable for the moment risen in input clock signal, is adopted The clock signal exported with prime clock signal output terminal controls the first logic unit to lead to the electric current where third logic unit Road disconnects or controls the second logic unit and the 4th logic using the inverting clock signal of prime inversion clock output terminal output Current path where unit disconnects.

Figure 10 shows the structure diagram of another latch in the embodiment of the present invention.Latch as shown in Figure 10 Device can include the first logic unit 1001, the second logic unit 1002, third logic unit 1003, the 4th logic unit 1004 and third control subelement 1005 and the 4th control subelement 1004.

First logic unit 1001 includes the 5th NMOS tube MN5, the second logic unit 1002 includes the 6th NMOS tube MN6, Third logic unit 1003 includes the 11st PMOS tube MP11 and the 13rd PMOS tube MP13, and the 4th logic unit 1004 includes the 12 PMOS tube MP12 and the 14th PMOS tube MP14；Third control subelement 1005 includes the 7th NMOS tube MN7 and the 8th NMOS tube MN8；4th control subelement 1006 includes the 9th NMOS tube MN9 and the tenth NMOS tube MN10.

Wherein, the source of the 5th NMOS tube MN5 and reference ground VREF_2 are coupled, the grid end of the 5th NMOS tube MN5 and when Clock signal input part CLK is coupled, and the drain terminal of the 5th NMOS tube MN5 and the source of the 7th NMOS tube MN7 couple.

The grid end of 7th NMOS tube MN7 is coupled with clock signal output terminal Q, the drain terminal and the 9th of the 7th NMOS tube MN7 The source coupling of NMOS tube MN9.

The grid end of 9th NMOS tube MN9 is coupled with prime clock signal output terminal D, the drain terminal of the 9th NMOS tube MN9 with it is anti- Clock signal output terminal Qn is coupled.

The source of 11st PMOS tube MP11 is coupled with reference power source, the grid end and clock signal of the 11st PMOS tube MP11 Output terminal Q is coupled, and drain terminal and the inverting clock signal output terminal Qn of the 11st PMOS tube MP11 are coupled.

The grid end of 13rd PMOS tube MP13 is coupled with prime clock signal output terminal D, the source of the 13rd PMOS tube MP13 End is coupled with reference power source VREF_1, and drain terminal and the inverting clock signal output terminal Qn of the 13rd PMOS tube MP13 are coupled.

The source of 6th NMOS tube MN6 is coupled with reference ground VREF_2, the grid end and clock signal of the 6th NMOS tube MN6 Input terminal CLK is coupled, and the drain terminal of the 6th NMOS tube MN6 and the source of the 4th NMOS tube MN4 couple.

The grid end of 8th NMOS tube MN8 is coupled with inverting clock signal output terminal Qn, the drain terminal of the 8th NMOS tube MN8 and the The source coupling of six NMOS tube MN6.

The grid end of tenth NMOS tube MN10 is coupled with prime inverting clock signal output terminal Dn, the leakage of the tenth NMOS tube MN10 End is coupled with clock signal output terminal Q.

The source of 12nd PMOS tube MP12 is coupled with reference power source VREF_1, the grid end of the 12nd PMOS tube MP12 with it is anti- Clock signal output terminal Qn is coupled, and drain terminal and the clock signal output terminal Q of the 12nd PMOS tube MP12 are coupled.

The grid end of 14th PMOS tube MP14 is coupled with prime inverting clock signal output terminal Dn, the 14th PMOS tube MP14 Source and reference power source VREF_1 couple, drain terminal and the clock signal output terminal Q of the 14th PMOS tube MP14 are coupled.

Below by the latch described in Figure 10 how dynamic and static conditions under to the process that power consumption controls into Row is introduced.

Rising edge is in the input clock signal of clock signal input terminal CLK namely from low transition into high level Moment, the 5th NMOS tube MN5 and the 6th NMOS tube MN6 conducting.Meanwhile when prime clock signal output terminal D be low level, it is preceding Grade inverting clock signal output terminal Dn is high level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is high level, the 9th NMOS tube MN9 is by so that the first logic unit and third logic unit place Current path disconnect namely there is no from the NMOS tube MN9 of the 13rd PMOS tube MP13 of the 11st PMOS tube MP11/ → the 9th → The current path of the NMOS tube MN5 of 7th NMOS tube MN7 → the 5th can largely reduce the dynamic power consumption of latch.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for high level, clock signal output terminal Q outputs Clock signal is the clock signal of low level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being high level, third NMOS tube MN3 cut-offs, so that the first logic unit is led to the electric current where third logic unit Road disconnects namely there is no from the NMOS of the NMOS tube MN9 of the 13rd PMOS tube MP13 of the 11st PMOS tube MP11/ → the 9th → the 7th The current path of the NMOS tube MN5 of pipe MN7 → the 5th, thus can largely reduce the quiescent dissipation of latch.

Rising edge is in the input clock signal of clock signal input terminal CLK namely from low transition into high level Moment, the 5th NMOS tube MN5 and the 6th NMOS tube MN6 conducting.Meanwhile when prime clock signal output terminal D be high level, it is preceding Grade inverting clock signal output terminal Dn is low level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is high level, the tenth NMOS tube MN10 is by so that the second logic unit and the 4th logic unit institute Current path disconnect namely there is no from the NMOS tube of the 12nd PMOS tube MP12 of the 11st PMOS tube MP11/ → the tenth The current path of the NMOS tube MN6 of the NMOS tube MN8 of MN10 → the 8th → the 6th, so as to largely reduce latch Dynamic power consumption.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for low level, clock signal output terminal Q outputs Clock signal is the clock signal of high level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being high level, the 8th NMOS tube MN8 cut-offs, so that the second logic unit is led to the electric current where the 4th logic unit Road disconnects namely there is no from NMOS tube MN10 → 8th of the 12nd PMOS tube MP12 of the 11st PMOS tube MP11/ → the tenth The current path of the NMOS tube MN6 of NMOS tube MN8 → the 6th can largely reduce the quiescent dissipation of latch.

It follows that the 7th NMOS tube MN7 and the 8th NMOS tube MN8 and the 4th in subelement are controlled by third The 9th NMOS tube MN9 and the tenth NMOS tube MN10 in subelement are controlled, can respectively be controlled under static conditions and dynamic condition The corresponding access that system is located between reference power source VREF_1 and reference ground VREF_2 disconnects, therefore can reduce static state respectively Power consumption under condition and dynamic condition.

Figure 11 shows the structure diagram of another latch in the embodiment of the present invention.Latch as shown in figure 11 Device can include the first logic unit 1101, the second logic unit 1102, third logic unit 1103, the 4th logic unit 1104 and third control subelement 1105 and the 4th control subelement 1106.

First logic unit 1101 includes the 5th NMOS tube MN5, the second logic unit 1102 includes the 6th NMOS tube MN6, Third logic unit 1103 includes the 11st PMOS tube MP11 and the 13rd PMOS tube MP13, and the 4th logic unit 1104 includes the 12 PMOS tube MP12 and the 14th PMOS tube MP14；Third control subelement 1105 includes the 7th NMOS tube MN7 and the 8th NMOS tube MN8 the 4th controls subelement 1106 to include the 9th NMOS tube MN9 and the tenth NMOS tube MN10.

Wherein, the source of the 5th NMOS tube MN5 and reference ground VREF_2 are coupled, the grid end of the 5th NMOS tube MN5 and when Clock signal input part CLK is coupled, the drain terminal of the 5th NMOS tube MN5 and the source of the 7th NMOS tube MN7 and the 8th NMOS tube MN8's Source couples.

The grid end of 7th NMOS tube MN7 is coupled with clock signal output terminal Q, the drain terminal and the 9th of the 7th NMOS tube MN7 The source coupling of NMOS tube MN9.

The grid end of 9th NMOS tube MN9 is coupled with prime clock signal output terminal D, the drain terminal of the 9th NMOS tube MN9 with it is anti- Clock signal output terminal Qn is coupled.

The source of 11st PMOS tube MP11 is coupled with reference ground VREF_2, the grid end of the 11st PMOS tube MP11 and when Clock signal output end Q is coupled, and drain terminal and the inverting clock signal output terminal Qn of the 11st PMOS tube MP11 are coupled.

The grid end of 13rd PMOS tube MP13 is coupled with prime clock signal output terminal D, the source of the 13rd PMOS tube MP13 End is coupled with reference power source VREF_1, and drain terminal and the inverting clock signal output terminal Qn of the 13rd PMOS tube MP13 are coupled.

The source of 6th NMOS tube MN6 is coupled with reference ground VREF_2, the grid end and clock signal of the 6th NMOS tube MN6 Input terminal CLK is coupled, and the drain terminal of the 6th NMOS tube MN6 and the source of the 8th NMOS tube MN8 couple.

The grid end of 8th NMOS tube MN8 is coupled with inverting clock signal output terminal Qn, the drain terminal of the 8th NMOS tube MN8 and the The source coupling of ten NMOS tube MN10.

The grid end of tenth NMOS tube MN10 is coupled with prime inverting clock signal output terminal Dn, the leakage of the tenth NMOS tube MN10 End is coupled with clock signal output terminal Q.

The source of 12nd PMOS tube MP12 is coupled with reference power source VREF_1, the grid end of the 12nd PMOS tube MP12 with it is anti- Clock signal output terminal Qn is coupled, and drain terminal and the clock signal output terminal Q of the 12nd PMOS tube MP12 are coupled.

The grid end of 14th PMOS tube MP14 is coupled with prime inverting clock signal output terminal Dn, the 14th PMOS tube MP14 Source and reference power source VREF_1 couple, drain terminal and the clock signal output terminal Q of the 14th PMOS tube MP14 are coupled.

Latch described in Figure 11 is specific as follows for the control process of power consumption under dynamic and static state：

Rising edge is in the input clock signal of clock signal input terminal CLK namely from low transition into high level Moment, the 5th NMOS tube MN5 and the 6th NMOS tube MN6 conducting.Meanwhile when prime clock signal output terminal D be low level, it is preceding Grade inverting clock signal output terminal Dn is high level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is high level, the 9th NMOS tube MN9 is by so that the first logic unit and third logic unit place Current path disconnect namely there is no from the NMOS tube MN9 of the 13rd PMOS tube MP13 of the 11st PMOS tube MP11/ → the 9th → The current path of the NMOS tube MN5 of 7th NMOS tube MN7 → the 5th can largely reduce the dynamic power consumption of latch.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for high level, clock signal output terminal Q outputs Clock signal is the clock signal of low level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being high level, third NMOS tube MN3 cut-offs, so that the first logic unit is led to the electric current where third logic unit Road disconnects namely there is no from the NMOS of the NMOS tube MN9 of the 13rd PMOS tube MP13 of the 11st PMOS tube MP11/ → the 9th → the 7th The current path of the NMOS tube MN5 of pipe MN7 → the 5th, thus can largely reduce the quiescent dissipation of latch.

Rising edge is in the input clock signal of clock signal input terminal CLK namely from low transition into high level Moment, the 5th NMOS tube MN5 and the 6th NMOS tube MN6 conducting.Meanwhile when prime clock signal output terminal D be high level, it is preceding Grade inverting clock signal output terminal Dn is low level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is high level, the tenth NMOS tube MN10 is by so that the second logic unit and the 4th logic unit institute Current path disconnect namely there is no from the NMOS tube of the 12nd PMOS tube MP12 of the 11st PMOS tube MP11/ → the tenth The current path of the NMOS tube MN6 of the NMOS tube MN8 of MN10 → the 8th → the 6th, so as to largely reduce latch Dynamic power consumption.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for low level, clock signal output terminal Q outputs Clock signal is the clock signal of high level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being high level, the 8th NMOS tube MN8 cut-offs, so that the second logic unit is led to the electric current where the 4th logic unit Road disconnects namely there is no from NMOS tube MN10 → 8th of the 12nd PMOS tube MP12 of the 11st PMOS tube MP11/ → the tenth The current path of the NMOS tube MN6 of NMOS tube MN8 → the 6th can largely reduce the quiescent dissipation of latch.

It follows that by third control subelement 1105 in the 7th NMOS tube MN7 and the 8th NMOS tube MN8 and The 9th NMOS tube MN9 and the tenth NMOS tube MN10 in 4th control subelement 1106, can be in static conditions and dynamic condition Under, the corresponding access that control is located between reference power source VREF_1 and reference ground VREF_2 respectively disconnects, therefore can divide Power consumption that Jiang Di be under static conditions and dynamic condition.

Figure 12 shows the structure diagram of another latch in the embodiment of the present invention.Latch as shown in figure 12 Device can include the first logic unit 1201, the second logic unit 1202, third logic unit 1203, the 4th logic unit 1204 and third control subelement 1205 and the 4th control subelement 1206.

First logic unit 1201 includes the 5th NMOS tube MN5, and the second logic unit 1202 includes the 6th NMOS tube MN6, Third logic unit 1203 includes the 11st PMOS tube MP11 and the 13rd PMOS tube MP13, and the 4th logic unit 1204 includes the 12 PMOS tube MP12 and the 14th PMOS tube MP14；Third control subelement 1205 includes the 11st NMOS tube MN11 and the tenth Two NMOS tube MN12；4th control subelement 1206 includes the 13rd NMOS tube MN13 and the 14th NMOS tube MN14.

Wherein, the grid end of the 5th NMOS tube MN5 and clock signal input terminal CLK are coupled, the source of the 5th NMOS tube MN5 with The drain terminal coupling of 11st NMOS tube MN11, the drain terminal of the 5th NMOS tube MN5 and the source of the 13rd NMOS tube MN13 couple.

The grid end of 11st NMOS tube MN11 is coupled with clock signal output terminal Q, the source of the 11st NMOS tube MN11 with Reference ground VREF_2 is coupled.

The grid end of 13rd NMOS tube MN13 is coupled with prime clock signal output terminal D, the leakage of the 13rd NMOS tube MN13 End is coupled with inverting clock signal output terminal Qn.

The grid end of 11st PMOS tube MP11 is coupled with clock signal output terminal Q, the source of the 11st PMOS tube MP11 with Reference power source VREF_1 is coupled, and drain terminal and the inverting clock signal output terminal Qn of the 11st PMOS tube MP11 are coupled.

The grid end of 13rd PMOS tube MP13 is coupled with prime clock signal output terminal D, the source of the 13rd PMOS tube MP13 End is coupled with reference power source VREF_1, and drain terminal and the inverting clock signal output terminal Qn of the 13rd PMOS tube MP13 are coupled.

The grid end of 6th NMOS tube MN6 is coupled with clock signal input terminal CLK, the source and the 8th of the 6th NMOS tube MN6 The drain terminal coupling of NMOS tube MN8, the drain terminal of the 6th NMOS tube MN6 and the source of the 14th NMOS tube MN14 couple.

The grid end of 12nd NMOS tube MN12 is coupled with clock signal output terminal Q, the source of the 12nd NMOS tube MN12 with Reference ground VREF_2 is coupled.

The grid end of 14th NMOS tube MN14 is coupled with prime inverting clock signal output terminal Dn, the 14th NMOS tube MN14 Drain terminal and clock signal output terminal Q couple.

The grid end of 12nd PMOS tube MP12 is coupled with inverting clock signal output terminal Qn, the source of the 12nd PMOS tube MP12 End is coupled with reference power source VREF_1, and drain terminal and the clock signal output terminal Q of the 12nd PMOS tube MP12 are coupled.

The grid end of 14th PMOS tube MP14 is coupled with prime inverting clock signal output terminal Dn, the 14th PMOS tube MP14 Source and reference power source VREF_1 couple, drain terminal and the clock signal output terminal Q of the 14th PMOS tube MP14 are coupled.

In specific implementation, the dynamic of above-mentioned latch and quiescent dissipation control process are as follows：

Rising edge is in the input clock signal of clock signal input terminal CLK namely from low transition into high level Moment, the 5th NMOS tube MN5 and the 6th NMOS tube MN6 conducting.Meanwhile when prime clock signal output terminal D be low level, it is preceding Grade inverting clock signal output terminal Dn is high level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is high level, the 13rd NMOS tube MN13 is by so that the first logic unit and third logic unit The current path at place disconnects namely there is no from the NMOS of the 13rd PMOS tube MP13 of the 11st PMOS tube MP11/ → the 13rd The current path of the NMOS tube MN11 of the NMOS tube MN5 of pipe MN13 → the 5th → the 11st, can largely reduce latch Dynamic power consumption.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for high level, clock signal output terminal Q outputs Clock signal is the clock signal of low level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being high level, the 11st NMOS tube MN11 cut-offs, so that the first logic unit and the electricity where third logic unit Logical circulation road disconnects so that the current path where the first logic unit and third logic unit disconnect namely there is no from NMOS tube MN5 → 11st of the NMOS tube MN13 of the 13rd PMOS tube MP13 of 11st PMOS tube MP11/ → the 13rd → the 5th The current path of NMOS tube MN11, thus can largely reduce the quiescent dissipation of latch.

Rising edge is in the input clock signal of clock signal input terminal CLK namely from low transition into high level Moment, the 5th NMOS tube MN5 and the 6th NMOS tube MN6 conducting.Meanwhile when prime clock signal output terminal D be high level, it is preceding Grade inverting clock signal output terminal Dn is low level, and inverting clock signal output terminal Qn and clock signal output terminal Q outputs When clock signal is high level, the 14th NMOS tube MN14 is by so that the second logic unit and the 4th logic unit The current path at place disconnects namely there is no from the NMOS of the 14th PMOS tube MP14 of the 12nd PMOS tube MP12/ → the 14th The current path of the NMOS tube MN12 of the NMOS tube MN6 of pipe MN14 → the 6th → the 12nd, so as to largely reduce lock The dynamic power consumption of storage.

When the inverting clock signal of inverting clock signal output terminal Qn outputs and the clock letter of clock signal output terminal Q outputs When number stablizing, the inverting clock signal of inverting clock signal output terminal Qn outputs for low level, clock signal output terminal Q outputs Clock signal is the clock signal of high level, prime clock signal output terminal D and prime inverting clock signal output terminal Dn outputs When being high level, the 12nd NMOS tube MN12 cut-offs, so that the second logic unit and the electricity where the 4th logic unit Logical circulation road disconnect namely there is no from the NMOS tube MN14 of the 14th PMOS tube MP14 of the 12nd PMOS tube MP12/ → the 14th → The current path of the NMOS tube MN12 of 6th NMOS tube MN6 → the 12nd can largely reduce the static work(of latch Consumption.

It follows that the 11st NMOS tube MN11 and the 12nd NMOS tube MN12 in subelement are controlled by third, with And the 4th control subelement include the 13rd NMOS tube MN13 and the 14th NMOS tube MN14, can be in static conditions and dynamic item Under part, control respectively is located at corresponding access between reference power source VREF_1 and reference ground VREF_2 and disconnects, therefore can be with The power consumption under static conditions and dynamic condition is reduced respectively.

The embodiment of the present invention additionally provides a kind of frequency divider, and frequency divider includes at least two latch.Wherein, latch knot The scheme introduced in above-described embodiment may be used in structure, repeats no more.

The embodiment of the present invention is had been described in detail above, the present invention is not limited thereto.Any those skilled in the art, Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore protection scope of the present invention should be with Subject to claim limited range.

Claims (22)

1. a kind of latch, which is characterized in that patrolled including the first logic unit, the second logic unit, third logic unit, the 4th Collect unit and control unit；

First logic unit is identical with second logical unit structure, the third logic unit and the 4th logic unit Structure is identical, and first logic unit and third logic unit are connected in series between reference power source and reference ground, institute It states the second logic unit and the 4th logic unit is connected in series between reference power source and reference ground；

Described control unit, suitable for when the latch is under preset operating condition, controlling first logic unit With the current path where the third logic unit or the second logic unit and the current path where the 4th logic unit It disconnects.

2. latch according to claim 1, which is characterized in that first logic unit includes the first PMOS tube；Institute It states the second logic unit and includes the second PMOS tube；The third logic unit includes the first NMOS tube and third NMOS tube；It is described 4th logic unit includes the second NMOS tube and the 4th NMOS tube；

The grid end of first PMOS tube is coupled with clock signal input terminal, and the source of first PMOS tube is with described with reference to electricity Source couples, and drain terminal and the described control unit of first PMOS tube couple；

The grid end of second PMOS tube is coupled with the input clock signal, source and the reference of second PMOS tube Supply coupling, drain terminal and the described control unit of second PMOS tube couple；

The drain terminal of first NMOS tube is coupled with inverting clock signal output terminal, and grid end and the clock of first NMOS tube are believed The coupling of number output terminal, source and the reference ground of first NMOS tube couple；

The drain terminal of the third NMOS tube is coupled with the inverting clock signal output terminal, and the grid end of the third NMOS tube is with before Grade clock signal output terminal coupling, source and the reference ground of the third NMOS tube couple；

The drain terminal of second NMOS tube is coupled with the clock signal output terminal, the grid end of second NMOS tube with it is described anti- Clock signal output terminal couples, and source and the reference ground of second NMOS tube couple；

The drain terminal of the third NMOS tube is coupled with the clock signal output terminal, and the grid end and prime of the third NMOS tube are anti- Clock signal output terminal couples, and source and the reference ground of the third NMOS tube couple.

3. latch according to claim 2, which is characterized in that described control unit, suitable for being in the latch Moment for declining of input clock signal and clock signal output terminal in the latch signal and inverting clock signal During the signal stabilization of output terminal, first logic unit and the current path where the third logic unit or the are controlled Two logic units are disconnected with the current path where the 4th logic unit.

4. latch according to claim 3, which is characterized in that described control unit includes the first control subelement and the Two control subelements；

The first control subelement, suitable in the letter of the signal of the clock signal output terminal and inverting clock signal output terminal When number stablizing, first logic unit and the current path where third logic unit or the second logic unit and the are controlled Current path where four logic units disconnects；

The second control subelement, suitable for the moment declined in the input clock signal, controls first logic unit It is disconnected with the current path where third logic unit or the second logic unit with the current path where the 4th logic unit.

5. latch according to claim 4, which is characterized in that the first control subelement, suitable in the clock During the signal stabilization that the signal and the inverting clock signal output terminal of signal output end output export, using the clock signal Described in current path where signal control first logic unit and third logic unit of output terminal is disconnected or is used Current path where the signal of inverting clock signal output terminal controls second logic unit and the 4th logic unit disconnects.

6. latch according to claim 5, which is characterized in that the second control subelement, suitable in the input The moment that clock signal declines, using the clock signal of prime clock signal output terminal output control first logic unit with Current path where third logic unit disconnects or the inverting clock signal control using the output of prime inversion clock output terminal Current path where making second logic unit and the 4th logic unit disconnects.

7. latch according to claim 6, which is characterized in that it is described first control subelement include third PMOS tube and 4th PMOS tube；

The drain terminal of the source of the third PMOS tube and first PMOS tube couples, the grid end of the third PMOS tube with it is described Clock signal output terminal couples, the drain terminal of the third PMOS tube and the described second control subelement coupling；

The source of 4th PMOS tube and the drain terminal of second PMOS tube couple, the grid end of the 4th PMOS tube with it is described Inverting clock signal output terminal couples, the drain terminal of the 4th PMOS tube and the described second control subelement coupling.

8. latch according to claim 7, which is characterized in that the source of the third PMOS tube and the 4th PMOS The source coupling of pipe.

9. latch according to claim 7 or 8, which is characterized in that the second control subelement includes the 5th PMOS Pipe and the 6th PMOS tube；

The source of 5th PMOS tube with described first control subelement coupling, the grid end of the 5th PMOS tube with it is described before Grade clock signal output terminal coupling, drain terminal and the inverting clock signal output terminal of the 5th PMOS tube couple；

The source of 6th PMOS tube with described first control subelement coupling, the grid end of the 6th PMOS tube with it is described before The output terminal coupling of grade inverting clock signal, drain terminal and the clock signal output terminal of the 6th PMOS tube couple.

10. latch according to claim 6, which is characterized in that the first control subelement includes the 7th PMOS tube With the 8th PMOS tube；

The source of 7th PMOS tube is coupled with the reference power source, grid end and the clock signal of the 7th PMOS tube Output terminal couples, and the drain terminal of the 7th PMOS tube is coupled with the source of first PMOS tube；

The source of 8th PMOS tube is coupled with the reference power source, grid end and the inversion clock of the 8th PMOS tube Signal output end couples, and the drain terminal of the 8th PMOS tube is coupled with the source of second PMOS tube.

11. latch according to claim 10, which is characterized in that the second control subelement includes the 9th PMOS tube With the tenth PMOS tube；

The source of 9th PMOS tube and the drain terminal of the 7th PMOS tube couple, the grid end of the 9th PMOS tube with it is described Prime clock signal output terminal couples, and drain terminal and the inverting clock signal output terminal of the 9th PMOS tube couple；

The source of tenth PMOS tube and the drain terminal of the 8th PMOS tube couple, the grid end of the tenth PMOS tube with it is described Prime inverting clock signal output terminal couples, and drain terminal and the clock signal output terminal of the tenth PMOS tube couple.

12. latch according to claim 1, which is characterized in that first logic unit includes the 5th NMOS tube, the Two logic units include the 6th NMOS tube, third logic unit include the 11st PMOS tube and the 13rd PMOS tube, the described 4th Logic unit includes the 12nd PMOS tube and the 14th PMOS tube；

The source of 5th NMOS tube is coupled with the reference ground, the grid end and input clock signal of the 5th NMOS tube Coupling, drain terminal and the described control unit of the 5th NMOS tube couple；

The source of 6th NMOS tube is coupled with the reference ground, grid end and the input clock of the 6th NMOS tube Signal couples, and drain terminal and the described control unit of the 6th NMOS tube couple；

The source of 11st PMOS tube is coupled with the reference power source, grid end and the clock of the 11st PMOS tube Signal output end couples, and drain terminal and the inverting clock signal output terminal of the 11st PMOS tube couple；

The source of 13rd PMOS tube is coupled with the reference power source, grid end and the prime clock of the 13rd PMOS tube Signal output end couples, and drain terminal and the inverting clock signal output terminal of the 13rd PMOS tube couple；

The source of 12nd PMOS tube is coupled with the reference power source, grid end and the reverse phase of the 12nd PMOS tube Clock signal output terminal couples, and drain terminal and the clock signal output terminal of the 12nd PMOS tube couple；

The source of 14th PMOS tube is coupled with the reference power source, grid end and the prime of the 14th PMOS tube Inverting clock signal output terminal couples, and drain terminal and the clock signal output terminal of the 14th PMOS tube couple.

13. latch according to claim 12, which is characterized in that described control unit, suitable in the latch Input clock signal rise moment and the latch clock signal output terminal signal and inverting clock signal it is defeated During the signal stabilization of outlet, first logic unit and the current path or second where the third logic unit are controlled Logic unit is disconnected with the current path where the 4th logic unit.

14. latch according to claim 13, which is characterized in that described control unit include third control subelement and 4th control subelement；

The third controls subelement, suitable in the letter of the signal of the clock signal output terminal and inverting clock signal output terminal When number stablizing, first logic unit and the current path where third logic unit or the second logic unit and the are controlled Current path where four logic units disconnects；

The 4th control subelement, suitable for the moment risen in the input clock signal, controls first logic unit It is disconnected with the current path where third logic unit or the second logic unit with the current path where the 4th logic unit.

15. latch according to claim 14, which is characterized in that the third controls subelement, suitable for when described During the signal stabilization that the signal and the inverting clock signal output terminal of clock signal output end output export, believed using the clock Current path where the signal of number output terminal controls first logic unit and third logic unit disconnects or using institute Current path where stating signal control second logic unit and the 4th logic unit of inverting clock signal output terminal breaks It opens.

16. latch according to claim 15, which is characterized in that the 4th control subelement, suitable for described defeated Enter the moment of clock signal rising, first logic unit is controlled using the clock signal of prime clock signal output terminal output The inverting clock signal for disconnecting with the current path where third logic unit or being exported using prime inversion clock output terminal Current path where controlling second logic unit and the 4th logic unit disconnects.

17. latch according to claim 16, which is characterized in that the third control subelement includes the 7th NMOS tube With the 8th NMOS tube；

The source of 7th NMOS tube and the drain terminal of the 5th NMOS tube couple, the grid end of the 7th NMOS tube with it is described Clock signal output terminal couples, the drain terminal of the 7th NMOS tube and the described 4th control subelement coupling；

The source of 8th NMOS tube and the drain terminal of the 6th NMOS tube couple, the grid end of the 8th NMOS tube with it is described Inverting clock signal output terminal couples, the drain terminal of the 8th NMOS tube and the described 4th control subelement coupling.

18. latch according to claim 17, which is characterized in that the source and the described 8th of the 7th NMOS tube The drain terminal coupling of NMOS tube.

19. the latch according to claim 17 or 18, which is characterized in that the 4th control subelement includes the 9th NMOS tube and the tenth NMOS tube；

The source of 9th NMOS tube is coupled with third control son member, grid end and the prime of the 9th NMOS tube Clock signal output terminal couples, and drain terminal and the inverting clock signal output terminal of the 9th NMOS tube couple；

The source of tenth NMOS tube and third control subelement coupling, the grid end of the tenth NMOS tube with it is described before The output terminal coupling of grade inverting clock signal, drain terminal and the clock signal output terminal of the tenth NMOS tube couple.

20. latch according to claim 16, which is characterized in that the third control subelement includes the 11st NMOS Pipe and the 12nd NMOS tube；

The source of 11st NMOS tube is coupled with the reference ground, grid end and the clock of the 11st NMOS tube Signal output end couples, and the drain terminal of the 11st NMOS tube is coupled with the source of the 5th NMOS tube；

The source of 12nd NMOS tube is coupled with the reference ground, grid end and the reverse phase of the 12nd NMOS tube Clock signal output terminal couples, and the drain terminal of the 12nd NMOS tube is coupled with the source of the 6th NMOS tube.

21. latch according to claim 20, which is characterized in that the 4th control subelement includes the 13rd NMOS Pipe and the 14th NMOS tube；

The source of 13rd NMOS tube and the drain terminal of the 5th NMOS tube couple, the grid end of the 13rd NMOS tube with The prime clock signal output terminal coupling, drain terminal and the inverting clock signal output terminal coupling of the 13rd NMOS tube It connects；

The source of 14th NMOS tube and the drain terminal of the 6th NMOS tube couple, the grid end of the 14th NMOS tube with The prime inverting clock signal output terminal coupling, drain terminal and the clock signal output terminal coupling of the 14th NMOS tube It connects.

22. a kind of frequency divider, which is characterized in that including at least two such as claim 1-21 any one of them latch；Institute It is defeated with the clock signal of another latch respectively to state the first input end of any latch and the second input terminal in two latch Outlet and the coupling of inverting clock signal output terminal.