CN113098488A - Latch unit and frequency divider - Google Patents
Latch unit and frequency divider Download PDFInfo
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- CN113098488A CN113098488A CN202110345759.3A CN202110345759A CN113098488A CN 113098488 A CN113098488 A CN 113098488A CN 202110345759 A CN202110345759 A CN 202110345759A CN 113098488 A CN113098488 A CN 113098488A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
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- H03K21/00—Details of pulse counters or frequency dividers
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Abstract
The invention provides a latch unit and a frequency divider, wherein the latch unit comprises: a first differential circuit for inputting a first polarity clock signal and a differential input signal pair; a second differential circuit connected to the first differential circuit, for inputting a second polarity clock signal, inputting the differential input signal pair simultaneously with the first differential circuit, and outputting a differential output signal pair; the first polarity clock signal and the second polarity clock signal are a pair of inverted clock signals. The invention greatly reduces the power consumption and can be widely applied to the fields with high requirement on the power consumption and long requirement on the endurance time.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and more particularly, to a latch unit and a frequency divider.
Background
Frequency dividers are widely used in integrated circuit chips, in the rf receive and transmit path, a divide-by-two circuit is often used to generate a quadrature local oscillator signal, and frequency dividers are also often used in a phase-locked loop feedback loop to divide a high frequency signal generated by a voltage controlled oscillator to a low frequency for phase/frequency comparison with a reference signal. The basic unit forming the frequency divider is a latch, the frequency dividing circuit is usually formed by two latches, and an important means for realizing the low-power-consumption frequency divider is to realize the low-power-consumption latch. Fig. 1 shows a block diagram of a divide-by-two circuit, which is composed of two latches.
Portable electronic devices generally require low power consumption of integrated circuits to improve the endurance of the devices and enhance user experience, and therefore low power consumption design is an important issue in modern integrated circuit design. The latch is a basic unit forming the frequency divider, and how to reduce the power consumption of the latch in a common module of an integrated circuit is an urgent problem to be solved.
Disclosure of Invention
The invention aims to provide a latch unit and a frequency divider, which can greatly reduce power consumption and can be widely applied to the fields with high power consumption requirement and long endurance time requirement.
The technical scheme provided by the invention is as follows:
the present invention provides a latch unit comprising:
a first differential circuit for inputting a first polarity clock signal and a differential input signal pair;
a second differential circuit connected to the first differential circuit, for inputting a second polarity clock signal, inputting the differential input signal pair simultaneously with the first differential circuit, and outputting a differential output signal pair; the first polarity clock signal and the second polarity clock signal are a pair of inverted clock signals.
The present invention also provides a latch unit comprising:
a third differential circuit for inputting the first polarity clock signal and outputting a differential output signal pair;
a fourth differential circuit connected to the third differential circuit, for inputting a second polarity clock signal and inputting a differential input signal pair, and outputting the differential output signal pair simultaneously with the third differential circuit; the first polarity clock signal and the second polarity clock signal are a pair of inverted clock signals.
The invention also provides a frequency divider, which is integrated with the latch unit.
The latch unit and the frequency divider provided by the invention can greatly reduce power consumption, and can be widely applied to the fields with high power consumption requirement and long endurance time requirement.
Drawings
The above features, technical features, advantages and implementations of a latch unit and a frequency divider will be further explained in a clearly understandable manner in the following description of preferred embodiments in conjunction with the accompanying drawings.
FIG. 1 is a block diagram of a divide-by-two circuit;
FIG. 2 is a circuit schematic of one embodiment of a latch cell of the present invention;
FIG. 3 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 4 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 5 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 6 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 7 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 8 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 9 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 10 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 11 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 12 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 13 is a circuit schematic of another embodiment of a latch cell of the present invention;
FIG. 14 is a circuit schematic of another embodiment of a latch cell of the present invention;
fig. 15 is a circuit schematic of another embodiment of a latch cell of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
In addition, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not intended to indicate or imply relative importance.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
One embodiment of the present invention, as shown in FIG. 2, is a latch cell comprising:
a first differential circuit for inputting a first polarity clock signal and a differential input signal pair;
a second differential circuit connected to the first differential circuit, for inputting a second polarity clock signal, inputting the differential input signal pair simultaneously with the first differential circuit, and outputting a differential output signal pair; the first polarity clock signal and the second polarity clock signal are a pair of inverted clock signals.
Specifically, the differential input signal pair includes a non-inverting input signal and an inverting input signal, and the differential output signal pair includes a non-inverting output signal and an inverting output signal.
Based on the foregoing embodiment, the second differential circuit includes:
the first differential signal transceiving module is used for inputting a positive phase input signal in the differential input signal pair;
the second differential signal transceiving module is used for inputting a negative phase input signal in the differential input signal pair;
the first ports and the second ports of the first differential signal transceiver module and the second differential signal transceiver module are cross-connected with each other to output a negative phase output signal and a positive phase output signal in the differential output signal pair respectively;
and the first clock signal input module is respectively connected with the third ports of the first differential signal transceiver module and the second differential signal transceiver module and is used for inputting the second polarity clock signal.
Based on the foregoing embodiment, the first differential signal transceiving module includes: the MOS transistor comprises a first MOS transistor and a third MOS transistor;
the second differential signal transceiving module includes: a second MOS tube and a fourth MOS tube;
the first clock signal input module includes: a fifth MOS transistor;
the first MOS tube and the third MOS tube share a drain electrode and are connected with a grid electrode of the fourth MOS tube;
the second MOS tube and the fourth MOS tube share a drain electrode and are connected with a grid electrode of the third MOS tube;
the third MOS tube and the fourth MOS tube share a common source and are connected with a first polarity interface;
the positive-phase input signal is input to the grid electrode of the first MOS tube, and the negative-phase input signal is input to the grid electrode of the second MOS tube;
the source electrodes of the first MOS tube and the second MOS tube are respectively connected with the drain electrode of the fifth MOS tube, the grid electrode of the fifth MOS tube inputs the second polarity clock signal, and the source electrode of the fifth MOS tube is connected with the first polarity interface;
the channel types of the first MOS tube, the third MOS tube, the second MOS tube, the fourth MOS tube and the fifth MOS tube are the same; the first port and the second port of the first differential signal transceiver module are respectively a drain electrode and a grid electrode of the third MOS tube; a first port and a second port of the second differential signal transceiver module are respectively a drain electrode and a grid electrode of the fourth MOS tube; and the third ports of the first differential signal transceiver module and the second differential signal transceiver module are respectively the source electrodes of the first MOS transistor and the second MOS transistor.
Based on the foregoing embodiment, the first differential circuit includes:
the second clock signal input module is used for inputting the first polarity clock signal;
and the first differential signal input module is respectively connected with the first ports of the first differential signal transceiver module and the second differential signal transceiver module, and the second clock signal input module and is used for inputting the differential input signal pair.
Based on the foregoing embodiments, the second clock signal input module includes: a sixth MOS transistor and a seventh MOS transistor;
the first differential signal input module includes: an eighth MOS transistor and a ninth MOS transistor;
the sixth MOS tube and the seventh MOS tube share a common source and are connected with the second polarity interface;
the sixth MOS tube and the seventh MOS tube share a grid and are connected with the first polarity clock signal;
the drain of the sixth MOS transistor is connected to the source of the eighth MOS transistor, the drain of the eighth MOS transistor is connected to the first port of the first differential signal transceiver module, and the gate of the eighth MOS transistor is connected to the positive-phase input signal of the differential input signal pair;
the drain electrode of the seventh MOS transistor is connected to the source electrode of the ninth MOS transistor, the drain electrode of the ninth MOS transistor is connected to the first port of the second differential signal transceiver module, and the gate electrode of the ninth MOS transistor is connected to the negative-phase input signal in the differential input signal pair;
the channel types of the sixth MOS tube, the seventh MOS tube, the eighth MOS tube and the ninth MOS tube are the same and are opposite to the channel type of the first MOS tube.
Based on the foregoing embodiment, the drain of the sixth MOS transistor is short-circuited with the drain of the seventh MOS transistor, and the source of the eighth MOS transistor is short-circuited with the source of the ninth MOS transistor.
Specifically, the first differential circuit and the second differential circuit include the following four cases.
In the first case: if the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor and the fifth MOS transistor are all N-type MOS transistors, as shown in fig. 3, the first MOS transistor, the third MOS transistor, the second MOS transistor, the fourth MOS transistor and the fifth MOS transistor are respectively a first N-type MOS transistor MN1, a third N-type MOS transistor MN3, a second N-type MOS transistor MN2, a fourth N-type MOS transistor MN4 and a fifth N-type MOS transistor MN 5. The sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are respectively a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3 and a fourth P-type MOS transistor MP 4. At this time, the first polarity interface is grounded, the second polarity interface is a power supply VDD, the first polarity clock signal is CKN, the second polarity clock signal is CKP, the positive phase input signal is D, the negative phase input signal is DB, the positive phase output signal is Q, and the negative phase output signal is QB. At this time, the sources of the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 are respectively connected to the power supply VDD, the gates of the first N-type MOS transistor MN1 and the third P-type MOS transistor MP3 are respectively connected to D, and the gates of the second N-type MOS transistor MN2 and the fourth P-type MOS transistor MP4 are respectively connected to DB. The gates of the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 are respectively connected to CKN, and the gate of the fifth N-type MOS transistor MN5 is connected to CKP.
In fig. 3, when CKN is 0 and CKP is 1, the gate of the N-type MOS transistor is turned on at a high level and the gate of the P-type MOS transistor is turned on at a low level, as can be seen from the principle that the level of D is 0 or 1, a direct path from the power supply to the ground does not exist, that is, no static current from the power supply to the ground exists. For example, when D is 0 and DB is 1, MP4 is off so that Q is pulled down to 0, so there is no direct path from power to ground for the right leg, and MN3 is off because MN1 is off and Q is 0, so there is no direct path from power to ground for the left leg, so there is no quiescent current from power to ground at this time. Also for example, when D is 1 and DB is 0, MP3 is off so that QB is pulled down to 0, so there is no direct path from supply to ground for the left leg, and MN4 is off because of the off of MN2 with QB of 0, so there is no direct path from supply to ground for the right leg. Because no static current exists from a power supply to the ground, the latch unit formed by the structure of fig. 3 has no static current when CKN is 0 and CKP is 1, and the power consumption of the latch unit is greatly reduced.
In the second case: if the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor and the fifth MOS transistor are all N-type MOS transistors, as shown in fig. 4, the latch unit of this embodiment is only short-circuited between the drain of the first P-type MOS transistor MP1 and the drain of the second P-type MOS transistor MP2, and short-circuited between the source of the third P-type MOS transistor MP3 and the source of the fourth P-type MOS transistor MP4, compared with the latch unit shown in fig. 3. Because the signal input mode is not changed, the latch unit composed by the structure of fig. 4 has no static current when CKN is 0 and CKP is 1, as in fig. 3, and the power consumption of the latch unit is greatly reduced.
In the third case: if the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are all P-type MOS transistors, as shown in fig. 6, the first MOS transistor, the third MOS transistor, the second MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are respectively a first P-type MOS transistor MP1, a third P-type MOS transistor MP3, a second P-type MOS transistor MP2, a fourth P-type MOS transistor MP4, and a fifth P-type MOS transistor MP 5. The sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are respectively a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3 and a fourth N-type MOS transistor MN 4. At this time, the first polarity interface is a power supply VDD, the second polarity interface is ground, the first polarity clock signal is CKP, the second polarity clock signal is CKN, the positive phase input signal is D, the negative phase input signal is DB, the positive phase output signal is Q, and the negative phase output signal is QB. At this time, the sources of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 are grounded, the gates of the first P-type MOS transistor MP1 and the third N-type MOS transistor MN3 are connected to D, and the gates of the second P-type MOS transistor MP2 and the fourth N-type MOS transistor MN4 are connected to DB. The gates of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 are respectively connected to CKP, and the gate of the fifth P-type MOS transistor MP5 is connected to CKN.
In fig. 6, when CKP is 1 and CKN is 0, the gate of the N-type MOS transistor is turned on at a high level and the gate of the P-type MOS transistor is turned on at a low level, as can be seen from the principle that the level of D is 0 or 1, a direct path from the power supply to the ground does not exist, that is, no static current from the power supply to the ground exists. For example, when D is 0 and DB is 1, MN3 is open so that QB is pulled up to 1, so there is no direct path from supply to ground for the left leg, since MP2 is open, QB is 1, causing MP4 to be open, so there is no direct path from supply to ground for the right leg, so there is no quiescent current from supply to ground at this time. Also for example, when D is 1 and DB is 0, MN4 is off such that Q is pulled up to 1, so there is no direct path from power to ground for the right leg, and since MP1 is off, Q is 1 causing MP3 to be off, so there is no direct path from power to ground for the left leg. Because no static current exists from a power supply to the ground, the latch unit formed by the structure of fig. 6 has no static current when CKP is equal to 1 and CKN is equal to 0, and the power consumption of the latch unit is greatly reduced.
In a fourth case: if the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor and the fifth MOS transistor are all P-type MOS transistors, as shown in fig. 7, the latch unit of this embodiment, as compared to the latch unit shown in fig. 6, only has the drain of the first N-type MOS transistor MN1 and the drain of the second N-type MOS transistor MN2 shorted together, and has the source of the third N-type MOS transistor MN3 and the source of the fourth N-type MOS transistor MN4 shorted together. Because the signal input mode is not changed, the latch unit composed by the structure of fig. 7 has no static current when CKP is 1 and CKN is 0, as in fig. 6, and the power consumption of the latch unit is greatly reduced.
Based on the foregoing embodiments, the second clock signal input module includes: a sixth MOS transistor and a seventh MOS transistor;
the first differential signal input module includes: an eighth MOS transistor and a ninth MOS transistor;
the sixth MOS tube and the seventh MOS tube share a common source and are connected with the second polarity interface;
the grid electrode of the sixth MOS tube is connected to a positive phase input signal in the differential input signal pair;
the grid electrode of the seventh MOS tube is connected to a negative phase input signal in the differential input signal pair;
the drain electrode of the sixth MOS tube is connected with the source electrode of the eighth MOS tube, and the drain electrode of the eighth MOS tube is connected with the first port of the first differential signal transceiver module;
the drain electrode of the seventh MOS tube is connected with the source electrode of the ninth MOS tube, and the drain electrode of the ninth MOS tube is connected with the first port of the second differential signal transceiver module;
the eighth MOS transistor and the ninth MOS transistor share a grid and are connected with the first polarity clock signal;
the channel types of the sixth MOS tube, the seventh MOS tube, the eighth MOS tube and the ninth MOS tube are the same and are opposite to the channel type of the first MOS tube.
Specifically, the first differential circuit and the second differential circuit include the following two cases in addition to the above two cases.
In the fifth case: if the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube and the fifth MOS tube are N-type MOS tubes, the first MOS tube, the third MOS tube, the second MOS tube, the fourth MOS tube and the fifth MOS tube are respectively a first N-type MOS tube MN1, a third N-type MOS tube MN3, a second N-type MOS tube MN2, a fourth N-type MOS tube MN4 and a fifth N-type MOS tube MN 5. The sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are respectively a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3 and a fourth P-type MOS transistor MP 4. At this time, the first polarity interface is grounded, the second polarity interface is a power supply VDD, the first polarity clock signal is CKN, the second polarity clock signal is CKP, the positive phase input signal is D, the negative phase input signal is DB, the positive phase output signal is Q, and the negative phase output signal is QB. At this time, the sources of the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 are respectively connected to the power supply VDD, the gates of the first P-type MOS transistor MP1 and the first N-type MOS transistor MN1 are respectively connected to D, and the gates of the second P-type MOS transistor MP2 and the second N-type MOS transistor MN2 are respectively connected to DB. The gates of the third P-type MOS transistor MP3 and the fourth P-type MOS transistor MP4 are respectively connected to CKN, and the gate of the fifth N-type MOS transistor MN5 is connected to CKP.
In fig. 5, when CKN is 0 and CKP is 1, the gate of the N-type MOS transistor is turned on at a high level and the gate of the P-type MOS transistor is turned on at a low level, as can be seen from the principle that the level of D is 0 or 1, a direct path from the power supply to the ground does not exist, that is, no static current from the power supply to the ground exists. For example, when D is 0 and DB is 1, MP2 is off so that Q is pulled down to 0, so there is no direct path from power to ground for the right leg, and MN3 is off because MN1 is off and Q is 0, so there is no direct path from power to ground for the left leg, so there is no quiescent current from power to ground at this time. Also for example, when D is 1 and DB is 0, MP1 is off so that QB is pulled down to 0, so there is no direct path from supply to ground for the left leg, and MN4 is off because of the off of MN2 with QB of 0, so there is no direct path from supply to ground for the right leg. Because no static current exists from the power supply to the ground, the latch unit formed by the structure of fig. 5 has no static current when CKN is 0 and CKP is 1, and the power consumption of the latch unit is greatly reduced.
In the sixth case: if the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube and the fifth MOS tube are all P-type MOS tubes, the first MOS tube, the third MOS tube, the second MOS tube, the fourth MOS tube and the fifth MOS tube are respectively a first P-type MOS tube MP1, a third P-type MOS tube MP3, a second P-type MOS tube MP2, a fourth P-type MOS tube MP4 and a fifth P-type MOS tube MP 5. The sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are respectively a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3 and a fourth N-type MOS transistor MN 4. At this time, the first polarity interface is a power supply VDD, the second polarity interface is ground, the first polarity clock signal is CKP, the second polarity clock signal is CKN, the positive phase input signal is D, the negative phase input signal is DB, the positive phase output signal is Q, and the negative phase output signal is QB. At this time, the sources of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 are connected to the power supply VDD, respectively, and the source of the fifth P-type MOS transistor MP5 is connected to the power supply VDD. The grids of the first N-type MOS transistor MN1 and the first P-type MOS transistor MP1 are respectively connected to D, and the grids of the second N-type MOS transistor MN2 and the second N-type MOS transistor MN2 are respectively connected to DB. The gates of the third N-type MOS transistor MN3 and the fourth N-type MOS transistor MN4 are respectively connected to CKP, and the gate of the fifth P-type MOS transistor MP5 is connected to CKN.
In fig. 8, when CKP is 1 and CKN is 0, the gate of the N-type MOS transistor is turned on at a high level and the gate of the P-type MOS transistor is turned on at a low level, as can be seen from the principle that the level of D is 0 or 1, a direct path from the power supply to the ground does not exist, that is, no static current from the power supply to the ground exists. For example, when D is 0 and DB is 1, MN1 is open so that QB is pulled up to 1, so there is no direct path from supply to ground for the left leg, since MP2 is open, QB is 1, causing MP4 to be open, so there is no direct path from supply to ground for the right leg, so there is no quiescent current from supply to ground at this time. Also for example, when D is 1 and DB is 0, MN2 is off such that Q is pulled up to 1, so there is no direct path from power to ground for the right leg, and since MP1 is off, Q is 1 causing MP3 to be off, so there is no direct path from power to ground for the left leg. Because no static current exists from the power supply to the ground, the latch unit composed of the structure of fig. 8 has no static current when CKP is equal to 1 and CKN is equal to 0, and the power consumption of the latch unit is greatly reduced.
One embodiment of the present invention, as shown in FIG. 9, is a latch cell comprising:
a third differential circuit for inputting the first polarity clock signal and outputting a differential output signal pair;
a fourth differential circuit connected to the third differential circuit, for inputting a second polarity clock signal and inputting a differential input signal pair, and outputting the differential output signal pair simultaneously with the third differential circuit; the first polarity clock signal and the second polarity clock signal are a pair of inverted clock signals.
Specifically, the differential input signal pair includes a non-inverting input signal and an inverting input signal, and the differential output signal pair includes a non-inverting output signal and an inverting output signal.
Based on the foregoing embodiment, the fourth differential circuit includes:
a third differential signal transceiver module, configured to input a positive-phase input signal in the differential input signal pair and output a negative-phase output signal in the differential output signal pair;
a fourth differential signal transceiver module, configured to input a negative-phase input signal in the differential input signal pair and output a positive-phase output signal in the differential output signal pair;
the first ports and the second ports of the third differential signal transceiver module and the fourth differential signal transceiver module are cross-connected with each other to output a negative phase output signal and a positive phase output signal in the differential output signal pair respectively;
and the third clock signal input module is respectively connected with the third ports of the third differential signal transceiver module and the fourth differential signal transceiver module and is used for inputting the second polarity clock signal.
Based on the foregoing embodiment, the third differential signaling transceiver module includes: the MOS transistor comprises a first MOS transistor and a third MOS transistor;
the fourth differential signal transceiving module includes: a second MOS tube and a fourth MOS tube;
the third clock signal input module includes: a fifth MOS transistor;
the first MOS tube and the third MOS tube share a drain electrode and are connected with a grid electrode of the fourth MOS tube;
the second MOS tube and the fourth MOS tube share a drain electrode and are connected with a grid electrode of the third MOS tube;
the third MOS tube and the fourth MOS tube share a common source and are connected with a first polarity interface;
the positive-phase input signal is input to the grid electrode of the first MOS tube, and the negative-phase input signal is input to the grid electrode of the second MOS tube;
the source electrodes of the first MOS tube and the second MOS tube are respectively connected with the drain electrode of the fifth MOS tube, the grid electrode of the fifth MOS tube inputs the second polarity clock signal, and the source electrode of the fifth MOS tube is connected with the first polarity interface;
the channel types of the first MOS tube, the third MOS tube, the second MOS tube, the fourth MOS tube and the fifth MOS tube are the same; a first port of the third differential signal transceiver module is a first junction of a first MOS transistor, a third MOS transistor and an eighth MOS transistor, and a second port of the third differential signal transceiver module is a gate of the third MOS transistor; a first port of the fourth differential signal transceiver module is a second junction of a second MOS transistor, a fourth MOS transistor and a ninth MOS transistor, and a second port of the fourth differential signal transceiver module is a gate of the fourth MOS transistor; and the third ports of the third differential signal transceiver module and the fourth differential signal transceiver module are respectively the source electrodes of the first MOS transistor and the second MOS transistor.
Based on the foregoing embodiment, the third differential circuit includes:
the fourth clock signal input module is used for inputting the first polarity clock signal;
and the second differential signal input module is connected with the fourth clock signal input module, is respectively and mutually cross-connected with the fourth ports of the third differential signal transceiver module and the fourth differential signal transceiver module, and is used for outputting the differential output signal pair.
Based on the foregoing embodiment, the fourth clock signal input module includes: a sixth MOS transistor and a seventh MOS transistor;
the second differential signal input module includes: an eighth MOS transistor and a ninth MOS transistor;
the sixth MOS tube and the seventh MOS tube share a common source and are connected with the second polarity interface;
the sixth MOS tube and the seventh MOS tube share a grid and are connected with the first polarity clock signal;
the drain electrode of the sixth MOS tube is connected with the source electrode of the eighth MOS tube, and the drain electrode of the eighth MOS tube is connected with the first port of the third differential signal transceiver module;
the drain electrode of the seventh MOS transistor is connected to the source electrode of the ninth MOS transistor, and the drain electrode of the ninth MOS transistor is connected to the first port of the fourth differential signal transceiver module;
a gate of the eighth MOS transistor is connected to the first port of the third differential signal transceiver module to output a positive phase output signal of the differential output signal pair;
a grid electrode of the ninth MOS tube is connected with a first port of the fourth differential signal transceiver module so as to output a negative phase output signal in the differential output signal pair;
the channel types of the sixth MOS tube, the seventh MOS tube, the eighth MOS tube and the ninth MOS tube are the same and are opposite to the channel type of the first MOS tube; the fourth port of the third differential signal transceiver module is a node which is close to the eighth MOS transistor and far away from the first junction on the connection line of the third MOS transistor and the eighth MOS transistor, and the fourth port of the fourth differential signal transceiver module is a node which is close to the ninth MOS transistor and far away from the second junction on the connection line of the fourth MOS transistor and the ninth MOS transistor.
Based on the foregoing embodiment, the drain of the sixth MOS transistor is short-circuited with the drain of the seventh MOS transistor, and the source of the eighth MOS transistor is short-circuited with the source of the ninth MOS transistor.
Specifically, the third differential circuit and the fourth differential circuit include the following four cases.
In the first case: if the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor and the fifth MOS transistor are all N-type MOS transistors, as shown in fig. 10, the first MOS transistor, the third MOS transistor, the second MOS transistor, the fourth MOS transistor and the fifth MOS transistor are respectively a first N-type MOS transistor MN1, a third N-type MOS transistor MN3, a second N-type MOS transistor MN2, a fourth N-type MOS transistor MN4 and a fifth N-type MOS transistor MN 5. The sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are respectively a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3 and a fourth P-type MOS transistor MP 4. At this time, the first polarity interface is grounded, the second polarity interface is a power supply VDD, the first polarity clock signal is CKN, the second polarity clock signal is CKP, the positive phase input signal is D, the negative phase input signal is DB, the positive phase output signal is Q, and the negative phase output signal is QB. At this time, the sources of the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 are connected to the power supply VDD, the gate of the first N-type MOS transistor MN1 is connected to D, and the gate of the second N-type MOS transistor MN2 is connected to DB. The gates of the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 are respectively connected to CKN, and the gate of the fifth N-type MOS transistor MN5 is connected to CKP.
In fig. 10, when CKN is 0 and CKP is 1, the gate of the N-type MOS transistor is turned on at a high level and the gate of the P-type MOS transistor is turned on at a low level, as can be seen from the principle that the level of D is 0 or 1, a direct path from the power supply to the ground does not exist, that is, no static current from the power supply to the ground exists. For example, when D is 0 and DB is 1, QB is pulled up to 1, Q is pulled down to 0, MP4 is off, so there is no direct path from supply to ground for the right leg, Q is 0 resulting in MN3 being off, so there is no direct path from supply to ground for the left leg, so there is no quiescent current from supply to ground at this time. Also for example when D is 1 and DB is 0 QB is pulled down to 0, Q is pulled up to 1, MP3 is off, so there is no direct path from supply to ground for the left leg, QB is 0 resulting in MN4 being off, so there is no direct path from supply to ground for the right leg. Because no static current exists from the power supply to the ground, the latch unit formed by the structure of fig. 10 has no static current when CKN is 0 and CKP is 1, and the power consumption of the latch unit is greatly reduced.
In the second case: if the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor and the fifth MOS transistor are all N-type MOS transistors, as shown in fig. 11, the latch unit of this embodiment is only short-circuited between the drain of the first P-type MOS transistor MP1 and the drain of the second P-type MOS transistor MP2, and short-circuited between the source of the third P-type MOS transistor MP3 and the source of the fourth P-type MOS transistor MP4, compared with the latch unit shown in fig. 10. Since the signal input mode is not changed, the latch unit composed of the structure of fig. 11 has no static current when CKN is 0 and CKP is 1, as in fig. 10, which greatly reduces the power consumption of the latch unit.
In the third case: if the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are all P-type MOS transistors, as shown in fig. 12, the first MOS transistor, the third MOS transistor, the second MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are respectively a first P-type MOS transistor MP1, a third P-type MOS transistor MP3, a second P-type MOS transistor MP2, a fourth P-type MOS transistor MP4, and a fifth P-type MOS transistor MP 5. The sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are respectively a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3 and a fourth N-type MOS transistor MN 4. At this time, the first polarity interface is a power supply VDD, the second polarity interface is ground, the first polarity clock signal is CKP, the second polarity clock signal is CKN, the positive phase input signal is D, the negative phase input signal is DB, the positive phase output signal is Q, and the negative phase output signal is QB. At this time, the sources of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 are grounded, the gate of the first P-type MOS transistor MP1 is connected to D, and the gate of the second P-type MOS transistor MP2 is connected to DB. The gates of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 are respectively connected to CKP, and the gate of the fifth P-type MOS transistor MP5 is connected to CKN.
In fig. 12, when CKP is 1 and CKN is 0, the gate of the N-type MOS transistor is turned on at a high level and the gate of the P-type MOS transistor is turned on at a low level, as can be seen from the principle that the level of D is 0 or 1, a direct path from the power supply to the ground does not exist, that is, no static current from the power supply to the ground exists. For example, when D is 0 and DB is 1, QB is pulled up to 1, Q is pulled down to 0, MN3 is off, so there is no direct path from supply to ground for the left leg, QB is 1 resulting in MP4 being off, so there is no direct path from supply to ground for the right leg, so there is no quiescent current from supply to ground at this time. Also for example, when D is 1 and DB is 0, QB is pulled down to 0, Q is pulled up to 1, MN4 is off, so there is no direct path from supply to ground for the right leg, Q is 1 resulting in MP3 being off, so there is no direct path from supply to ground for the left leg. Because no static current exists from the power supply to the ground, the latch unit formed by the structure of fig. 12 has no static current when CKP is equal to 1 and CKN is equal to 0, and the power consumption of the latch unit is greatly reduced.
In a fourth case: if the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor and the fifth MOS transistor are all P-type MOS transistors, as shown in fig. 13, the latch unit of this embodiment is only short-circuited between the drain of the first N-type MOS transistor MN1 and the drain of the second N-type MOS transistor MN2, and short-circuited between the source of the third N-type MOS transistor MN3 and the source of the fourth N-type MOS transistor MN4, compared with the latch unit shown in fig. 12. Because the signal input mode is not changed, the latch unit composed by the structure of fig. 13 has no static current when CKP is 1 and CKN is 0, as in fig. 12, and the power consumption of the latch unit is greatly reduced.
Based on the foregoing embodiment, the fourth clock signal input module includes: a sixth MOS transistor and a seventh MOS transistor;
the second differential signal input module includes: an eighth MOS transistor and a ninth MOS transistor;
the sixth MOS tube and the seventh MOS tube share a common source and are connected with the second polarity interface;
the drain electrode of the sixth MOS tube is connected with the source electrode of the eighth MOS tube, and the drain electrode of the eighth MOS tube is connected with the first port of the third differential signal transceiver module;
the drain electrode of the seventh MOS transistor is connected to the source electrode of the ninth MOS transistor, and the drain electrode of the ninth MOS transistor is connected to the first port of the fourth differential signal transceiver module;
a grid electrode of the sixth MOS transistor is connected to the first port of the fourth differential signal transceiver module, and a grid electrode of the seventh MOS transistor is connected to the first port of the third differential signal transceiver module;
the grid electrodes of the eighth MOS tube and the ninth MOS tube are respectively connected to the first polarity clock signal;
the drain electrode of the eighth MOS transistor is connected to the first port of the third differential signal transceiver module to output a negative phase output signal of the differential output signal pair;
a drain electrode of the ninth MOS transistor is connected to the first port of the fourth differential signal transceiver module to output a positive phase output signal of the differential output signal pair;
the channel types of the sixth MOS tube, the seventh MOS tube, the eighth MOS tube and the ninth MOS tube are the same and are opposite to the channel type of the first MOS tube.
Specifically, the third differential circuit and the fourth differential circuit include the following two cases in addition to the above two cases.
In the fifth case: if the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube and the fifth MOS tube are N-type MOS tubes, the first MOS tube, the third MOS tube, the second MOS tube, the fourth MOS tube and the fifth MOS tube are respectively a first N-type MOS tube MN1, a third N-type MOS tube MN3, a second N-type MOS tube MN2, a fourth N-type MOS tube MN4 and a fifth N-type MOS tube MN 5. Then, as shown in fig. 14, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are the first P-type MOS transistor MP1, the second P-type MOS transistor MP2, the third P-type MOS transistor MP3 and the fourth P-type MOS transistor MP4, respectively. At this time, the first polarity interface is grounded, the second polarity interface is a power supply VDD, the first polarity clock signal is CKN, the second polarity clock signal is CKP, the positive phase input signal is D, the negative phase input signal is DB, the positive phase output signal is Q, and the negative phase output signal is QB. At this time, the sources of the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 are connected to the power supply VDD, the gate of the first N-type MOS transistor MN1 is connected to D, and the gate of the second N-type MOS transistor MN2 is connected to DB. The gates of the third P-type MOS transistor MP3 and the fourth P-type MOS transistor MP4 are respectively connected to CKN, and the gate of the fifth N-type MOS transistor MN5 is connected to CKP.
In fig. 14, when CKN is 0 and CKP is 1, the gate of the N-type MOS transistor is turned on at a high level and the gate of the P-type MOS transistor is turned on at a low level, as can be seen from the principle that the level of D is 0 or 1, a direct path from the power supply to the ground does not exist, that is, no static current from the power supply to the ground exists. For example, when D is 0 and DB is 1, QB is pulled up to 1, Q is pulled down to 0, MP2 is off, so there is no direct path from supply to ground for the right leg, Q is 0 resulting in MN3 being off, so there is no direct path from supply to ground for the left leg, so there is no quiescent current from supply to ground at this time. Also for example when D is 1 and DB is 0 QB is pulled down to 0, Q is pulled up to 1, MP1 is off, so there is no direct path from supply to ground for the left leg, QB is 0 resulting in MN4 being off, so there is no direct path from supply to ground for the right leg. Because no static current exists from the power supply to the ground, the latch unit formed by the structure of fig. 14 has no static current when CKN is 0 and CKP is 1, and the power consumption of the latch unit is greatly reduced.
In the sixth case: if the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube and the fifth MOS tube are all P-type MOS tubes, the first MOS tube, the third MOS tube, the second MOS tube, the fourth MOS tube and the fifth MOS tube are respectively a first P-type MOS tube MP1, a third P-type MOS tube MP3, a second P-type MOS tube MP2, a fourth P-type MOS tube MP4 and a fifth P-type MOS tube MP 5. Then, as shown in fig. 15, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are the first N-type MOS transistor MN1, the second N-type MOS transistor MN2, the third N-type MOS transistor MN3 and the fourth N-type MOS transistor MN4, respectively. At this time, the first polarity interface is a power supply VDD, the second polarity interface is ground, the first polarity clock signal is CKP, the second polarity clock signal is CKN, the positive phase input signal is D, the negative phase input signal is DB, the positive phase output signal is Q, and the negative phase output signal is QB. At this time, the sources of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 are grounded, the source of the fifth P-type MOS transistor MP5 is connected to the power supply VDD, the gate of the first P-type MOS transistor MP1 is connected to D, and the gate of the second P-type MOS transistor MP2 is connected to DB. The gates of the third N-type MOS transistor MN3 and the fourth N-type MOS transistor MN4 are respectively connected to CKP, and the gate of the fifth P-type MOS transistor MP5 is connected to CKN.
In fig. 15, when CKP is 1 and CKN is 0, the gate of the N-type MOS transistor is turned on at a high level and the gate of the P-type MOS transistor is turned on at a low level, as can be seen from the principle that the level of D is 0 or 1, a direct path from the power supply to the ground does not exist, that is, no static current from the power supply to the ground exists. For example, when D is 0 and DB is 1, QB is pulled up to 1, Q is pulled down to 0, MN1 is off, so there is no direct path from supply to ground for the left leg, QB is 1 resulting in MP4 being off, so there is no direct path from supply to ground for the right leg, so there is no quiescent current from supply to ground at this time. Also for example, when D is 1 and DB is 0, QB is pulled down to 0, Q is pulled up to 1, MN2 is off, so there is no direct path from supply to ground for the right leg, Q is 1 resulting in MP3 being off, so there is no direct path from supply to ground for the left leg. Because no static current exists from the power supply to the ground, the latch unit formed by the structure of fig. 15 has no static current when CKP is equal to 1 and CKN is equal to 0, and the power consumption of the latch unit is greatly reduced.
In one embodiment of the invention, a frequency divider is integrated with the latch unit.
The latch provided by the invention can form a low-power-consumption frequency divider, and can be widely applied to the fields with high power consumption requirements and long endurance requirements.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of program modules is illustrated, and in practical applications, the above-described distribution of functions may be performed by different program modules, that is, the internal structure of the apparatus may be divided into different program units or modules to perform all or part of the above-described functions. Each program module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one processing unit, and the integrated unit may be implemented in a form of hardware, or may be implemented in a form of software program unit. In addition, the specific names of the program modules are only used for distinguishing the program modules from one another, and are not used for limiting the protection scope of the application.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or recited in detail in a certain embodiment.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (16)
1. A latch cell, comprising:
a first differential circuit for inputting a first polarity clock signal and a differential input signal pair;
a second differential circuit connected to the first differential circuit, for inputting a second polarity clock signal, inputting the differential input signal pair simultaneously with the first differential circuit, and outputting a differential output signal pair; the first polarity clock signal and the second polarity clock signal are a pair of inverted clock signals.
2. The latch unit of claim 1, wherein the second differential circuit comprises:
the first differential signal transceiving module is used for inputting a positive phase input signal in the differential input signal pair;
the second differential signal transceiving module is used for inputting a negative phase input signal in the differential input signal pair;
the first ports and the second ports of the first differential signal transceiver module and the second differential signal transceiver module are cross-connected with each other to output a negative phase output signal and a positive phase output signal in the differential output signal pair respectively;
and the first clock signal input module is respectively connected with the third ports of the first differential signal transceiver module and the second differential signal transceiver module and is used for inputting the second polarity clock signal.
3. The latch unit of claim 2, wherein:
the first differential signal transceiving module includes: the MOS transistor comprises a first MOS transistor and a third MOS transistor;
the second differential signal transceiving module includes: a second MOS tube and a fourth MOS tube;
the first clock signal input module includes: a fifth MOS transistor;
the first MOS tube and the third MOS tube share a drain electrode and are connected with a grid electrode of the fourth MOS tube;
the second MOS tube and the fourth MOS tube share a drain electrode and are connected with a grid electrode of the third MOS tube;
the third MOS tube and the fourth MOS tube share a common source and are connected with a first polarity interface;
the positive-phase input signal is input to the grid electrode of the first MOS tube, and the negative-phase input signal is input to the grid electrode of the second MOS tube;
the source electrodes of the first MOS tube and the second MOS tube are respectively connected with the drain electrode of the fifth MOS tube, the grid electrode of the fifth MOS tube inputs the second polarity clock signal, and the source electrode of the fifth MOS tube is connected with the first polarity interface;
the channel types of the first MOS tube, the third MOS tube, the second MOS tube, the fourth MOS tube and the fifth MOS tube are the same; the first port and the second port of the first differential signal transceiver module are respectively a drain electrode and a grid electrode of the third MOS tube; a first port and a second port of the second differential signal transceiver module are respectively a drain electrode and a grid electrode of the fourth MOS tube; and the third ports of the first differential signal transceiver module and the second differential signal transceiver module are respectively the source electrodes of the first MOS transistor and the second MOS transistor.
4. The latch unit of claim 3, wherein said first differential circuit comprises:
the second clock signal input module is used for inputting the first polarity clock signal;
and the first differential signal input module is respectively connected with the first ports of the first differential signal transceiver module and the second differential signal transceiver module, and the second clock signal input module and is used for inputting the differential input signal pair.
5. The latch unit of claim 4, wherein:
the second clock signal input module includes: a sixth MOS transistor and a seventh MOS transistor;
the first differential signal input module includes: an eighth MOS transistor and a ninth MOS transistor;
the sixth MOS tube and the seventh MOS tube share a common source and are connected with the second polarity interface;
the sixth MOS tube and the seventh MOS tube share a grid and are connected with the first polarity clock signal;
the drain of the sixth MOS transistor is connected to the source of the eighth MOS transistor, the drain of the eighth MOS transistor is connected to the first port of the first differential signal transceiver module, and the gate of the eighth MOS transistor is connected to the positive-phase input signal of the differential input signal pair;
the drain electrode of the seventh MOS transistor is connected to the source electrode of the ninth MOS transistor, the drain electrode of the ninth MOS transistor is connected to the first port of the second differential signal transceiver module, and the gate electrode of the ninth MOS transistor is connected to the negative-phase input signal in the differential input signal pair;
the channel types of the sixth MOS tube, the seventh MOS tube, the eighth MOS tube and the ninth MOS tube are the same and are opposite to the channel type of the first MOS tube.
6. The latch unit of claim 4, wherein:
the second clock signal input module includes: a sixth MOS transistor and a seventh MOS transistor;
the first differential signal input module includes: an eighth MOS transistor and a ninth MOS transistor;
the sixth MOS tube and the seventh MOS tube share a common source and are connected with the second polarity interface;
the grid electrode of the sixth MOS tube is connected to a positive phase input signal in the differential input signal pair;
the grid electrode of the seventh MOS tube is connected to a negative phase input signal in the differential input signal pair;
the drain electrode of the sixth MOS tube is connected with the source electrode of the eighth MOS tube, and the drain electrode of the eighth MOS tube is connected with the first port of the first differential signal transceiver module;
the drain electrode of the seventh MOS tube is connected with the source electrode of the ninth MOS tube, and the drain electrode of the ninth MOS tube is connected with the first port of the second differential signal transceiver module;
the eighth MOS transistor and the ninth MOS transistor share a grid and are connected with the first polarity clock signal;
the channel types of the sixth MOS tube, the seventh MOS tube, the eighth MOS tube and the ninth MOS tube are the same and are opposite to the channel type of the first MOS tube.
7. The latch unit of claim 5, wherein:
and the drain electrode of the sixth MOS tube is in short circuit with the drain electrode of the seventh MOS tube, and the source electrode of the eighth MOS tube is in short circuit with the source electrode of the ninth MOS tube.
8. A frequency divider, characterized in that it integrates a latch unit as claimed in any one of claims 1 to 7.
9. A latch cell, comprising:
a third differential circuit for inputting the first polarity clock signal and outputting a differential output signal pair;
a fourth differential circuit connected to the third differential circuit, for inputting a second polarity clock signal and inputting a differential input signal pair, and outputting the differential output signal pair simultaneously with the third differential circuit; the first polarity clock signal and the second polarity clock signal are a pair of inverted clock signals.
10. The latch unit of claim 9, wherein the fourth differential circuit comprises:
a third differential signal transceiver module, configured to input a positive-phase input signal in the differential input signal pair and output a negative-phase output signal in the differential output signal pair;
a fourth differential signal transceiver module, configured to input a negative-phase input signal in the differential input signal pair and output a positive-phase output signal in the differential output signal pair;
the first ports and the second ports of the third differential signal transceiver module and the fourth differential signal transceiver module are cross-connected with each other to output a negative phase output signal and a positive phase output signal in the differential output signal pair respectively;
and the third clock signal input module is respectively connected with the third ports of the third differential signal transceiver module and the fourth differential signal transceiver module and is used for inputting the second polarity clock signal.
11. The latch cell of claim 10, wherein:
the third differential signal transceiving module includes: the MOS transistor comprises a first MOS transistor and a third MOS transistor;
the fourth differential signal transceiving module includes: a second MOS tube and a fourth MOS tube;
the third clock signal input module includes: a fifth MOS transistor;
the first MOS tube and the third MOS tube share a drain electrode and are connected with a grid electrode of the fourth MOS tube;
the second MOS tube and the fourth MOS tube share a drain electrode and are connected with a grid electrode of the third MOS tube;
the third MOS tube and the fourth MOS tube share a common source and are connected with a first polarity interface;
the positive-phase input signal is input to the grid electrode of the first MOS tube, and the negative-phase input signal is input to the grid electrode of the second MOS tube;
the source electrodes of the first MOS tube and the second MOS tube are respectively connected with the drain electrode of the fifth MOS tube, the grid electrode of the fifth MOS tube inputs the second polarity clock signal, and the source electrode of the fifth MOS tube is connected with the first polarity interface;
the channel types of the first MOS tube, the third MOS tube, the second MOS tube, the fourth MOS tube and the fifth MOS tube are the same; a first port of the third differential signal transceiver module is a first junction of a first MOS transistor, a third MOS transistor and an eighth MOS transistor, and a second port of the third differential signal transceiver module is a gate of the third MOS transistor; a first port of the fourth differential signal transceiver module is a second junction of a second MOS transistor, a fourth MOS transistor and a ninth MOS transistor, and a second port of the fourth differential signal transceiver module is a gate of the fourth MOS transistor; and the third ports of the third differential signal transceiver module and the fourth differential signal transceiver module are respectively the source electrodes of the first MOS transistor and the second MOS transistor.
12. The latch unit of claim 11, wherein said third differential circuit comprises:
the fourth clock signal input module is used for inputting the first polarity clock signal;
and the second differential signal input module is connected with the fourth clock signal input module, is respectively and mutually cross-connected with the fourth ports of the third differential signal transceiver module and the fourth differential signal transceiver module, and is used for outputting the differential output signal pair.
13. The latch cell of claim 12, wherein:
the fourth clock signal input module includes: a sixth MOS transistor and a seventh MOS transistor;
the second differential signal input module includes: an eighth MOS transistor and a ninth MOS transistor;
the sixth MOS tube and the seventh MOS tube share a common source and are connected with the second polarity interface;
the sixth MOS tube and the seventh MOS tube share a grid and are connected with the first polarity clock signal;
the drain electrode of the sixth MOS tube is connected with the source electrode of the eighth MOS tube, and the drain electrode of the eighth MOS tube is connected with the first port of the third differential signal transceiver module;
the drain electrode of the seventh MOS transistor is connected to the source electrode of the ninth MOS transistor, and the drain electrode of the ninth MOS transistor is connected to the first port of the fourth differential signal transceiver module;
a gate of the eighth MOS transistor is connected to the first port of the third differential signal transceiver module to output a positive phase output signal of the differential output signal pair;
a grid electrode of the ninth MOS tube is connected with a first port of the fourth differential signal transceiver module so as to output a negative phase output signal in the differential output signal pair;
the channel types of the sixth MOS tube, the seventh MOS tube, the eighth MOS tube and the ninth MOS tube are the same and are opposite to the channel type of the first MOS tube.
14. The latch cell of claim 13, wherein:
and the drain electrode of the sixth MOS tube is in short circuit with the drain electrode of the seventh MOS tube, and the source electrode of the eighth MOS tube is in short circuit with the source electrode of the ninth MOS tube.
15. The latch cell of claim 12, wherein:
the fourth clock signal input module includes: a sixth MOS transistor and a seventh MOS transistor;
the second differential signal input module includes: an eighth MOS transistor and a ninth MOS transistor;
the sixth MOS tube and the seventh MOS tube share a common source and are connected with the second polarity interface;
the drain electrode of the sixth MOS tube is connected with the source electrode of the eighth MOS tube, and the drain electrode of the eighth MOS tube is connected with the first port of the third differential signal transceiver module;
the drain electrode of the seventh MOS transistor is connected to the source electrode of the ninth MOS transistor, and the drain electrode of the ninth MOS transistor is connected to the first port of the fourth differential signal transceiver module;
a grid electrode of the sixth MOS transistor is connected to the first port of the fourth differential signal transceiver module, and a grid electrode of the seventh MOS transistor is connected to the first port of the third differential signal transceiver module;
the grid electrodes of the eighth MOS tube and the ninth MOS tube are respectively connected to the first polarity clock signal;
the drain electrode of the eighth MOS transistor is connected to the first port of the third differential signal transceiver module to output a negative phase output signal of the differential output signal pair;
a drain electrode of the ninth MOS transistor is connected to the first port of the fourth differential signal transceiver module to output a positive phase output signal of the differential output signal pair;
the channel types of the sixth MOS tube, the seventh MOS tube, the eighth MOS tube and the ninth MOS tube are the same and are opposite to the channel type of the first MOS tube.
16. A frequency divider, characterized in that it integrates a latch unit as claimed in any one of claims 9 to 15.
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| CN202110345759.3A CN113098488A (en) | 2021-03-31 | 2021-03-31 | Latch unit and frequency divider |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330176A (en) * | 2015-06-26 | 2017-01-11 | 展讯通信（上海）有限公司 | Latch and frequency divider |
| CN106330177A (en) * | 2015-06-30 | 2017-01-11 | 展讯通信（上海）有限公司 | Latch |
| CN108242921A (en) * | 2016-12-27 | 2018-07-03 | 展讯通信（上海）有限公司 | Latch and frequency divider |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330176A (en) * | 2015-06-26 | 2017-01-11 | 展讯通信（上海）有限公司 | Latch and frequency divider |
| CN106330177A (en) * | 2015-06-30 | 2017-01-11 | 展讯通信（上海）有限公司 | Latch |
| CN108242921A (en) * | 2016-12-27 | 2018-07-03 | 展讯通信（上海）有限公司 | Latch and frequency divider |
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Application publication date: 20210709 |