CN106330176A - Latch and frequency divider - Google Patents
Latch and frequency divider Download PDFInfo
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- CN106330176A CN106330176A CN201510366173.XA CN201510366173A CN106330176A CN 106330176 A CN106330176 A CN 106330176A CN 201510366173 A CN201510366173 A CN 201510366173A CN 106330176 A CN106330176 A CN 106330176A
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Abstract
The invention provides a latch and a frequency divider. The latch comprises a first logic unit, a second logic unit, a first control unit, a second control unit, a third control unit and a fourth control unit. The first logic unit and the second logic unit are coupled between a power supply and a ground wire and are symmetrical. The first control unit, the first logic unit and the third control unit forms an access. The second control unit, the second logic unit and the fourth control unit forms an access. At least one of the control units is suitable for controlling an access between the power supply and the ground wire to be switched on or off. By use of the latch and the frequency divider, power consumption of a Wang-structured two-frequency divider can be effectively reduced.
Description
Technical field
The present invention relates to digital circuit field, particularly relate to a kind of latch and frequency divider.
Background technology
Along with developing rapidly of mobile communication technology, improve the speed of mobile communication terminal radio circuit, fall
The power consumption of low radio frequency circuit becomes the focus of existing mobile communication technology research.
Frequency-halving circuit as the basic module of frequency divider, is one of the Key Circuit of radio circuit.At a high speed
Two-divider circuit is made up of two stage latch circuit, and any of which latch circuit is another latch
The rear class unit of circuit.In conventional frequency divider circuit, latch circuit is driven by identical clock.And
In Wang structure divider circuit, latch circuit is to be driven by complementary clock signal.Relative to
Conventional frequency divider circuit, faster, power consumption is lower for Wang structure two-divider circuit speed.
But, inventor finds in research and practice process: for some reason, and existing Wang ties
Structure two-divider circuit power consumption is the biggest.
Summary of the invention
The problem that the embodiment of the present invention solves is how to reduce the power consumption of Wang structure two-divider circuit.
For solving the problems referred to above, the embodiment of the present invention provides a kind of latch, including: be coupled to power supply with
The first logical block between ground wire and the second logical block, and described first logical block and described the
Two logical unit structure are symmetrical；
Four control units, including: the first control unit, the second control unit, the 3rd control unit with
And the 4th control unit；Wherein:
Described first control unit, described first logical block and described 3rd control unit composition path；
Described second control unit, described second logical block and described 4th control unit composition path；Its
In at least one control unit, the path being suitable to control between power supply and the ground wire of place path disconnects or closes
Close.
Optionally, the outfan of described first control unit and the first outfan of described first logical block
Couple, at least one feedforward end and the input of described first logical block or described second logic list
The input of unit couples, and clock signal input terminal is suitable to input the first clock signal.
Optionally, the outfan of described second control unit and the first outfan of described second logical block
Couple, at least one feedforward end and the input of described second logical block or described first logic list
The input of unit couples, and clock signal input terminal is suitable to input second clock signal.
Optionally, the outfan of described 3rd control unit and the second outfan of described first logical block
Couple, at least one feedforward end and the input of described first logical block or described second logic list
The input of unit couples, and clock signal input terminal is suitable to input the 3rd clock signal.
Optionally, the outfan of described 4th control unit and the second outfan of described second logical block
Couple, at least one feedforward end and the input of described second logical block or described first logic list
The input of unit couples, and clock signal input terminal is suitable to input the 4th clock signal.
Optionally, at least one control unit in described four control units includes: be mutually coupled
One on-off control subelement and second switch control subelement.
Optionally, described first on-off control subelement includes transistor MC1, and described second switch controls
Subelement includes transistor MC2.
Optionally, described transistor MC1 is PMOS, and described transistor MC2 is PMOS,
Wherein:
The source electrode of described transistor MC1 couples with the drain electrode of described transistor MC2, and grid is clock letter
Number input, drains as outfan；
The source electrode of described transistor MC2 and supply coupling, grid is feedforward end.
Optionally, described transistor MC1 is PMOS, and described transistor MC2 is NMOS tube,
Wherein:
The source electrode of described transistor MC1 couples with the source electrode of described transistor MC2, and grid is clock letter
Number input, drains as outfan；
The drain electrode of described transistor MC2 and supply coupling, grid is feedforward end.
Optionally, described transistor MC1 is PMOS, and described transistor MC2 is PMOS,
Wherein:
The source electrode of described transistor MC1 and supply coupling, grid is clock signal input terminal, drain electrode and institute
The source electrode stating transistor MC2 couples；
The grid of described transistor MC2 is feedforward end, drains as outfan.
Optionally, described transistor MC1 is PMOS, and described transistor MC2 is NMOS tube,
Wherein:
The source electrode of described transistor MC1 and supply coupling, grid is clock signal input terminal, drain electrode and institute
The drain electrode stating transistor MC2 couples；
The grid of described transistor MC2 is feedforward end, and source electrode is outfan.
Optionally, described transistor MC1 is PMOS, and described transistor MC2 is PMOS,
Wherein:
The drain electrode coupling of the source electrode of described transistor MC1 and supply coupling, grid and described transistor MC2
Connect, drain as outfan；
The source electrode of described transistor MC2 is clock signal input terminal, and grid is feedforward end.
Optionally, described transistor MC1 is PMOS, and described transistor MC2 is NMOS tube,
Wherein:
The source electrode coupling of the source electrode of described transistor MC1 and supply coupling, grid and described transistor MC2
Connect, drain as outfan；
The drain electrode of described transistor MC2 is clock signal input terminal, and grid is feedforward end.
Optionally, described transistor MC1 is NMOS tube, and described transistor MC2 is NMOS tube,
Wherein:
The source electrode of described transistor MC1 couples with the drain electrode of described transistor MC2, and grid is clock letter
Number input, drains as outfan；
The source electrode of described transistor MC2 couples with ground wire, and grid is feedforward end.
Optionally, described transistor MC1 is NMOS tube, and described transistor MC2 is PMOS,
Wherein:
The source electrode of described transistor MC1 couples with the source electrode of described transistor MC2, and grid is clock letter
Number input, drains as outfan；
The drain electrode of described transistor MC2 couples with ground wire, and grid is feedforward end.
Optionally, described transistor MC1 is NMOS tube, and described transistor MC2 is NMOS tube,
Wherein:
The source electrode of described transistor MC1 couples with ground wire, and grid is clock signal input terminal, drain electrode and institute
The source electrode stating transistor MC2 couples；
The grid of described transistor MC2 is feedforward end, drains as outfan.
Optionally, described transistor MC1 is NMOS tube, and described transistor MC2 is PMOS,
Wherein:
The source electrode of described transistor MC1 couples with ground wire, and grid is clock signal input terminal, drain electrode and institute
The drain electrode stating transistor MC2 couples；
The grid of described transistor MC2 is feedforward end, drains as outfan.
Optionally, described transistor MC1 is NMOS tube, and described transistor MC2 is PMOS,
Wherein:
The source electrode of described transistor MC1 couples with ground wire, grid and the drain electrode coupling of described transistor MC2
Connect, drain as outfan；
The source electrode of described transistor MC2 is clock signal input terminal, and grid is feedforward end.
Optionally, described transistor MC1 is NMOS tube, and described transistor MC2 is NMOS tube,
Wherein:
The source electrode of described transistor MC1 couples with ground wire, grid and the source electrode coupling of described transistor MC2
Connect, drain as outfan；
The drain electrode of described transistor MC2 is clock signal input terminal, and grid is feedforward end.
Optionally, at least one control unit in described four control units includes: be mutually coupled
One on-off control subelement, second switch control subelement and the 3rd on-off control subelement.
Optionally, described first on-off control subelement includes transistor MC1, and described second switch controls
Subelement includes that transistor MC2, described 3rd on-off control subelement include transistor MC3.
Optionally, described transistor MC1, described transistor MC2 and described transistor MC3 are
PMOS, wherein:
The source electrode of described transistor MC1 couples with the drain electrode of described transistor MC2, and grid is clock letter
Number input, the source electrode with described transistor MC3 that drains couples；
The source electrode of described transistor MC2 and supply coupling, grid is the first feedforward end；
The grid of described transistor MC3 is the second feedforward end, drains as outfan.
Optionally, described transistor MC1 is PMOS, and described transistor MC2 is PMOS,
Described transistor MC3 is NMOS tube, wherein:
The source electrode of described transistor MC1 couples with the drain electrode of described transistor MC2, and grid is clock letter
Number input, the drain electrode with described transistor MC3 that drains couples；
The source electrode of described transistor MC2 and supply coupling, grid is the first feedforward end；
The grid of described transistor MC3 is the second feedforward end, and source electrode is outfan.
Optionally, described transistor MC1, described transistor MC2 and described transistor MC3 are
PMOS, wherein:
The drain electrode coupling of the source electrode of described transistor MC1 and supply coupling, grid and described transistor MC2
Connecing, the source electrode with described transistor MC2 that drains couples；
The source electrode of described transistor MC2 is clock signal input terminal, and grid is the first feedforward end；
The grid of described transistor MC3 is the second feedforward end, drains as outfan.
Optionally, described transistor MC1 is PMOS, and described transistor MC2 is NMOS tube,
Described transistor MC3 is NMOS tube, wherein:
The source electrode of described transistor MC1 couples with the source electrode of described transistor MC2, grid and described crystalline substance
The source electrode of body pipe MC2 couples, and drains as outfan；
The grid of described transistor MC2 is the first feedforward end, drains as clock signal input terminal；
The grid of described transistor MC3 is the second feedforward end, drain electrode and supply coupling.
The embodiment of the present invention additionally provides a kind of frequency divider, including the latch described in two any of the above-described kind,
Wherein, first input end and second input of the arbitrary latch in described latch is locked with another respectively
First outfan and second outfan of storage couple.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantage that
By at least one control unit in four control units, control power supply and the ground wire of place path
Between current path disconnect, such that it is able to reduce latch under the conditions of static work because of exist power supply with
Path between ground wire and the power consumption that causes, owing to Wang structure two-divider circuit is by latch circuit group
Becoming, therefore while latch lower power consumption, the power consumption of Wang structure two-divider circuit drops significantly
Low.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing a kind of high speed two-divider circuit；
Fig. 2 be existing a kind of output duty cycle be the circuit structure diagram of the latch of 50%；
Fig. 3 be existing another kind of output duty cycle be the circuit structure diagram of the latch of 50%；
Fig. 4 is the structural representation of a kind of latch in the embodiment of the present invention；
Fig. 5～Figure 20 is the multiple circuit structure diagram of the control unit in the embodiment of the present invention；
Figure 21 is the circuit structure diagram of a kind of latch in the embodiment of the present invention；
Figure 22 is the circuit structure diagram of the another kind of latch in the embodiment of the present invention；
Figure 23 is the circuit structure diagram of another latch in the embodiment of the present invention；
Figure 24 is the circuit structure diagram of the another kind of latch in the embodiment of the present invention.
Detailed description of the invention
With reference to Fig. 1, give the structural representation of a kind of high speed two-divider circuit of the prior art, bag
Include latch 101 and 102.
Latch 101 and latch 102 are d type flip flop, D end and Dn end and are input, Q
End and Qn end are outfan.The clock signal input terminal CLK input clock signal CK of latch 101,
The clock signal input terminal CLK input clock signal CKb of latch 102, and clock signal CK and time
Signal CKb is anti-phase for clock.
The D end of latch 101 couples with the Qn end of latch 102, Q end and the D of latch 102
End couples, and Dn end couples with the Q end of latch 102, and Qn end couples with the Dn end of latch 102.
That is: the input of latch 101 is respectively coupled to the outfan of latch 102, latch 101 defeated
Go out and hold the input with latch 102 to be respectively coupled to, latch 101 and latch 102 front stage each other.
With reference to Fig. 2, give the Wang structure two-divider electricity that existing a kind of output duty cycle is 50%
The circuit structure diagram of the latch in road.
First control unit 203 is coupled between power supply VREF_1 and the first logical block 201, and the 3rd
Control unit 205 is coupled between the first logical block 201 and ground wire VREF_2；Second control unit
204 are coupled between power supply VREF_1 and the second logical block 202, and the 4th control unit 206 is coupled to
Between second logical block 202 and ground wire VREF_2.
First logical block 201 includes third transistor M3 and the 5th transistor M5, the second logical block
202 include the 4th transistor M4 and the 6th transistor M6, and third transistor M3, the 5th transistor
M5, the 4th transistor M4 and the 6th transistor M6 are NMOS tube.Wherein:
Third transistor M3, the drain electrode with the 5th transistor M5 that drains couples, as the first logical block
First outfan of 201；The drain electrode of grid and the 4th transistor M4 couples；Source electrode and the 5th transistor
The source electrode of M5 couples, and couples with the 3rd control unit 205；
5th transistor M5, grid is the input of the first logical block 201；
4th transistor M4, the drain electrode with the 6th transistor M6 that drains couples, as the second logical block
First outfan of 202；Grid couples with the drain electrode of third transistor M3；Source electrode and the 4th transistor
The source electrode of M4 couples, and couples with the 4th control unit 206；
6th transistor M6, grid is the input of the second logical block 202.
First control unit 203 includes that the first transistor M1, the first transistor M1 are PMOS, source
Pole couples with power supply VREF_1, and grid is clock signal input terminal CLK, is suitable to input clock signal,
The drain electrode with third transistor M3 that drains couples.
Second control unit 204 includes that transistor seconds M2, transistor seconds M2 are PMOS, source
Pole couples with power supply VREF_1, and grid is clock signal input terminal CLK, is suitable to input clock signal,
The drain electrode with the 4th transistor M4 that drains couples.
3rd control unit 205 includes the 7th transistor M7, and the 7th transistor M7 is NMOS tube,
Source electrode couples with ground wire VREF_2, and grid is clock signal input terminal CLKB, is suitable to input clock letter
Number, the source electrode with the 5th transistor M5 that drains couples.
4th control unit 206 includes the 8th transistor M8, and the 8th transistor M8 is NMOS tube,
Source electrode couples with ground wire VREF_2, and grid is clock signal input terminal CLKB, is suitable to input clock letter
Number, the source electrode with the 6th transistor M6 that drains couples.Clock signal clk B is mutual with clock signal clk
For inversion signal.
When the grid equal input low level signal of grid and the transistor seconds M2 of the first transistor M1,
The first transistor M1 and transistor seconds M2 turns on.Grid and the 8th crystal as the 7th transistor M7
During the grid equal input high level signal of pipe M8, the 7th transistor M7 and the 8th transistor M8 conducting.
When the input D input high level signal of the first logical block 201, the second logical block 202
During input Dn input low level signal, latch circuit exist VREF_1, the first transistor M1,
Third transistor M3 to VREF_2 and VREF_1, the first transistor M1, the 5th transistor M5,
The DC channel of the 7th transistor M7 to VREF_2, therefore, the latch circuit provided in Fig. 2 is deposited
At DC power.
With reference to Fig. 3, give the Wang structure two-divider that existing another kind of output duty cycle is 50%
The circuit structure diagram of the latch in circuit.
3rd control unit 205 is coupled between power supply VREF_1 and the first logical block 201, and first
Control unit 203 is coupled between the first logical block 201 and ground wire VREF_2；4th control unit
206 are coupled between power supply VREF_1 and the second logical block 202, and the second control unit 204 is coupled to
Between second logical block 202 and ground wire VREF_2.
First logical block 201 includes third transistor M3 and the 5th transistor M5, the second logical block
202 include the 4th transistor M4 and the 6th transistor M6, and third transistor M3, the 5th transistor
M5, the 4th transistor M4 and the 6th transistor M6 are PMOS.Wherein:
Third transistor M3, the drain electrode with the 5th transistor M5 that drains couples, as the first logical block
First outfan of 201；The drain electrode of grid and the 4th transistor M4 couples；Source electrode and the 5th transistor
The source electrode of M5 couples, and couples with the 3rd control unit 205；
5th transistor M5, grid is the input of the first logical block 201；
4th transistor M4, the drain electrode with the 6th transistor M6 that drains couples, as the second logical block
First outfan of 202；Grid couples with the drain electrode of third transistor M3；Source electrode and the 4th transistor
The source electrode of M4 couples, and couples with the 4th control unit 206；
6th transistor M6, grid is the input of the second logical block 202.
First control unit 203 includes that the first transistor M1, the first transistor M1 are NMOS tube,
Source electrode couples with ground wire VREF_2, and grid is clock signal input terminal CLK, is suitable to input clock signal,
The drain electrode with third transistor M3 that drains couples.
Second control unit 204 includes that transistor seconds M2, transistor seconds M2 are NMOS tube,
Source electrode couples with ground wire VREF_2, and grid is clock signal input terminal CLK, is suitable to input clock signal,
The drain electrode with the 4th transistor M4 that drains couples.
3rd control unit 205 includes the 7th transistor M7, and the 7th transistor M7 is PMOS, source
Pole couples with power supply VREF_1, and grid is clock signal input terminal CLKB, is suitable to input clock signal,
The source electrode with the 5th transistor M5 that drains couples.
4th control unit 206 includes the 8th transistor M8, and the 8th transistor M8 is PMOS, source
Pole couples with power supply VREF_1, and grid is clock signal input terminal CLKB, is suitable to input clock signal,
The source electrode with the 6th transistor M6 that drains couples.
When the grid equal input low level signal of the grid of the 7th transistor M7 and the 8th transistor M8,
7th transistor M7 and the 8th transistor M8 conducting.Grid and the second crystal as the first transistor M1
During the grid equal input high level signal of pipe M2, the first transistor M1 and transistor seconds M2 turns on.
When the input D input low level signal of the first logical block 201, the second logical block 202
During input Dn input high level signal, latch circuit exist VREF_1, the 7th transistor M7,
5th transistor M5, the DC channel of the first transistor M1 to VREF_2, therefore, provide in Fig. 3
Latch circuit there is also DC power.
In embodiments of the present invention, by least one control unit in four control units, control institute
Current path between the power supply VREF_1 and ground wire VREF_2 of path disconnects, such that it is able to reduce
Latch under the conditions of static work because there is the path between power supply VREF_1 and ground wire VREF_2 and
The power consumption caused, owing to Wang structure two-divider circuit is made up of latch circuit, therefore at latch
While lower power consumption, the power consumption of Wang structure two-divider circuit is substantially reduced.
Understandable for enabling the above-mentioned purpose of the embodiment of the present invention, feature and advantage to become apparent from, knot below
Close accompanying drawing the specific embodiment of the present invention is described in detail.
With reference to Fig. 4, give the structural representation of a kind of latch in the embodiment of the present invention, including: the
One logical block the 401, second logical block the 402, first control unit the 403, second control unit 404,
3rd control unit 405 and the 4th control unit 406, wherein:
First logical block 401 and the second logical block 402 are coupled to power supply VREF_1 and ground wire
Between VREF_2, and the first logical block 401 and the second logical block 402 symmetrical configuration.First logic
The first logical block 201 that the concrete structure of unit 401 and the second logical block 402 is referred in Fig. 2
And second logical block 202, do not repeat.
First control unit the 403, first logical block 401 and the 3rd control unit 405 form first and lead to
Road, is coupled between power supply and ground wire；Second control unit the 404, second logical block 402 and the 4th
Control unit 406 forms alternate path, is coupled between power supply and ground wire.In four control units extremely
A few control unit, the path being suitable to control between power supply and the ground wire of place path is opened or closed.
In being embodied as, each control unit may each comprise outfan, clock signal input terminal with
And at least one feedforward end.
In embodiments of the present invention, the outfan and the first of the first logical block of the first control unit 403
Outfan couples；At least one feedforward end and the input of the first logical block or the second logical block
Input couple, clock signal input terminal is suitable to input the first clock signal.
In embodiments of the present invention, the outfan and the first of the second logical block of the second control unit 404
Outfan couples, at least one feedforward end and the input of the second logical block or the first logical block
Input couple, clock signal input terminal be suitable to input second clock signal.
In embodiments of the present invention, the outfan and the second of the first logical block of the 3rd control unit 405
Outfan couples, at least one feedforward end and the input of the first logical block or the second logical block
Input couple, clock signal input terminal is suitable to input the 3rd clock signal.
In embodiments of the present invention, the outfan and the second of the second logical block of the 4th control unit 406
Outfan couples, at least one feedforward end and the input of the second logical block or the first logical block
Input couple, clock signal input terminal is suitable to input the 4th clock signal.
In embodiments of the present invention, the first path can be controlled by the first control unit 403 and disconnect, from
And make the current path disconnection of power supply, the first path to ground wire.The second control unit 404 can also be passed through
Control alternate path to disconnect so that the current path between power supply, alternate path to ground wire disconnects.Also may be used
To control the first path disconnection by the 3rd control unit 405, or controlled by the 4th control unit 406
Alternate path processed disconnects, so that the path between power supply and ground wire disconnects.Can also be simultaneously by four
Any two or more in individual control unit, controls the electricity between place path and power supply and ground wire
Circulation flow path disconnects, and repeats the most one by one.
As can be seen here, by least one control unit in four control units, place path is controlled
Current path between power supply and ground wire disconnects, such that it is able to reduce latch under the conditions of static work because of
The power consumption that there is the path between power supply and ground wire and cause, owing to Wang structure two-divider circuit is by locking
Latch circuit forms, therefore while latch lower power consumption, and the merit of Wang structure two-divider circuit
Consumption is substantially reduced.
In embodiments of the present invention, at least one control unit in four control units can include mutually
The the first on-off control subelement coupled and second switch control subelement, it is also possible to include being mutually coupled
First on-off control subelement, second switch control subelement and the 3rd on-off control subelement.Wherein:
First on-off control subelement can include that transistor MC1, second switch unit can include transistor
MC2, the 3rd switch element can include transistor MC3.
When control unit includes that the first on-off control subelement controls subelement with second switch, this control
Unit includes a feedforward end, an outfan and a clock signal input terminal.Single when controlling
Unit includes that the first on-off control subelement, second switch control subelement and the 3rd on-off control subelement
Time, this control unit includes an outfan, a clock signal input terminal and two feedforward ends,
And two feedforward ends are respectively the first feedforward end and the second feedforward end.
Below in conjunction with Fig. 2, the structure of the control unit in the latch provide the above embodiment of the present invention is entered
Row describes in detail.
With reference to Fig. 5～Figure 16, give the structural representation of several control units in the embodiment of the present invention.
Control unit includes that the first on-off control subelement and second switch control subelement, the first on-off control
Unit includes transistor MC1, and second switch controls subelement and includes transistor MC2.
With reference to Fig. 5, give the structural representation of a kind of control unit in the embodiment of the present invention, control single
In unit, transistor MC1 is PMOS, and transistor MC2 is PMOS, wherein:
The source electrode of transistor MC1 couples with the drain electrode of transistor MC2, and grid is clock signal input terminal,
Drain electrode is outfan；The source electrode of transistor MC2 couples with power supply VREF_1, and grid is control unit
Feedforward end.
In embodiments of the present invention, clock signal input terminal is suitable to input the clock letter corresponding with control unit
Number.Feedforward end can couple with the input of the logical block on the path of control unit place, it is possible to
Couple with the input with the logical block on another path.
Such as, control unit is the first control unit 403, then when the grid of transistor MC1 inputs first
Clock signal.Feedforward end can couple with the first logical block on the first path, it is also possible to second
The second logical block on path couples.
In embodiments of the present invention, from the characteristic of transistor, the grid at transistor MC2 inputs electricity
When putting down as low level, transistor MC2 turns on.Grid incoming level at transistor MC2 is high level
Time, transistor MC2 ends.
With reference to Fig. 6, give the structural representation of another kind of control unit in the embodiment of the present invention, control
Transistor MC1 in unit is PMOS, and transistor MC2 is NMOS tube, wherein:
The source electrode of transistor MC1 couples with the source electrode of transistor MC2, and grid is clock signal input terminal,
Drain electrode is outfan；The drain electrode of transistor MC2 couples with power supply VREF_1, and grid is feedforward end.
In embodiments of the present invention, from the characteristic of transistor, the grid at transistor MC2 inputs electricity
When putting down as low level, transistor MC2 ends.Grid incoming level at transistor MC2 is high level
Time, transistor MC2 turns on.
With reference to Fig. 7, give the structural representation of another control unit in the embodiment of the present invention, control
Transistor MC1 in unit is PMOS, and transistor MC2 is PMOS, wherein:
The source electrode of transistor MC1 couples with power supply VREF_1, and grid is clock signal input terminal, drain electrode
Couple with the source electrode of transistor MC2；The grid of transistor MC2 is feedforward end, drains as output
End.
In embodiments of the present invention, from the characteristic of transistor, the grid at transistor MC2 inputs electricity
When putting down as low level, transistor MC2 turns on.Grid incoming level at transistor MC2 is high level
Time, transistor MC2 ends.
With reference to Fig. 8, give the structural representation of another control unit in the embodiment of the present invention, control
Transistor MC1 in unit is PMOS, and transistor MC2 is NMOS tube, wherein:
The source electrode of transistor MC1 couples with power supply VREF_1, and grid is clock signal input terminal, drain electrode
Drain electrode with transistor MC2 couples；The grid of transistor MC2 is feedforward end, and source electrode is output
End.
In embodiments of the present invention, from the characteristic of transistor, the grid at transistor MC2 inputs electricity
When putting down as low level, transistor MC2 ends.Grid incoming level at transistor MC2 is high level
Time, transistor MC2 turns on.
With reference to Fig. 9, give the structural representation of another control unit in the embodiment of the present invention, control
Transistor MC1 in unit is PMOS, and transistor MC2 is PMOS, wherein:
The source electrode of transistor MC1 couples with power supply VREF_1, grid and the drain electrode coupling of transistor MC2
Connect, drain as outfan；The source electrode of transistor MC2 is clock signal input terminal, and grid is the feedforward
End.
With reference to Figure 10, give the structural representation of another control unit in the embodiment of the present invention, control
Transistor MC1 in unit processed is PMOS, and transistor MC2 is NMOS tube, wherein:
The source electrode of transistor MC1 couples with power supply VREF_1, grid and the source electrode coupling of transistor MC2
Connect, drain as outfan；The drain electrode of transistor MC2 is clock signal input terminal, and grid is the feedforward
End.
With reference to Figure 11, give the structural representation of another control unit in the embodiment of the present invention, control
Transistor MC1 in unit processed is NMOS tube, and transistor MC2 is NMOS tube, wherein:
The source electrode of transistor MC1 couples with the drain electrode of transistor MC2, and grid is clock signal input terminal,
Drain electrode is outfan；The source electrode of transistor MC2 couples with ground wire VREF_2, and grid is feedforward end.
With reference to Figure 12, give the structural representation of another control unit in the embodiment of the present invention, control
Transistor MC1 in unit processed is NMOS tube, and transistor MC2 is PMOS, wherein:
The source electrode of transistor MC1 couples with the source electrode of transistor MC2, and grid is clock signal input terminal,
Drain electrode is outfan；The drain electrode of transistor MC2 couples with ground wire VREF_2, and grid is feedforward end.
With reference to Figure 13, give the structural representation of another control unit in the embodiment of the present invention, control
Transistor MC1 in unit processed is NMOS tube, and transistor MC2 is NMOS tube, wherein:
The source electrode of transistor MC1 couples with ground wire VREF_2, and grid is clock signal input terminal, drain electrode
Couple with the source electrode of transistor MC2；The grid of transistor MC2 is feedforward end, drains as output
End.
With reference to Figure 14, give the structural representation of another control unit in the embodiment of the present invention, control
Transistor MC1 in unit processed is NMOS tube, and transistor MC2 is PMOS, wherein:
The source electrode of transistor MC1 couples with ground wire VREF_2, and grid is clock signal input terminal, drain electrode
Drain electrode with transistor MC2 couples；The grid of transistor MC2 is feedforward end, drains as output
End.
With reference to Figure 15, give the structural representation of another control unit in the embodiment of the present invention, control
Transistor MC1 in unit processed is NMOS tube, and transistor MC2 is PMOS, wherein:
The source electrode of transistor MC1 couples with ground wire VREF_2, grid and the drain electrode coupling of transistor MC2
Connect, drain as outfan；The source electrode of transistor MC2 is clock signal input terminal, and grid is the feedforward
End.
With reference to Figure 16, give the structural representation of another control unit in the embodiment of the present invention, control
Transistor MC1 in unit processed is NMOS tube, and transistor MC2 is NMOS tube, wherein:
The source electrode of transistor MC1 couples with ground wire VREF_2, grid and the source electrode coupling of transistor MC2
Connect, drain as outfan；The drain electrode of transistor MC2 is clock signal input terminal, and grid is the feedforward
End.
With reference to Figure 17～Figure 20, give the structural representation of several control units in the embodiment of the present invention.
The first on-off control subelement that control unit includes being mutually coupled, second switch control subelement and the
Three on-off control subelements.Wherein: the first on-off control subelement includes transistor MC1, second switch
Control subelement and include that transistor MC2, the 3rd on-off control subelement include transistor MC3.
With reference to Figure 17, give the structural representation of a kind of control unit in the embodiment of the present invention, control
Transistor MC1 in unit, described transistor MC2 and described transistor MC3 are PMOS,
Wherein:
The source electrode of transistor MC1 couples with the drain electrode of described transistor MC2, and grid is that clock signal is defeated
Entering end, the source electrode with transistor MC3 that drains couples；
The source electrode of transistor MC2 couples with power supply VREF_1, and grid is the first feedforward end；
The grid of transistor MC3 is the second feedforward end, drains as outfan.
When the grid input high level signal of transistor MC2, transistor MC2 ends.Work as transistor
During the grid input high level signal of MC3, transistor MC3 ends.
With reference to Figure 18, give the structural representation of another kind of control unit in the embodiment of the present invention, brilliant
Body pipe MC1 is PMOS, and transistor MC2 is PMOS, and transistor MC3 is NMOS tube,
Wherein:
The source electrode of transistor MC1 couples with the drain electrode of transistor MC2, and grid is clock signal input terminal,
The drain electrode with transistor MC3 that drains couples；
The source electrode of transistor MC2 couples with power supply VREF_1, and grid is the first feedforward end；
The grid of transistor MC3 is the second feedforward end, and source electrode is outfan.
With reference to Figure 19, give the structural representation of another kind of control unit in the embodiment of the present invention, brilliant
Body pipe MC1, described transistor MC2 and described transistor MC3 are PMOS, wherein:
The source electrode of transistor MC1 couples with power supply VREF_1, grid and the drain electrode coupling of transistor MC2
Connecing, the source electrode with transistor MC2 that drains couples；
The source electrode of transistor MC2 is clock signal input terminal, and grid is the first feedforward end；
The grid of transistor MC3 is the second feedforward end, drains as outfan.
With reference to Figure 20, give the structural representation of another kind of control unit in the embodiment of the present invention, institute
Stating transistor MC1 is PMOS, and described transistor MC2 is NMOS tube, described transistor MC3
For NMOS tube, wherein:
The source electrode of transistor MC1 couples with the source electrode of transistor MC2, grid and the source of transistor MC2
Pole couples, and drains as outfan；
The grid of transistor MC2 is the first feedforward end, drains as clock signal input terminal；
The grid of transistor MC3 is the second feedforward end, and drain electrode couples with power supply VREF_1.
It is understood that in embodiments of the present invention, first controls switch subelement, second switch
Unit and the 3rd controls switch subelement can also be capable of the device of switching function for other, not
PMOS or the NMOS tube provided is provided in above-described embodiment.
In embodiments of the present invention, it is to be understood that at least one in four control units controls single
The circuit structure diagram of unit can be arbitrary shown in Fig. 5～Figure 20.
Such as, in Fig. 2, the circuit structure diagram of the first control unit 203 is shown in Figure 16, and second controls list
The circuit structure diagram of unit 204 is shown in Figure 18, and the circuit structure diagram of the 3rd control unit 205 is Figure 15
Shown in, the 4th circuit structure diagram controlling control unit 206 is shown in Figure 14.Can answer according to actual
By scene and demand, therefrom select the circuit structure diagram of the control unit of correspondence.
In an embodiment of the present invention, by the first control unit 203 electricity provided in Fig. 7 in Fig. 2
Line structure substitutes, and obtains Figure 21, wherein: transistor MC1 is the first transistor M1, transistor MC2
It is the 9th transistor M9.
Below the operation principle of the latch provided in Figure 21 is illustrated.
The first transistor M1 and transistor seconds M2 is PMOS, at the grid of the first transistor M1
During the grid equal input low level clock signal of pole and transistor seconds M2, the first transistor M1 and
Transistor seconds M2 turns on.7th transistor M7 and the 8th transistor M8 is NMOS tube,
During the murderous intention input high level clock signal of the grid of the 7th transistor M7 and the 8th transistor M8,
Seven transistor M7 and the 8th transistor M8 conducting.
When the input D input high level signal of the first logical block 201, the second logical block 202
During input Dn input low level signal, the grid of the 9th transistor M9 is high level, and now the 9th is brilliant
Body pipe ends.Therefore, the first control unit of the first transistor M1 and the 9th transistor M9 composition
203 open circuits, so that power supply VREF_1, the first transistor M1, the 9th transistor M9, trimorphism
Body pipe M3, the 5th transistor M5, the current path of the 7th transistor M7 to ground wire VREF_2 disconnect,
Such that it is able to reduce the DC power of latch, therefore decrease the power consumption of Wang structure frequency divider.
In an embodiment of the present invention, by the first control unit 203 and the second control unit in Fig. 2
204 all substitute with the circuit structure provided in Fig. 7, obtain Figure 22, wherein: the first control unit 203
In, transistor MC1 is the first transistor M1, and transistor MC2 is the 9th transistor M9；Second control
In unit 204 processed, transistor MC1 is transistor seconds M2, and transistor MC2 is the tenth transistor
M10。
The principle similar with Figure 21, when the input D input high level signal of the first logical block 201,
During the input Dn input low level signal of the second logical block 202, the grid of the 9th transistor M9 is
High level, now the 9th transistor M9 cut-off.Therefore, the first transistor M1 and the 9th transistor
M9 composition the first control unit 203 open circuit so that power supply VREF_1, the first transistor M1,
9th transistor M9, third transistor M3, the 5th transistor M5, the 7th transistor M7 are to ground wire
The current path of VREF_2 disconnects；
When the input D input low level signal of the first logical block 201, the second logical block 202
During input Dn input high level signal, the grid of the tenth transistor M10 is high level, the tenth crystal
Pipe M10 ends.Therefore, the second control of transistor seconds M2 and the tenth transistor M10 composition is single
Unit's 204 open circuits so that power supply VREF_1, transistor seconds M2, the tenth transistor M10, the
Four transistor M4, the 6th transistor M6, the current path of the 8th transistor M8 to ground wire VREF_2
Disconnect.Therefore, use above-mentioned latch can reduce DC power, therefore decrease Wang structure frequency dividing
The power consumption of device.
In an embodiment of the present invention, by the first control unit 203 electricity provided in Figure 17 in Fig. 2
Line structure substitutes, and obtains Figure 23, wherein: transistor MC1 is the first transistor M1, transistor MC2
Being the 9th transistor M9, transistor MC3 is the 11st transistor M11.
When the input D input high level of the first logical block 201, the 9th transistor M9 and the tenth
One transistor M11 cut-off, so that power supply VREF_1, first control unit the 203, first logic
The current path of unit the 201, the 3rd control unit 205 to bottom line VREF_2 disconnects, such that it is able to reduce
The DC power of latch, therefore decreases the power consumption of Wang structure frequency divider.
In an embodiment of the present invention, by the first control unit 203 and the second control unit in Fig. 3
204 all substitute with the circuit structure provided in Figure 11, obtain Figure 24, wherein: the first control unit 203
In, transistor MC1 is the first transistor M1, and transistor MC2 is the 9th transistor M9；Second control
In unit 204 processed, transistor MC1 is transistor seconds M2, and transistor MC2 is the tenth transistor
M10。
When the input D input low level signal of the first logical block 201, the second logical block 202
During input Dn input high level signal, the grid of the 9th transistor M9 is low level, and now the 9th is brilliant
Body pipe M9 ends.Therefore, the first control of the first transistor M1 and the 9th transistor M9 composition is single
Unit's 203 open circuits so that power supply VREF_1, the first transistor M1, the 9th transistor M9, the
Three transistor M3, the 5th transistor M5, the current path of the 7th transistor M7 to ground wire VREF_2
Disconnect；
When the input D input high level signal of the first logical block 201, the second logical block 202
During input Dn input low level signal, the grid of the tenth transistor M10 is low level, the tenth crystal
Pipe M10 ends.Therefore, the second control of transistor seconds M2 and the tenth transistor M10 composition is single
Unit's 204 open circuits so that power supply VREF_1, transistor seconds M2, the tenth transistor M10, the
Four transistor M4, the 6th transistor M6, the current path of the 8th transistor M8 to ground wire VREF_2
Disconnect.Therefore, use above-mentioned latch can reduce DC power, therefore decrease Wang structure frequency dividing
The power consumption of device.
In embodiments of the present invention, it is to be understood that the first control unit 203, second in Fig. 2 is controlled
Unit 204 processed all can use any one structure in Fig. 5～Figure 10, Figure 17～Figure 20 to substitute, and the 3rd controls
Unit 205 and the 4th control unit 206 all can substitute by any one structure in Figure 11～Figure 16；
First control unit the 203, second control unit 204 in Fig. 3 all can be with appointing in Figure 11～Figure 16
A kind of structure substitutes, the 3rd control unit 205 and the 4th control unit 206 all can use Fig. 5～Figure 10,
Any one structure in Figure 17～Figure 20 substitutes.The operation principle of the latch circuit obtained is referred to this
The operation principle provided in invention above-described embodiment, does not repeats.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (26)
1. a latch, it is characterised in that including: the first logical block being coupled between power supply and ground wire
And second logical block, and described first logical block is symmetrical with described second logical unit structure；
Four control units, including: the first control unit, the second control unit, the 3rd control unit and
Four control units；Wherein: described first control unit, described first logical block and described 3rd control
Unit processed composition path；Described second control unit, described second logical block and the described 4th control
Unit composition path；At least one of which control unit, be suitable to the power supply controlling place path and ground wire it
Between path be opened or closed.
2. latch as claimed in claim 1, it is characterised in that the outfan of described first control unit with
First outfan of described first logical block couples, at least one feedforward end and described first logic
The input of unit or the input of described second logical block couple, and clock signal input terminal is suitable to input
First clock signal.
3. latch as claimed in claim 1, it is characterised in that the outfan of described second control unit with
First outfan of described second logical block couples, at least one feedforward end and described second logic
The input of unit or the input of described first logical block couple, and clock signal input terminal is suitable to input
Second clock signal.
4. latch as claimed in claim 1, it is characterised in that the outfan of described 3rd control unit with
Second outfan of described first logical block couples, at least one feedforward end and described first logic
The input of unit or the input of described second logical block couple, and clock signal input terminal is suitable to input
3rd clock signal.
5. latch as claimed in claim 1, it is characterised in that the outfan of described 4th control unit with
Second outfan of described second logical block couples, at least one feedforward end and described second logic
The input of unit or the input of described first logical block couple, and clock signal input terminal is suitable to input
4th clock signal.
6. the latch as described in any one of claim 1-5, it is characterised in that in described four control units
At least one control unit include: the first on-off control subelement being mutually coupled and second switch control
Subelement.
7. latch as claimed in claim 6, it is characterised in that described first on-off control subelement includes
Transistor MC1, described second switch controls subelement and includes transistor MC2.
8. latch as claimed in claim 7, it is characterised in that described transistor MC1 is PMOS,
Described transistor MC2 is PMOS, wherein:
The source electrode of described transistor MC1 couples with the drain electrode of described transistor MC2, and grid is that clock signal is defeated
Enter end, drain as outfan；
The source electrode of described transistor MC2 and supply coupling, grid is feedforward end.
9. latch as claimed in claim 7, it is characterised in that described transistor MC1 is PMOS,
Described transistor MC2 is NMOS tube, wherein:
The source electrode of described transistor MC1 couples with the source electrode of described transistor MC2, and grid is that clock signal is defeated
Enter end, drain as outfan；
The drain electrode of described transistor MC2 and supply coupling, grid is feedforward end.
10. latch as claimed in claim 7, it is characterised in that described transistor MC1 is PMOS,
Described transistor MC2 is PMOS, wherein:
The source electrode of described transistor MC1 and supply coupling, grid is clock signal input terminal, drain electrode and described crystalline substance
The source electrode of body pipe MC2 couples；
The grid of described transistor MC2 is feedforward end, drains as outfan.
11. latch as claimed in claim 7, it is characterised in that described transistor MC1 is PMOS,
Described transistor MC2 is NMOS tube, wherein:
The source electrode of described transistor MC1 and supply coupling, grid is clock signal input terminal, drain electrode and described crystalline substance
The drain electrode of body pipe MC2 couples；
The grid of described transistor MC2 is feedforward end, and source electrode is outfan.
12. latch as claimed in claim 7, it is characterised in that described transistor MC1 is PMOS,
Described transistor MC2 is PMOS, wherein:
The source electrode of described transistor MC1 and supply coupling, grid couples with the drain electrode of described transistor MC2,
Drain electrode is outfan；
The source electrode of described transistor MC2 is clock signal input terminal, and grid is feedforward end.
13. latch as claimed in claim 7, it is characterised in that described transistor MC1 is PMOS,
Described transistor MC2 is NMOS tube, wherein:
The source electrode of described transistor MC1 and supply coupling, grid couples with the source electrode of described transistor MC2,
Drain electrode is outfan；
The drain electrode of described transistor MC2 is clock signal input terminal, and grid is feedforward end.
14. latch as claimed in claim 7, it is characterised in that described transistor MC1 is NMOS tube,
Described transistor MC2 is NMOS tube, wherein:
The source electrode of described transistor MC1 couples with the drain electrode of described transistor MC2, and grid is that clock signal is defeated
Enter end, drain as outfan；
The source electrode of described transistor MC2 couples with ground wire, and grid is feedforward end.
15. latch as claimed in claim 7, it is characterised in that described transistor MC1 is NMOS tube,
Described transistor MC2 is PMOS, wherein:
The source electrode of described transistor MC1 couples with the source electrode of described transistor MC2, and grid is that clock signal is defeated
Enter end, drain as outfan；
The drain electrode of described transistor MC2 couples with ground wire, and grid is feedforward end.
16. latch as claimed in claim 7, it is characterised in that described transistor MC1 is NMOS tube,
Described transistor MC2 is NMOS tube, wherein:
The source electrode of described transistor MC1 couples with ground wire, and grid is clock signal input terminal, drain electrode and described crystalline substance
The source electrode of body pipe MC2 couples；
The grid of described transistor MC2 is feedforward end, drains as outfan.
17. latch as claimed in claim 7, it is characterised in that described transistor MC1 is NMOS tube,
Described transistor MC2 is PMOS, wherein:
The source electrode of described transistor MC1 couples with ground wire, and grid is clock signal input terminal, drain electrode and described crystalline substance
The drain electrode of body pipe MC2 couples；
The grid of described transistor MC2 is feedforward end, drains as outfan.
18. latch as claimed in claim 7, it is characterised in that described transistor MC1 is NMOS tube,
Described transistor MC2 is PMOS, wherein:
The source electrode of described transistor MC1 couples with ground wire, and grid couples with the drain electrode of described transistor MC2,
Drain electrode is outfan；
The source electrode of described transistor MC2 is clock signal input terminal, and grid is feedforward end.
19. latch as claimed in claim 7, it is characterised in that described transistor MC1 is NMOS tube,
Described transistor MC2 is NMOS tube, wherein:
The source electrode of described transistor MC1 couples with ground wire, and grid couples with the source electrode of described transistor MC2,
Drain electrode is outfan；
The drain electrode of described transistor MC2 is clock signal input terminal, and grid is feedforward end.
20. latch as described in any one of claim 1-5, it is characterised in that in described four control units
At least one control unit include: the first on-off control subelement of being mutually coupled, second switch control
Subelement and the 3rd on-off control subelement.
21. latch as claimed in claim 20, it is characterised in that described first on-off control subelement bag
Including transistor MC1, described second switch controls subelement and includes transistor MC2, described 3rd switch control
Subunit includes transistor MC3.
22. latch as claimed in claim 21, it is characterised in that described transistor MC1, described crystal
Pipe MC2 and described transistor MC3 is PMOS, wherein:
The source electrode of described transistor MC1 couples with the drain electrode of described transistor MC2, and grid is that clock signal is defeated
Entering end, the source electrode with described transistor MC3 that drains couples；
The source electrode of described transistor MC2 and supply coupling, grid is the first feedforward end；
The grid of described transistor MC3 is the second feedforward end, drains as outfan.
23. latch as claimed in claim 21, it is characterised in that described transistor MC1 is PMOS,
Described transistor MC2 is PMOS, and described transistor MC3 is NMOS tube, wherein:
The source electrode of described transistor MC1 couples with the drain electrode of described transistor MC2, and grid is that clock signal is defeated
Entering end, the drain electrode with described transistor MC3 that drains couples；
The source electrode of described transistor MC2 and supply coupling, grid is the first feedforward end；
The grid of described transistor MC3 is the second feedforward end, and source electrode is outfan.
24. latch as claimed in claim 21, it is characterised in that described transistor MC1, described crystal
Pipe MC2 and described transistor MC3 is PMOS, wherein:
The source electrode of described transistor MC1 and supply coupling, grid couples with the drain electrode of described transistor MC2,
The source electrode with described transistor MC2 that drains couples；
The source electrode of described transistor MC2 is clock signal input terminal, and grid is the first feedforward end；
The grid of described transistor MC3 is the second feedforward end, drains as outfan.
25. latch as claimed in claim 21, it is characterised in that described transistor MC1 is PMOS,
Described transistor MC2 is NMOS tube, and described transistor MC3 is NMOS tube, wherein:
The source electrode of described transistor MC1 couples with the source electrode of described transistor MC2, grid and described transistor
The source electrode of MC2 couples, and drains as outfan；
The grid of described transistor MC2 is the first feedforward end, drains as clock signal input terminal；
The grid of described transistor MC3 is the second feedforward end, drain electrode and supply coupling.
26. 1 kinds of frequency dividers, it is characterised in that include that at least two is as described in any one of claim 1～25
Latch, wherein, the first input end of the arbitrary latch in described latch and the second input are respectively
Couple with the first outfan and second outfan of another latch.
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| CN201510366173.XA CN106330176B (en) | 2015-06-26 | 2015-06-26 | Latch and frequency divider |
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| CN201510366173.XA CN106330176B (en) | 2015-06-26 | 2015-06-26 | Latch and frequency divider |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098488A (en) * | 2021-03-31 | 2021-07-09 | 上海移芯通信科技有限公司 | Latch unit and frequency divider |
| WO2024041437A1 (en) * | 2022-08-26 | 2024-02-29 | 深圳市中兴微电子技术有限公司 | Differential latch circuit, switch driver, and digital-to-analog conversion circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103026623A (en) * | 2010-07-27 | 2013-04-03 | 飞思卡尔半导体公司 | Latch circuit, flip-flop circuit and frequency divider |
| CN103281071A (en) * | 2013-06-21 | 2013-09-04 | 上海中科高等研究院 | Latch and frequency divider circuit including same |
| KR20150027541A (en) * | 2013-09-04 | 2015-03-12 | 삼성전기주식회사 | Frequency divider |
| CN104426530A (en) * | 2013-09-04 | 2015-03-18 | 财团法人工业技术研究院 | Latch, operation method thereof and comparator |
-
2015
- 2015-06-26 CN CN201510366173.XA patent/CN106330176B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103026623A (en) * | 2010-07-27 | 2013-04-03 | 飞思卡尔半导体公司 | Latch circuit, flip-flop circuit and frequency divider |
| CN103281071A (en) * | 2013-06-21 | 2013-09-04 | 上海中科高等研究院 | Latch and frequency divider circuit including same |
| KR20150027541A (en) * | 2013-09-04 | 2015-03-12 | 삼성전기주식회사 | Frequency divider |
| CN104426530A (en) * | 2013-09-04 | 2015-03-18 | 财团法人工业技术研究院 | Latch, operation method thereof and comparator |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098488A (en) * | 2021-03-31 | 2021-07-09 | 上海移芯通信科技有限公司 | Latch unit and frequency divider |
| WO2024041437A1 (en) * | 2022-08-26 | 2024-02-29 | 深圳市中兴微电子技术有限公司 | Differential latch circuit, switch driver, and digital-to-analog conversion circuit |
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| CN106330176B (en) | 2019-01-29 |
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