CN106330177B - latch - Google Patents
latch Download PDFInfo
- Publication number
- CN106330177B CN106330177B CN201510372875.9A CN201510372875A CN106330177B CN 106330177 B CN106330177 B CN 106330177B CN 201510372875 A CN201510372875 A CN 201510372875A CN 106330177 B CN106330177 B CN 106330177B
- Authority
- CN
- China
- Prior art keywords
- transistor
- switch
- control unit
- latch
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Logic Circuits (AREA)
Abstract
A kind of latch, including：The first and second logic unit being coupled between power supply and ground wire, and first logic unit and second logical unit structure are symmetrical；First, second, third and the 4th control unit, described first, one end of third control unit and first, second logic unit couples, form the first access, described second, the other end of the 4th control unit and first, second logic unit couple, form alternate path；It include multiple switch in any control unit, each switch is suitable for according to the control signal closing or opening from control signal input is received, so that the output signal of latch output and the control signal duty ratio corresponding.Using the latch, the circuit complexity of frequency divider can be effectively reduced, to reduce the complexity of radio circuit, reduce the area of radio circuit.
Description
Technical field
The present invention relates to digital circuit field more particularly to a kind of latch.
Background technique
With the rapid development of mobile communication technology, to the configurability of radio circuit, speed, power consumption requirement increasingly
It is high.Basic unit of the two-divider circuit as frequency dividing circuit is to restrict one of circuit speed and the Key Circuit of power consumption.
High speed two-divider circuit is generally made of two stage latch unit, and any latch unit is another lock
The rear class unit of storage power supply.In conventional frequency divider circuit, latch unit is driven by identical clock, and in Razavi
In structure two-divider circuit, latch unit is driven by complementary clock.Relative to conventional frequency divider circuit, Razavi knot
Faster, power consumption is lower for structure two-divider circuit speed.
In the prior art, radio frequency system generates the output signal of different duty using a signal source.Usual situation
Under, there are the frequency dividers of multiple and different structures in radio frequency system, to generate the output signal of different duty respectively.
However, improving the complexity of radio circuit when using multiple frequency dividers, the area of radio circuit is increased.
Summary of the invention
What the embodiment of the present invention solved the problem of is how to reduce the complexity reduction radio circuit area of radio circuit.
To solve the above problems, the embodiment of the present invention provides a kind of latch, including：
The first and second logic unit being coupled between power supply and ground wire, and first logic unit and described the
Two logical unit structures are symmetrical；
First, second, third and the 4th control unit, described first, third control unit patrols with described first, second
One end coupling for collecting unit forms the first access, described second, the 4th control unit and first, second logic unit
Other end coupling, forms alternate path；
It include multiple switch in any control unit, each switch is suitable for basis and receives from control signal input
Signal closing or opening is controlled, so that the output signal of latch output and the control signal duty ratio corresponding.
Optionally, the number at least two of the control signal input.
Optionally, the control signal of each control signal input input is control level, and the control signal is each control
The control word that level combinations processed are formed.
Optionally, any control unit includes：Control terminal, the first output end, second output terminal and clock letter
Number input terminal, wherein：
First output end of the first control unit and the first output end, first logic unit of the latch
The coupling of the first output end, the first input end of second output terminal and first logic unit couples；
First output end of second control unit and second output terminal, first logic unit of the latch
Second output terminal coupling, the second input terminal of second output terminal and first logic unit couples；
First output end of the third control unit and the first output end, second logic unit of the latch
The coupling of the first output end, the first input end of second output terminal and second logic unit couples；
First output end of the 4th control unit and second output terminal, second logic unit of the latch
Second output terminal coupling, the second input terminal of second output terminal and second logic unit couples；Wherein：First control
Unit processed and the second control unit symmetrical configuration；The third control unit and the 4th control unit symmetrical configuration.
Optionally, first logic unit includes the 9th transistor and the tenth transistor, and the 9th transistor
It is NMOS tube with the tenth transistor；Second logic unit includes the 11st transistor and the tenth two-transistor, and
11st transistor and the tenth two-transistor are PMOS tube, wherein：
The drain electrode of 9th transistor is the first output end of first logic unit, with the first control unit
The first output end and the latch the first output end coupling；Source level is the first input of first logic unit
End is coupled with the second output terminal of the first control unit；The drain electrode of grid and the tenth transistor couples；
The drain electrode of tenth transistor is the second output terminal of first logic unit, with second control unit
The first output end and the latch second output terminal coupling；Source level is the second input of first logic unit
End is coupled with the second output terminal of second control unit；The drain electrode of grid and the 9th transistor couples；
The drain electrode of 11st transistor is the first output end of second logic unit, is controlled with the third single
The first output end coupling of the first output end and the latch of member；Source level is the first input of second logic unit
End is coupled with the second output terminal of the third control unit；The drain electrode of grid and the tenth two-transistor couples；
The drain electrode of tenth two-transistor is the second output terminal of second logic unit, single with the 4th control
The second output terminal coupling of the first output end and the latch of member；Source level is the second input of second logic unit
End is coupled with the second output terminal of the 4th control unit；The drain electrode of grid and the 11st transistor couples.
Optionally, the first control unit includes：First switch, third switch, the 9th switch, the first transistor and
5th transistor, wherein：
The clock signal input terminal of the first end of the first switch and the first control unit couples, second end and institute
State the first end coupling of the grid and third switch of the first transistor；
The second end and supply coupling of the third switch；
The first transistor is NMOS tube, and the source level and ground wire of the first transistor couple, drain electrode and the described 9th
The source level of transistor couples；
The first end of 9th switch and the control terminal of the first control unit couple, second end and the 5th crystalline substance
The grid of body pipe couples；
5th transistor is NMOS tube, the source electrode of the 5th transistor and the source electrode coupling of the 9th transistor
It connects, the second output terminal as the first control unit；Drain electrode is coupled with the drain electrode of the 9th transistor, and with the lock
First output end of storage couples.
Optionally, second control unit includes：Second switch, the 4th switch, the tenth switch, second transistor and
6th transistor, wherein：
The clock signal input terminal of the first end of the second switch and second control unit couples, second end and institute
State the first end coupling of the grid and the 4th switch of second transistor；
The second end and supply coupling of 4th switch；
The second transistor is NMOS tube, and the source level and ground wire of the second transistor couple, drain electrode and the described tenth
The source level of transistor couples；
The first end of tenth switch and the control terminal of second control unit couple, second end and the 6th crystalline substance
The grid of body pipe couples；
6th transistor is NMOS tube, the source electrode of the 6th transistor and the source electrode coupling of the tenth transistor
It connects, the second output terminal as second control unit；Drain electrode is coupled with the drain electrode of the tenth transistor, and with the lock
The second output terminal of storage couples.
Optionally, the third control unit includes：5th switch, the 7th switch, the 17th switch, third transistor with
And the 7th transistor, wherein：
The first end of 5th switch and the clock signal input terminal of the third control unit couple, second end and institute
State the first end coupling of the grid and the 7th switch of third transistor；
The second end and ground wire of 7th switch couple；
The third transistor is PMOS tube, the source level and supply coupling of the third transistor, drain electrode and the described tenth
The source level of one transistor couples；
The first end of 17th switch and the control terminal of the third control unit couple, second end and the described 7th
The grid of transistor couples；
7th transistor is PMOS tube, the source electrode of the 7th transistor and the source electrode coupling of the 11st transistor
It connects, the second output terminal as the third control unit；Drain electrode is coupled with the drain electrode of the 11st transistor, and with it is described
First output end of latch couples.
Optionally, the 4th control unit includes：6th switch, the 8th switch, eighteenmo close, the 4th transistor with
And the 8th transistor, wherein：
The first end of 6th switch and the clock signal input terminal of the 4th control unit couple, second end and institute
State the first end coupling of the grid and the 8th switch of the 4th transistor；
The second end and ground wire of 8th switch couple；
4th transistor is PMOS tube, the source level and supply coupling of the 4th transistor, drain electrode and the described tenth
The source level of two-transistor couples；
The control terminal of first end and the 4th control unit that the eighteenmo closes couples, second end and the described 8th
The grid of transistor couples；
8th transistor is PMOS tube, the source electrode of the 8th transistor and the source electrode coupling of the tenth two-transistor
It connects, the second output terminal as the 4th control unit；Drain electrode is coupled with the drain electrode of the tenth two-transistor, and with it is described
The second output terminal of latch couples.
Optionally, the first control unit includes：First switch, third switch, the 9th switch, the 11st switch, the
13 switches, the 15th switch, the first transistor and the 5th transistor, wherein：The first transistor and the 5th crystalline substance
Body pipe is NMOS tube,
The clock signal input terminal of the first end of the first switch and the first control unit couples, second end and institute
State the first end coupling of the grid and third switch of the first transistor；The second end and power supply coupling of the third switch
It connects；
The source level and ground wire of the first transistor couple, the source level and the described tenth of drain electrode and the 9th transistor
The first end coupling of five switches；
The first end of 9th switch and the first input end of the latch couple, second end and the 5th crystal
The second end coupling of the grid of pipe and the 11st switch；The first end and ground wire of 11st switch couple；
The first end of 13rd switch and the drain electrode of the 5th transistor couple, second end and the latch
The drain electrode of first output end and the 9th transistor couples；
The drain electrode of the source level and the first transistor of the first end and the 9th transistor of 15th switch
The source level of coupling, second end and the 5th transistor couples.
Optionally, the second control unit includes：Second switch, the 4th switch, the tenth switch, the 12nd switch, the 14th
Switch, sixteenmo pass, second transistor and the 6th transistor, wherein：The second transistor and the 6th crystal
Pipe is NMOS tube,
The clock signal input terminal of the first end of the second switch and second control unit couples, second end and institute
State the first end coupling of the grid and the 4th switch of second transistor；The second end and power supply coupling of 4th switch
It connects；
The source level and ground wire of the second transistor couple, the source level and the described tenth of drain electrode and the tenth transistor
The first end coupling of six switches；
The first end of tenth switch and the second input terminal of the latch couple, second end and the 6th crystal
The second end coupling of the grid of pipe and the 12nd switch；The first end and ground wire of 12nd switch couple；
The first end of 14th switch and the drain electrode of the 6th transistor couple, second end and the latch
The drain electrode of second output terminal and the tenth transistor couples；
The drain electrode of the source level and the second transistor of first end and the tenth transistor that the sixteenmo closes
The source level of coupling, second end and the 6th transistor couples.
Optionally, third control unit includes：5th switch, the 7th switch, the 17th switch, the 19th switch, second
11 switches, the 23rd switch, third transistor and the 7th transistor, wherein：The third transistor and the described 7th
Transistor is PMOS tube,
The first end of 5th switch and the clock signal input terminal of the third control unit couple, second end and institute
State the first end coupling of the grid and the 7th switch of third transistor；The second end and ground wire coupling of 7th switch
It connects；
The source level and supply coupling of the third transistor, drain electrode and the source level of the 11st transistor and described the
The first end coupling of 21 switches；
The first end of 17th switch and the first input end of the latch couple, second end and the 7th crystalline substance
The second end coupling of the grid of body pipe and the 19th switch；The first end and supply coupling of 19th switch；
The first end of 21st switch and the drain electrode of the 7th transistor couple, second end and the latch
The first output end and the 11st transistor drain electrode coupling；
The source level and the third transistor of described 23rd first end switched and the 11st transistor
The source level of drain electrode coupling, second end and the 7th transistor couples.
Optionally, the 4th control unit includes：6th switch, the 8th switch, eighteenmo close, the 20th switchs,
22nd switch, the 24th switch, the 4th transistor and the 8th transistor, wherein：4th transistor with it is described
8th transistor is PMOS tube,
The first end of 6th switch and the clock signal input terminal of the 4th control unit couple, second end and institute
State the first end coupling of the grid and the 8th switch of the 4th transistor；The second end and ground wire coupling of 8th switch
It connects；
The source level and supply coupling of 4th transistor, drain electrode and the source level of the tenth two-transistor and described the
The first end coupling of 22 switches；
Second input terminal of first end and the latch that the eighteenmo closes couples, second end and the 8th crystalline substance
The second end coupling of the grid of body pipe and the 20th switch；The first end and supply coupling of 20th switch；
The first end of 22nd switch and the drain electrode of the 8th transistor couple, second end and the latch
Second output terminal and the tenth two-transistor drain electrode coupling；
The source level and the 4th transistor of described 24th first end switched and the tenth two-transistor
The source level of drain electrode coupling, second end and the 8th transistor couples.
Compared with prior art, the technical solution of the embodiment of the present invention has the following advantages that：
Include multiple switch in any control unit in latch, when latch receives control signal, respectively opens
It closes according to control signal closing or opening, so that the output signal of latch output and control signal duty ratio corresponding.Using same
One latch can export the output signal of different duty, frequency divider can be effectively reduced according to different control signals
Circuit complexity reduce radio circuit area to reduce the complexity of radio circuit.
Detailed description of the invention
Fig. 1 is a kind of circuit structure diagram of existing high speed two-divider circuit；
Fig. 2 is the circuit structure diagram for the latch that a kind of existing output signal duty ratio is 25%；
Fig. 3 is the circuit structure diagram for the latch that a kind of existing output signal duty ratio is 75%；
Fig. 4 is the circuit structure diagram for the latch that a kind of existing output signal duty ratio is 50%；
Fig. 5 is the structural schematic diagram of one of embodiment of the present invention latch；
Fig. 6 is the circuit structure diagram of one of embodiment of the present invention latch；
Fig. 7 is the circuit structure diagram of another latch in the embodiment of the present invention；
Fig. 8 is the circuit structure diagram for the latch that one of embodiment of the present invention output signal duty ratio is 25%；
Fig. 9 is the operation schematic diagram for the latch that duty ratio is 25% in Fig. 8；
Figure 10 is the circuit structure diagram for the latch that one of embodiment of the present invention output signal duty ratio is 50%；
Figure 11 is the operation schematic diagram for the latch that duty ratio is 50% in Figure 10；
Figure 12 is the circuit structure diagram for the latch that another output signal duty ratio in the embodiment of the present invention is 50%；
Figure 13 is the operation schematic diagram for the latch that duty ratio is 50% in Figure 12；
Figure 14 is the circuit structure diagram for the latch that one of embodiment of the present invention output signal duty ratio is 75%；
Figure 15 is the operation schematic diagram for the latch that duty ratio is 75% in Figure 14；
Figure 16 is the circuit structure diagram for the latch that another output signal duty ratio in the embodiment of the present invention is 25%；
Figure 17 is the circuit structure diagram for the latch that another output signal duty ratio in the embodiment of the present invention is 25%.
Specific embodiment
In the prior art, radio frequency system generates the output signal of different duty using a signal source.Usual situation
Under, there are the frequency dividers of multiple and different structures in radio frequency system, to generate the output signal of different duty respectively.However, adopting
When with multiple frequency dividers, the complexity of radio circuit is improved, increases the area of radio circuit.
It in embodiments of the present invention, include multiple switch in any control unit in latch, when latch receives
To when controlling signal, each switch is according to control signal closing or opening, so that latch output and control signal duty ratio corresponding
Output signal.Using the same latch, the output signal of different duty can be exported according to different control signals,
The circuit complexity of frequency divider can be effectively reduced, to reduce the complexity of radio circuit, reduce radio circuit area.
It is understandable to enable the above objects, features, and advantages of the embodiment of the present invention to become apparent, it is right with reference to the accompanying drawing
Specific embodiments of the present invention are described in detail.
Referring to Fig.1, a kind of high speed two-divider in the prior art, including latch 101 and 102 are given.
Latch 101 and latch 102 are d type flip flop, and the end D and the end Dn are input terminal, and the end Q and the end Qn are defeated
Outlet.Clock signal input terminal the CLK input clock signal CK, the clock signal input terminal CLK of latch 102 of latch 101
Input clock signal CKb, and clock signal CK and clock signal CKb reverse phase.
The end D of latch 101 and the end Qn of latch 102 couple, and the end D of the end Q and latch 102 couples, the end Dn and lock
The end Q of storage 102 couples, and the end Dn of the end Qn and latch 102 couples.I.e.：The input terminal of latch 101 and latch 102
Output end is respectively coupled to, and the input terminal of the output end and latch 102 of latch 101 is respectively coupled to, latch 101 and latch
102 front stages each other.
Fig. 2 shows realize duty ratio for the circuit structure of the latch in the high speed two-divider of 25% fractional frequency signal
Schematic diagram.The latch includes：First logic unit 201, the second logic unit 202, first control unit 203 and second
Control unit 204, wherein：
First logic unit 201 and the second logic unit 202 are coupled between power supply VREF_1 and ground wire VREF_2, and two
Person's circuit structure is symmetrical；
First control unit 203 is coupled between the first logic unit 201 and power supply VREF_1, including clock signal input
Hold CLK1.Second control unit 204 is coupled between the second logic unit 202 and power supply VREF_1, including clock signal input
Hold CLK2.The clock signal input terminal of the clock signal input terminal CLK1 of first control unit 203 and the second control unit 204
CLK2 can be with input high level signal VREF_3 and low level signal VREF_4.
First logic unit 201 includes the first signal input part D and the first signal output end Qn, the second logic unit packet
Include second signal input terminal Dn and second signal output end Q.
First control unit 203 include the first transistor M1, the second control unit 204 include second transistor M2, first
Logic unit 201 includes third transistor M3 and the 5th transistor M5, and the second logic unit 202 includes the 4th transistor M4 and the
Six transistor M6.Wherein, the first transistor M1 and second transistor M2 be NMOS tube, third transistor M3, the 4th transistor M4,
5th transistor M5 and the 6th transistor M6 is NMOS tube.
The source electrode of the first transistor M1 and second transistor M2 are coupled with power supply VREF_1 respectively, the leakage of the first transistor M1
Pole respectively with the drain electrode of third transistor M3 and the 5th transistor M5 and the first output end Qn and the 4th transistor M4
Grid coupling.The drain electrode of second transistor M2 is defeated with the drain electrode of the 4th transistor M4 and the 6th transistor M6 and second respectively
The coupling of the grid of outlet Q and third transistor M3.Third transistor M3, the 4th transistor M4, the 5th transistor M5 and the 6th are brilliant
The source electrode and ground wire VREF_2 of body pipe M6 couples.
Fig. 3 shows the circuit structure of the latch in the high speed two-divider for the fractional frequency signal for realizing that duty ratio is 75%
Schematic diagram.The latch includes：First logic unit 301, the second logic unit 302, first control unit 303 and second
Control unit 304, wherein：
First logic unit 301 and the second logic unit 302 are coupled between power supply VREF_1 and ground wire VREF_2, and two
Person's circuit structure is symmetrical；
First control unit 303 is coupled between the first logic unit 301 and power supply VREF_1, including clock signal input
Hold CLK1.Second control unit 304 is coupled between the second logic unit 302 and power supply VREF_1, including clock signal input
Hold CLK2.The clock signal input terminal of the clock signal input terminal CLK1 of first control unit 303 and the second control unit 304
CLK2 can be with input high level signal VREF_3 and low level signal VREF_4.
First logic unit 301 includes the first signal input part D and the first signal output end Qn, the second logic unit packet
Include second signal input terminal Dn and second signal output end Q.
First control unit 303 include the first transistor M1, the second control unit 304 include second transistor M2, first
Logic unit 301 includes third transistor M3 and the 5th transistor M5, and the second logic unit 302 includes the 4th transistor M4 and the
Six transistor M6.Wherein, the first transistor M1 and second transistor M2 be PMOS tube, third transistor M3, the 4th transistor M4,
5th transistor M5 and the 6th transistor M6 is PMOS tube.
The grid of the first transistor M1 is the first clock signal input terminal CLK1, and source electrode and ground wire VREF_2 are coupled, drain electrode
The drain electrode of drain electrode and third transistor M3 with the 5th transistor M5 couples.The grid of second transistor M2 is second clock letter
Number input terminal CLK2, source electrode and ground wire VREF_2 are coupled, the drain electrode of drain electrode and the 4th transistor M4 and the 6th transistor M6's
Drain electrode coupling.
Fig. 4 shows the circuit structure of the latch in the high speed two-divider for the fractional frequency signal for realizing that duty ratio is 50%
Schematic diagram.Latch includes：First logic unit 401, the second logic unit 402 and first control unit 403, second are controlled
Unit 404, third control unit 405 and the 4th control unit 406 processed, wherein：First logic unit 401 and the second logic list
Member 402 is coupled between power supply VREF_1 and ground wire VREF_2, and the two circuit structure is symmetrical.
First logic unit 401 includes third transistor M3 and the 5th transistor M5, and the second logic unit 402 includes the 4th
Transistor M4 and the 6th transistor M6, and third transistor M3, the 5th transistor M5, the 4th transistor M4 and the 6th transistor
M6 is NMOS tube.Wherein：
Third transistor M3, drain electrode and the drain electrode of the 5th transistor M5 couple, and first as the first logic unit 401 is defeated
Outlet；The drain electrode of grid and the 4th transistor M4 couple；The coupling of the source electrode of source electrode and the 5th transistor M5, and list is controlled with third
Member 405 couples；
5th transistor M5, grid are the input terminal of the first logic unit 401；
4th transistor M4, drain electrode and the drain electrode of the 6th transistor M6 couple, and first as the second logic unit 402 is defeated
Outlet；The drain electrode of grid and third transistor M3 couple；The coupling of the source electrode of source electrode and the 4th transistor M4, and it is single with the 4th control
Member 406 couples；
6th transistor M6, grid are the input terminal of the second logic unit 402.
First control unit 403 include the first transistor M1, the first transistor M1 be PMOS tube, source electrode and supply coupling,
Grid is clock signal input terminal, and drain electrode and the drain electrode of third transistor M3 couple.
Second control unit 404 include second transistor M2, second transistor M2 be PMOS tube, source electrode and supply coupling,
Grid is clock signal input terminal, and drain electrode and the drain electrode of the 4th transistor M4 couple.
Third control unit 405 includes the 7th transistor M7, and the 7th transistor M7 is NMOS tube, and source electrode and ground wire couple,
Grid is clock signal input terminal, and drain electrode and the source electrode of the 5th transistor M5 couple.
4th control unit 406 includes the 8th transistor M8, and the 8th transistor M8 is NMOS tube, and source electrode and ground wire couple,
Grid is clock signal input terminal, and drain electrode and the source electrode of the 6th transistor M6 couple.
When radio frequency system needs to generate the output signal of different duty, for example, radio frequency system generation duty ratio is
25%, it when 50% and 75% output signal, needs that latch as shown in figs. 2 to 4 is arranged, leads to the complexity of radio circuit
It spends higher.
Referring to Fig. 5, the structural schematic diagram of one of embodiment of the present invention latch is given, including：First logic list
First 501, second logic unit 502, first control unit 503, the second control unit 504, third control unit 505 and the 4th
Control unit 506, wherein：
First logic unit 501 and the second logic unit 502 are coupled between power supply VREF_1 and ground wire VREF_2, and the
502 symmetrical configuration of one logic unit 501 and the second logic unit；
First control unit 503, the second control unit 504, third control unit 505 and the 4th control unit 506,
In：One end coupling of first control unit 503, third control unit 505 and the first logic unit 501, the second logic unit 502
It connects, forms the first access；Second control unit 504, the 4th control unit 506 and the first logic unit 501, the second logic unit
502 other end coupling, forms alternate path.
In specific implementation, it may each comprise multiple switch in each control unit.When latch circuit receives control
When the control signal of signal input part input processed, according to preset corresponding relationship, the partial switch in each control unit is closed
It closes, remaining switch disconnects, to control the output signal of latch output with control signal duty ratio corresponding.
In embodiments of the present invention, latch may include at least two control signal inputs, and each control signal is defeated
The control signal for entering end input is control level, the control word that control signal can be formed for each control level combinations.Different
The duty ratio for controlling the corresponding output signal of control word that level combinations are formed can be different, can be according to actual application scenarios
It is set.
For example, the number of control signal input is two, control level includes high level " 1 " and low level " 0 ", when
Control level combinations formed control word be " 01 " when, output duty cycle be 25% output signal；When control level combinations shape
At control word be " 10 " when, output duty cycle be 50% output signal；When the control word that control level combinations are formed is
When " 11 ", output duty cycle be 75% output signal.
For another example, the number of control signal input is three, and control level includes high level " 1 " and low level " 0 ", when
Control level combinations formed control word be " 100 " when, output duty cycle be 25% output signal；When control level combinations shape
At control word be " 010 " when, output duty cycle be 50% output signal；When the control word that control level combinations are formed is
When " 001 ", output duty cycle be 75% output signal.
In specific implementation, the first output end of the first output end and latch of first control unit 503, the first logic
First output end of unit 501 couples, and the first input end of second output terminal and the first logic unit 501 couples；
The second of the second output terminal of first output end of the second control unit 504 and latch, the first logic unit 501
Second input terminal of output end coupling, second output terminal and the first logic unit 501 couples；
The first of first output end of the first output end of third control unit 505 and latch, the second logic unit 502
The first input end of output end coupling, second output terminal and the second logic unit 502 couples；
The second of the second output terminal of first output end of the 4th control unit 506 and latch, the second logic unit 502
Second input terminal of output end coupling, second output terminal and the second logic unit 502 couples；Wherein：First control unit 503 with
Second control unit, 504 symmetrical configuration；506 symmetrical configuration of third control unit 505 and the 4th control unit.
It can be seen that including multiple switch in any control unit in latch, when latch receives control letter
Number when, each switch is according to control signal closing or opening, so that latch output and the output of control signal duty ratio corresponding are believed
Number.Using the same latch, the output signal of different duty can be exported according to different control signals, it can be effective
The circuit complexity of frequency divider is reduced, to reduce the complexity of radio circuit, reduces radio circuit area.
Referring to Fig. 6, the circuit structure diagram of one of embodiment of the present invention latch is given, is illustrated in conjunction with Fig. 5.
First logic unit 501 includes the 9th transistor M9 and the tenth transistor M10, and the 9th transistor M9 and the tenth is brilliant
Body pipe M10 is NMOS tube；Second logic unit 502 includes the 11st transistor M11 and the tenth two-transistor M12, and the tenth
One transistor M11 and the tenth two-transistor M12 is PMOS tube.
The drain electrode of 9th transistor M9 is the first output end of the first logic unit 501, the with first control unit 503
First output end Q of one output end and latch coupling；Source level is the first input end of the first logic unit 501, with first
The second output terminal of control unit 503 couples；The drain electrode of grid and the tenth transistor M10 couple.
The drain electrode of tenth transistor M10 is the second output terminal of the first logic unit 501, with the second control unit 504
The second output terminal Qn of first output end and latch coupling；Source level is the second input terminal of the first logic unit 501, with the
The second output terminal of two control units 504 couples；The drain electrode of grid and the 9th transistor M9 couple.
The drain electrode of 11st transistor M11 is the first output end of the second logic unit 502, with third control unit 505
The first output end and latch the first output end Q coupling；Source level is the first input end of the second logic unit 502, with
The second output terminal of third control unit 505 couples；The drain electrode of grid and the tenth two-transistor M12 couple.
The drain electrode of tenth two-transistor M12 is the second output terminal of the second logic unit 502, with the 4th control unit 506
The first output end and latch second output terminal Qn coupling；Source level is the second input terminal of the second logic unit 502, with
The second output terminal of 4th control unit couples；The drain electrode of grid and the 11st transistor M11 couple.
First control unit 503 includes：First switch SW1, third switch SW3, the 9th switch SW9, the first transistor M1
And the 5th transistor M5, wherein：
The clock signal input terminal CLKB of the first end of first switch SW1 and first control unit 503 is coupled, second end with
The first end coupling of the grid and third switch SW3 of the first transistor M1；
The second end of third switch SW3 can be coupled with power supply VREF_1；
The first transistor M1 is NMOS tube, and the source level and ground wire VREF_2 of the first transistor M1 couples, and drain electrode is brilliant with the 9th
The source electrode coupling of the source level and the 5th transistor M5 of body pipe M9；
The first end of 9th switch SW9 and the control terminal of first control unit 503 couple, second end and the 5th transistor M5
Grid coupling；The control terminal of first control unit 503 is the first input end D of latch.
5th transistor M5 is NMOS tube, and the source electrode of the 5th transistor M5 and the source electrode of the 9th transistor M9 couple, as
The second output terminal of first control unit 503；Drain electrode and the drain electrode of the 9th transistor M9 couple, as first control unit 503
The first output end, and with the first output end Q of latch couple.
Second control unit 504 includes：Second switch SW2, the 4th switch SW4, the tenth switch SW10, second transistor M2
And the 6th transistor M6, wherein：
The clock signal input terminal CLKB of the first end of second switch SW2 and the second control unit 504 is coupled, second end with
The coupling of the first end of the grid of second transistor M2 and the 4th switch SW4；
The second end of 4th switch SW4 can be coupled with power supply VREF_1；
Second transistor M2 is NMOS tube, and the source level and ground wire VREF_2 of second transistor M2 couples, and drain electrode is brilliant with the tenth
The source electrode coupling of the source level and the 6th transistor M6 of body pipe M10；
The control terminal of the first end of tenth switch SW10 and the second control unit 504 couples, second end and the 6th transistor
The grid of M6 couples；The control terminal of second control unit 504 is the second input terminal Dn of latch.
6th transistor M6 is NMOS tube, the source electrode coupling of the source electrode of second transistor M2 and the tenth transistor M10, as
The second output terminal of second control unit 504；Drain electrode and the drain electrode of the tenth transistor M10 couple, as the second control unit 504
The first output end, and with the second output terminal Qn of latch couple.
Third control unit 505 includes：5th switch SW5, the 7th switch SW7, the 17th switch SW17, third transistor
M3 and the 7th transistor M7, wherein：
The clock signal input terminal CLK of the first end of 5th switch SW5 and third control unit 505 is coupled, second end with
The coupling of the first end of the grid of third transistor M3 and the 7th switch SW7；
The second end of 7th switch SW7 can be coupled with ground wire VREF_2；
Third transistor M3 is PMOS tube, and the source level and power supply VREF_1 of third transistor M3 couples, drain electrode and the 11st
The coupling of the source electrode of the source level of transistor M11 and the 7th transistor M7；
The first end of 17th switch SW17 and the control terminal of third control unit 505 couple, second end and the 7th crystal
The grid of pipe M7 couples；The control terminal of third control unit 505 is the first input end D of latch.
7th transistor M7 is PMOS tube, and the source electrode of the 7th transistor M7 and the source electrode of the 11st transistor M11 couple, make
For the second output terminal of third control unit 505；Drain electrode and the drain electrode of the 11st transistor M11 couple, and control as third single
First output end of member 505, and coupled with the first output end Q of latch.
4th control unit 506 includes：6th switch SW6, the 8th switch SW8, eighteenmo close SW18, the 4th transistor
M4 and the 8th transistor M8, wherein：
The clock signal input terminal CLK of the first end of 6th switch SW6 and the 4th control unit 506 is coupled, second end with
The first end coupling of the grid and the 8th switch SW8 of 4th transistor M4；
The second end of 8th switch SW8 can be coupled with ground wire VREF_2；
4th transistor M4 is PMOS tube, and the source level and power supply VREF_1 of the 4th transistor M4 couples, drain electrode and the 12nd
The coupling of the source electrode of the source level of transistor M12 and the 8th transistor M8；
The control terminal of first end and the 4th control unit 506 that eighteenmo closes SW18 couples, second end and the 8th crystal
The grid of pipe M8 couples；The control terminal of 4th control unit 506 is the second input terminal Dn of latch.
8th transistor M8 is PMOS tube, and the source electrode of the 8th transistor M8 and the source electrode of the tenth two-transistor M12 couple, make
For the second output terminal of the 4th control unit 506；Drain electrode and the drain electrode of the tenth two-transistor M12 couple, single as the 4th control
The second output terminal of member 506, and coupled with the second output terminal Qn of latch.
Referring to Fig. 7, the circuit structure diagram of another latch in the embodiment of the present invention is given, is said in conjunction with Fig. 5
It is bright.
First control unit 503 includes：First switch SW1, third switch SW3, the 9th switch SW9, the 11st switch
SW11, the 13rd switch SW13, the 15th switch SW15, the first transistor M1 and the 5th transistor M5, wherein：First crystal
Pipe M1 and the 5th transistor M5 is NMOS tube,
The clock signal input terminal CLKB of the first end of first switch SW1 and first control unit 503 is coupled, second end with
The first end coupling of the grid and third switch SW3 of the first transistor M1；
The second end and power supply VREF_1 of third switch SW3 couples；
The source level and ground wire VREF_2 of the first transistor M1 couples, the source level and the 15th of drain electrode and the 9th transistor M9
The first end of switch SW15 couples；
The first end of 9th switch SW9 and the first input end D of latch are coupled, the grid of second end and the 5th transistor M5
The coupling of the second end of pole and the 11st switch SW11；
The first end and ground wire VREF_2 of 11st switch SW11 couples；
The first of the first end of 13rd switch SW13 and the drain electrode coupling of the 5th transistor M5, second end and latch is defeated
The drain electrode of outlet Q and the 9th transistor M9 couple；
The drain electrode of the first end of 15th switch SW15 and the source level of the 9th transistor M9 and the first transistor M1 couples,
The source level of second end and the 5th transistor M5 couple.
Second control unit 504 includes：Second switch SW2, the 4th switch SW4, the tenth switch SW10, the 12nd switch
SW12, the 14th switch SW14, sixteenmo close SW16, second transistor M2 and the 6th transistor M6, wherein：Second crystal
Pipe M2 and the 6th transistor M6 is NMOS tube,
The clock signal input terminal CLKB of the first end of second switch SW2 and the second control unit 504 is coupled, second end with
The coupling of the first end of the grid of second transistor M2 and the 4th switch SW4；
The second end and power supply VREF_1 of 4th switch SW4 couples；
The source level and ground wire VREF_2 of second transistor M2 couples, the source level and the tenth of drain electrode and the tenth transistor M10
The first end of six switch SW16 couples；
The first end of tenth switch SW10 and the second input terminal Dn of latch are coupled, and second end is with the 6th transistor M6's
The coupling of the second end of grid and the 12nd switch SW12；
The first end and ground wire VREF_2 of 12nd switch SW12 couples；
The second of the first end of 14th switch SW14 and the drain electrode coupling of the 6th transistor M6, second end and latch is defeated
The drain electrode of outlet Qn and the tenth transistor M10 couple；
Sixteenmo closes the first end and the source level of the tenth transistor M10 and the drain electrode coupling of second transistor M2 of SW16
It connects, the source level of second end and the 6th transistor M6 couple.
Third control unit 505 includes：5th switch SW5, the 7th switch SW7, the 17th switch SW17, the 19th switch
SW19, the 21st switch SW21, the 23rd switch SW23, third transistor M3 and the 7th transistor M7, wherein：Third
Transistor M3 and the 7th transistor M7 is PMOS tube,
The clock signal input terminal CLK of the first end of 5th switch SW5 and third control unit 505 is coupled, second end with
The coupling of the first end of the grid of third transistor M3 and the 7th switch SW7；
The second end and ground wire VREF_2 of 7th switch SW7 couples；
The source level of third transistor M3 and power supply VREF_1 are coupled, the source level of drain electrode and the 11st transistor M11 and the
The first end of 21 switch SW21 couples；
The first end of 17th switch SW17 and the first input end D of latch are coupled, second end and the 7th transistor M7
Grid and the 19th switch SW19 second end coupling；
The first end and power supply VREF_1 of 19th switch SW19 couples；
The first end of 21st switch SW21 and the drain electrode of the 7th transistor M7 couple, and the first of second end and latch
The drain electrode of output end Q and the 11st transistor M11 couple；
The drain electrode of the source level and third transistor M3 of the first end and the 11st transistor M11 of 23rd switch SW23
The source level of coupling, second end and the 7th transistor M7 couple.
4th control unit 506 includes：6th switch SW6, the 8th switch SW8, eighteenmo close SW18, the 20th switch
SW20, the 22nd switch SW22, the 24th switch SW24, the 4th transistor M4 and the 8th transistor M8, wherein：4th
Transistor M4 and the 8th transistor M8 is PMOS tube,
The clock signal input terminal CLK of the first end of 6th switch SW6 and the 4th control unit 506 is coupled, second end with
The first end coupling of the grid and the 8th switch SW8 of 4th transistor M4；The second end and ground wire VREF_2 of 8th switch SW8
Coupling；
The source level of 4th transistor M4 and power supply VREF_1 are coupled, the source level of drain electrode and the tenth two-transistor M12 and the
The first end of 22 switch SW22 couples；
Eighteenmo closes the first end of SW18 and the second input terminal Dn of latch is coupled, second end and the 8th transistor M8
Grid and the 20th switch SW20 second end coupling；The first end and power supply VREF_1 of 20th switch SW20 couples；
The first end of 22nd switch SW22 and the drain electrode of the 8th transistor M8 couple, and the second of second end and latch
The drain electrode of output end Qn and the tenth two-transistor M12 couple；
The drain electrode of the source level and the 4th transistor M4 of the first end and the tenth two-transistor M12 of 24th switch SW24
The source level of coupling, second end and the 8th transistor M8 couple.
It is understood that in practical applications, first control unit 503, the second control unit 504, third in Fig. 6
Any of control unit 505 and the 4th control unit 506 can be using control unit replacements corresponding in Fig. 7.
For example, the structure of the first control unit 503 in Fig. 6 can be replaced with the structure of the first control unit 503 in Fig. 7
It changes, the structure of the second control unit 504 in Fig. 6 can be replaced with the structure of the second control unit 504 in Fig. 7, in Fig. 6
The structure of third control unit 505 can be replaced with the structure of the third control unit 505 in Fig. 7, and the 4th control in Fig. 6 is single
The structure of member 506 can be replaced with the structure of the 4th control unit 506 in Fig. 7.
In an embodiment of the present invention, different when receiving above-mentioned three kinds by taking the latch circuit provided in Fig. 7 as an example
When controlling signal, the corresponding state for closing the switch or disconnecting is referred to table 1.
The number of control signal input is 3, is followed successively by control signal input C0, C1, C2.When control signal input
Hold C0, C1, C2 control level combinations at control word be " 100 " when, output duty cycle be 25% output signal；Work as control
Signal input part C0, C1, C2 control level combinations at control word be " 010 " when, output duty cycle be 50% output believe
Number；When control signal input C0, C1, C2 control level combinations at control word be " 001 " when, output duty cycle 75%
Output signal.In table 1, when the switches are opened, state is expressed as Open；When the switch is closed, state is expressed as
Close。
Table 1
In conjunction with table 1 and Fig. 7, when latch output duty cycle is 25% output signal, the circuit state figure of latch
As shown in Figure 8：
Third switch SW3, the 9th switch SW9, the 13rd switch SW13 and the 15th in first control unit 503 are opened
SW15 closure is closed, first switch SW1 and the 11st switch SW11 are disconnected；
The 4th switch SW4, the tenth switch SW10, the 14th switch SW14 and the 16th in second control unit 504
Switch SW16 closure, third switch SW3 and the 12nd switch SW12 are disconnected；
The 5th switch SW5, the 19th switch SW19 closure in third control unit 505, the 7th switch SW7, the 17th
Switch SW17, the 21st switch SW21 and the 23rd switch SW23 are disconnected；
The 6th switch SW6, the 20th switch SW20 closure in 4th control unit 506, the 8th switch SW8, the 18th
Switch SW18, the 22nd switch SW22 and the 24th switch SW24 are disconnected.
Fig. 8 is simplified, the switch of closure is substituted using conducting wire, the corresponding circuit of switch of disconnection is removed, obtains
Fig. 9.Fig. 9 is compared with Fig. 2, you can learn that the output signal that output duty cycle is 25% may be implemented in the circuit in Fig. 9.
In conjunction with table 1 and Fig. 7, when latch output duty cycle is 50% output signal, the circuit state figure of latch
As shown in Figure 10, Figure 12.
In Figure 10, first switch SW1, the 9th switch SW9, the 13rd switch SW13 in first control unit 503 and
15th switch SW15 closure, third switch SW3, the 11st switch SW11 are disconnected；
Second switch SW2, the tenth switch SW10, the 14th switch SW14 and the 16th in second control unit 504
Switch SW16 closure, the 4th switch SW4 and the 12nd switch SW12 are disconnected；
The 5th switch SW5, the 19th switch SW19 closure in third control unit 505, the 7th switch SW7, the 17th
Switch SW17, the 21st switch SW21 and the 23rd switch SW23 are disconnected；
The 6th switch SW6, the 20th switch SW20 closure in 4th control unit 506, the 8th switch SW8, the 18th
Switch SW18, the 22nd switch SW22 and the 24th switch SW24 are disconnected.
Figure 10 is simplified, the switch of closure is substituted using conducting wire, the corresponding circuit of switch of disconnection is removed, obtains
Figure 11.Figure 11 is compared with Fig. 4, is believed you can learn that the output that output duty cycle is 50% may be implemented in the circuit in Figure 10
Number.
In Figure 12, first switch SW1, the 11st switch SW11 in first control unit 503 are closed, third switch SW3,
9th switch SW9, the 13rd switch SW13 and the 15th switch SW15 are disconnected；
Second switch SW2, the 12nd switch SW12 closure in second control unit 504, the 4th switch SW4, the tenth open
It closes SW10, the 14th switch SW14 and sixteenmo and closes SW16 disconnection；
The 5th switch SW5, the 17th switch SW17, the 21st switch SW21 in third control unit 505 and
23 switch SW23 closure, the 7th switch SW7, the 19th switch SW19 are disconnected；
The 6th switch SW6 in 4th control unit 506, eighteenmo close SW18, the 22nd switch SW22 and the
24-carat gold closes SW24 closure, and the 8th switch SW8, the 20th switch SW20 are disconnected.
Figure 12 is simplified, the switch of closure is substituted using conducting wire, the corresponding circuit of switch of disconnection is removed, obtains
Figure 13.Figure 13 is compared with Fig. 4, is believed you can learn that the output that output duty cycle is 50% may be implemented in the circuit in Figure 12
Number.
In conjunction with table 1 and Fig. 7, when latch output duty cycle is 75% output signal, the circuit state figure of latch
As shown in figure 14.
In Figure 14, first switch SW1, the 11st switch SW11 of first control unit 503 are closed, third switch SW3, the
Nine switch SW9, the 13rd switch SW13 and the 15th switch SW15 are disconnected；
Second switch SW2, the 12nd switch SW12 of second control unit 504 are closed, the 4th switch SW4, the tenth switch
The 14th switch SW14 of SW10 and sixteenmo close SW16 and disconnect；
The 7th switch SW7, the 17th switch SW17, the 21st switch SW21 and second of third control unit 505
13 switch SW23 closure, the 5th switch SW5 and the 19th switch SW19 are disconnected；
The 8th switch SW8, the eighteenmo of 4th control unit 506 close SW18, the 22nd switch SW22 and second
14 switch SW24 closure, the 6th switch SW6 and the 20th switch SW20 are disconnected.
Figure 14 is simplified, the switch of closure is substituted using conducting wire, the corresponding circuit of switch of disconnection is removed, obtains
Figure 15.Figure 15 is compared with Fig. 5, is believed you can learn that the output that output duty cycle is 75% may be implemented in the circuit in Figure 14
Number.
In practical applications, it is to be understood that there may also be the combinations of other switch cut-off/closes, to realize
The output signal that duty ratio is 25%, 50% and 75%.
For example, third switch SW3, the 13rd switch SW13 and the 15th in Figure 16, in first control unit 503
Switch SW15 closure, first switch SW1, the 9th switch SW9 are disconnected, and the 11st switch SW11 is opened or closed；
The 4th switch SW4, the 14th switch SW14 and sixteenmo in second control unit 504 close SW16 closure,
Third switch SW3, the tenth switch SW10 are disconnected, and the 12nd switch SW12 is opened or closed；
The 5th switch SW5, the 17th switch SW17, the 21st switch SW21 in third control unit 505 and
23 switch SW23 closure, the 7th switch SW7, the 19th switch SW19 are disconnected；
The 6th switch SW6 in 4th control unit 506, eighteenmo close SW18, the 22nd switch SW22 and the
24-carat gold closes SW24 closure, and the 8th switch SW8, the 20th switch SW20 are disconnected.At this point it is possible to realize that output duty cycle is
25% output signal.
For another example, third switch SW3, the 9th switch SW9, the 13rd switch in Figure 17, in first control unit 503
SW13 and the 15th switch SW15 closure, first switch SW1 are disconnected, and the 11st switch SW11 is opened or closed；
The 4th switch SW4, the tenth switch SW10, the 14th switch SW14 and the 16th in second control unit 504
Switch SW16 closure, third switch SW3 are disconnected, and the 12nd switch SW12 is opened or closed；
The 5th switch SW5, the 17th switch SW17, the 21st switch SW21 in third control unit 505 and
23 switch SW23 closure, the 7th switch SW7, the 19th switch SW19 are disconnected；
The 6th switch SW6 in 4th control unit 506, eighteenmo close SW18, the 22nd switch SW22 and the
24-carat gold closes SW24 closure, and the 8th switch SW8, the 20th switch SW20 are disconnected.At this point it is possible to realize that output duty cycle is
25% output signal.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (13)
1. a kind of latch, which is characterized in that including：
The first and second logic unit being coupled between power supply and ground wire, and first logic unit is patrolled with described second
It is symmetrical to collect cellular construction；
First, second, third and the 4th control unit, described first, third control unit and the first, second logic list
Member one end coupling, formed the first access, described second, the 4th control unit it is another with first, second logic unit
End coupling, forms alternate path；
It include multiple switch in any control unit, each switch is suitable for basis and receives the control from control signal input
Signal closing or opening, so that the output signal of latch output and the control signal duty ratio corresponding.
2. latch as described in claim 1, which is characterized in that including：The number of the control signal input is at least
Two.
3. latch as claimed in claim 2, which is characterized in that the control signal of each control signal input input is control
Level processed, the control signal are the control word that each control level combinations are formed.
4. latch as claimed in claim 3, which is characterized in that any control unit includes：It is control terminal, first defeated
Outlet, second output terminal and clock signal input terminal, wherein：
The of first output end of the first output end of the first control unit and the latch, first logic unit
The first input end of the coupling of one output end, second output terminal and first logic unit couples；Second control unit
The second output terminal of first output end and the latch, the second output terminal of first logic unit couple, the second output
End and the second input terminal of first logic unit couple；The first output end and the latch of the third control unit
The first output end, second logic unit the coupling of the first output end, second output terminal and second logic unit
First input end coupling；The second output terminal of first output end of the 4th control unit and the latch, described second
The second output terminal of logic unit couples, and the second input terminal of second output terminal and second logic unit couples；Wherein：Institute
State first control unit and the second control unit symmetrical configuration；The third control unit and the 4th control unit knot
Structure is symmetrical.
5. latch as claimed in claim 4, which is characterized in that first logic unit includes the 9th transistor and the
Ten transistors, and the 9th transistor and the tenth transistor are NMOS tube；Second logic unit includes the tenth
One transistor and the tenth two-transistor, and the 11st transistor and the tenth two-transistor are PMOS tube, wherein：
The drain electrode of 9th transistor is the first output end of first logic unit, the with the first control unit
The coupling of first output end of one output end and the latch；Source level is the first input end of first logic unit, with
The second output terminal of the first control unit couples；The drain electrode of grid and the tenth transistor couples；
The drain electrode of tenth transistor is the second output terminal of first logic unit, the with second control unit
The coupling of the second output terminal of one output end and the latch；Source level is the second input terminal of first logic unit, with
The second output terminal of second control unit couples；The drain electrode of grid and the 9th transistor couples；
The drain electrode of 11st transistor is the first output end of second logic unit, with the third control unit
The coupling of first output end of the first output end and the latch；Source level is the first input end of second logic unit,
It is coupled with the second output terminal of the third control unit；The drain electrode of grid and the tenth two-transistor couples；
The drain electrode of tenth two-transistor is the second output terminal of second logic unit, with the 4th control unit
The coupling of the second output terminal of first output end and the latch；Source level is the second input terminal of second logic unit,
It is coupled with the second output terminal of the 4th control unit；The drain electrode of grid and the 11st transistor couples.
6. latch as claimed in claim 5, which is characterized in that the first control unit includes：First switch, third are opened
Pass, the 9th switch, the first transistor and the 5th transistor, wherein：
The clock signal input terminal of the first end of the first switch and the first control unit couples, second end and described the
The first end coupling of the grid of one transistor and third switch；
The second end and supply coupling of the third switch；
The first transistor is NMOS tube, and the source level and ground wire of the first transistor couple, drain electrode and the 9th crystal
The source level of pipe couples；
The first end of 9th switch and the control terminal of the first control unit couple, second end and the 5th transistor
Grid coupling；
5th transistor is NMOS tube, and the source electrode of the 5th transistor and the source electrode of the 9th transistor couple, make
For the second output terminal of the first control unit；Drain electrode is coupled with the drain electrode of the 9th transistor, and with the latch
The first output end coupling.
7. latch as claimed in claim 5, which is characterized in that second control unit includes：Second switch, the 4th open
Pass, the tenth switch, second transistor and the 6th transistor, wherein：
The clock signal input terminal of the first end of the second switch and second control unit couples, second end and described the
The first end coupling of the grid of two-transistor and the 4th switch；
The second end and supply coupling of 4th switch；
The second transistor is NMOS tube, and the source level and ground wire of the second transistor couple, drain electrode and the tenth crystal
The source level of pipe couples；
The first end of tenth switch and the control terminal of second control unit couple, second end and the 6th transistor
Grid coupling；
6th transistor is NMOS tube, and the source electrode of the 6th transistor and the source electrode of the tenth transistor couple, make
For the second output terminal of second control unit；Drain electrode is coupled with the drain electrode of the tenth transistor, and with the latch
Second output terminal coupling.
8. latch as claimed in claim 5, which is characterized in that the third control unit includes：5th switch, the 7th open
Pass, the 17th switch, third transistor and the 7th transistor, wherein：
The first end of 5th switch and the clock signal input terminal of the third control unit couple, second end and described the
The first end coupling of the grid of three transistors and the 7th switch；
The second end and ground wire of 7th switch couple；
The third transistor is PMOS tube, the source level and supply coupling of the third transistor, drain electrode and the 11st crystalline substance
The source level of body pipe couples；
The first end of 17th switch and the control terminal of the third control unit couple, second end and the 7th crystal
The grid of pipe couples；
7th transistor is PMOS tube, and the source electrode of the 7th transistor and the source electrode of the 11st transistor couple,
Second output terminal as the third control unit；Drain electrode is coupled with the drain electrode of the 11st transistor, and with the lock
First output end of storage couples.
9. latch as claimed in claim 5, which is characterized in that the 4th control unit includes：6th switch, the 8th open
Pass, eighteenmo pass, the 4th transistor and the 8th transistor, wherein：
The first end of 6th switch and the clock signal input terminal of the 4th control unit couple, second end and described the
The first end coupling of the grid of four transistors and the 8th switch；
The second end and ground wire of 8th switch couple；
4th transistor is PMOS tube, the source level and supply coupling of the 4th transistor, drain electrode and the 12nd crystalline substance
The source level of body pipe couples；
The control terminal of first end and the 4th control unit that the eighteenmo closes couples, second end and the 8th crystal
The grid of pipe couples；
8th transistor is PMOS tube, and the source electrode of the 8th transistor and the source electrode of the tenth two-transistor couple,
Second output terminal as the 4th control unit；Drain electrode is coupled with the drain electrode of the tenth two-transistor, and with the lock
The second output terminal of storage couples.
10. latch as claimed in claim 5, which is characterized in that the first control unit includes：First switch, third
Switch, the 9th switch, the 11st switch, the 13rd switch, the 15th switch, the first transistor and the 5th transistor, wherein：
The first transistor and the 5th transistor are NMOS tube,
The clock signal input terminal of the first end of the first switch and the first control unit couples, second end and described the
The first end coupling of the grid of one transistor and third switch；The second end and supply coupling of the third switch；
The source level and ground wire of the first transistor couple, and drain electrode is opened with the source level of the 9th transistor and the described 15th
The first end of pass couples；
The first end of 9th switch and the first input end of the latch couple, second end and the 5th transistor
The second end coupling of grid and the 11st switch；The first end and ground wire of 11st switch couple；
The first end of 13rd switch and the drain electrode of the 5th transistor couple, and the first of second end and the latch
The drain electrode of output end and the 9th transistor couples；
The drain electrode of the source level and the first transistor of the first end and the 9th transistor of 15th switch couples,
The source level of second end and the 5th transistor couples.
11. latch as claimed in claim 5, which is characterized in that the second control unit includes：Second switch, the 4th switch,
Tenth switch, the 12nd switch, the 14th switch, sixteenmo pass, second transistor and the 6th transistor, wherein：It is described
Second transistor and the 6th transistor are NMOS tube, the first end of the second switch and second control unit
Clock signal input terminal coupling, the first end coupling of the grid of second end and the second transistor and the 4th switch
It connects；The second end and supply coupling of 4th switch；
The source level and ground wire of the second transistor couple, the source level and the sixteenmo of drain electrode and the tenth transistor
The first end of pass couples；
The first end of tenth switch and the second input terminal of the latch couple, second end and the 6th transistor
The second end coupling of grid and the 12nd switch；The first end and ground wire of 12nd switch couple；
The first end of 14th switch and the drain electrode of the 6th transistor couple, and the second of second end and the latch
The drain electrode of output end and the tenth transistor couples；
The drain electrode of the source level and the second transistor of first end and the tenth transistor that the sixteenmo closes couples,
The source level of second end and the 6th transistor couples.
12. latch as claimed in claim 5, which is characterized in that third control unit includes：5th switchs, the 7th switchs,
17th switch, the 19th switch, the 21st switch, the 23rd switch, third transistor and the 7th transistor,
In：The third transistor and the 7th transistor are PMOS tube,
The first end of 5th switch and the clock signal input terminal of the third control unit couple, second end and described the
The first end coupling of the grid of three transistors and the 7th switch；The second end and ground wire of 7th switch couple；
The source level and supply coupling of the third transistor, the source level and the described 20th of drain electrode and the 11st transistor
The first end coupling of one switch；
The first end of 17th switch and the first input end of the latch couple, second end and the 7th transistor
Grid and it is described 19th switch second end coupling；The first end and supply coupling of 19th switch；
The first end of 21st switch and the drain electrode of the 7th transistor couple, and the of second end and the latch
The drain electrode of one output end and the 11st transistor couples；
The first end and the source level of the 11st transistor and the drain electrode of the third transistor of 23rd switch
The source level of coupling, second end and the 7th transistor couples.
13. latch as claimed in claim 5, which is characterized in that the 4th control unit includes：6th switch, the 8th
Switch, eighteenmo pass, the 20th switch, the 22nd switch, the 24th switch, the 4th transistor and the 8th crystal
Pipe, wherein：4th transistor and the 8th transistor are PMOS tube,
The first end of 6th switch and the clock signal input terminal of the 4th control unit couple, second end and described the
The first end coupling of the grid of four transistors and the 8th switch；The second end and ground wire of 8th switch couple；
The source level and supply coupling of 4th transistor, the source level and the described 20th of drain electrode and the tenth two-transistor
The first end coupling of two switches；
Second input terminal of first end and the latch that the eighteenmo closes couples, second end and the 8th transistor
Grid and it is described 20th switch second end coupling；The first end and supply coupling of 20th switch；
The first end of 22nd switch and the drain electrode of the 8th transistor couple, and the of second end and the latch
The drain electrode of two output ends and the tenth two-transistor couples；
The drain electrode of the source level and the 4th transistor of the first end and the tenth two-transistor of 24th switch
The source level of coupling, second end and the 8th transistor couples.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510372875.9A CN106330177B (en) | 2015-06-30 | 2015-06-30 | latch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510372875.9A CN106330177B (en) | 2015-06-30 | 2015-06-30 | latch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106330177A CN106330177A (en) | 2017-01-11 |
| CN106330177B true CN106330177B (en) | 2018-11-27 |
Family
ID=57722924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510372875.9A Active CN106330177B (en) | 2015-06-30 | 2015-06-30 | latch |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106330177B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098488A (en) * | 2021-03-31 | 2021-07-09 | 上海移芯通信科技有限公司 | Latch unit and frequency divider |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200601699A (en) * | 2004-02-05 | 2006-01-01 | Koninkl Philips Electronics Nv | Latch circuit |
| CN101213749A (en) * | 2005-06-30 | 2008-07-02 | 皇家飞利浦电子股份有限公司 | Multi-bit programmable frequency divider |
| CN101682298A (en) * | 2007-05-08 | 2010-03-24 | Nxp股份有限公司 | Calibration-free local oscillator signal generation for a harmonic-rejection mixer |
| CN102201808A (en) * | 2010-03-24 | 2011-09-28 | 联发科技股份有限公司 | Frequency divider |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100358118B1 (en) * | 2000-06-08 | 2002-10-25 | 한국전자통신연구원 | Phase locked loop having high-speed locking |
| FR2961978B1 (en) * | 2010-06-25 | 2013-11-22 | St Microelectronics Sa | BISTABLE CIRCUIT IN CML LOGIC |
-
2015
- 2015-06-30 CN CN201510372875.9A patent/CN106330177B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200601699A (en) * | 2004-02-05 | 2006-01-01 | Koninkl Philips Electronics Nv | Latch circuit |
| CN101213749A (en) * | 2005-06-30 | 2008-07-02 | 皇家飞利浦电子股份有限公司 | Multi-bit programmable frequency divider |
| CN101682298A (en) * | 2007-05-08 | 2010-03-24 | Nxp股份有限公司 | Calibration-free local oscillator signal generation for a harmonic-rejection mixer |
| CN102201808A (en) * | 2010-03-24 | 2011-09-28 | 联发科技股份有限公司 | Frequency divider |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106330177A (en) | 2017-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104009736B (en) | Low-power consumption master-slave flip-flop | |
| CN105471412B (en) | Integrated clock gating cell using low area and low power latches | |
| KR102216981B1 (en) | Spin logic device and method of operating the same | |
| CN109379061A (en) | TSPC trigger with set function | |
| CN106877868A (en) | A kind of high speed gradual approaching A/D converter | |
| CN108806583A (en) | Shift register cell, driving method, shift register and display device | |
| US8324932B2 (en) | High-speed static XOR circuit | |
| CN103312326B (en) | There is the digital to analog converter current unit exporting impedance-compensated auxiliary differential transistor | |
| CN106330177B (en) | latch | |
| CN104901681B (en) | A kind of pressure-resistant CMOS of VDD 2VDD level shifting circuits | |
| CN105634464B (en) | Latch and frequency divider | |
| CN106452395A (en) | Multi-clock distribution circuit and electronic device | |
| CN105790755B (en) | A kind of programmable user register circuit that single-particle is reinforced | |
| CN105634465A (en) | Latch and frequency divider | |
| CN104300508B (en) | Tandem cell protection circuit and system | |
| CN104660222B (en) | The d type flip flop and five frequency dividing circuits of a kind of current switching formula | |
| CN204242561U (en) | Gate driver circuit and display device | |
| CN106330176B (en) | Latch and frequency divider | |
| WO2023024805A1 (en) | Level shift circuit and electronic device | |
| CN100452696C (en) | Multi-spiral chaos generator | |
| CN108649931A (en) | A kind of adjustable high-speed level shifter circuit of duty ratio | |
| CN114567296A (en) | Circuit unit, logic circuit, processor and computing device | |
| CN104362848B (en) | Charge pump apparatus and its control method | |
| CN107528580B (en) | Level conversion circuit | |
| CN105048998B (en) | Redundancy clock changes tolerance latch cicuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |