CN204242561U - Gate driver circuit and display device - Google Patents
Gate driver circuit and display device Download PDFInfo
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- CN204242561U CN204242561U CN201420736019.8U CN201420736019U CN204242561U CN 204242561 U CN204242561 U CN 204242561U CN 201420736019 U CN201420736019 U CN 201420736019U CN 204242561 U CN204242561 U CN 204242561U
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Abstract
The utility model relates to display technique field, disclose a kind of gate driver circuit, comprise some element circuits, each element circuit comprises: high level end, low level end, the first clock end, second clock end, gate output terminal, logic are opened and opened output terminal, control module, the first gating module and the second gating module into end, logic.Also disclose a kind of display device comprising above-mentioned gate driver circuit.The utility model is under the condition keeping original two sequential, and the gate driver circuit that the interlacing realizing not existing between interlacing sequential vacant state exports, namely eliminates the vacant state in the middle of two interlacing, ensure that the stable output of shift register.
Description
Technical field
The utility model relates to display technique field, particularly a kind of gate driver circuit and display device.
Background technology
In current OLED design, signal exports to be needed to use interlacing export structure, like this in the shift register of existing (signal of existing gate driver circuit exports line by line) two clock controls, can at n capable and n+2 capable between there is the vacant state of a sequential (can when a certain sequential in circuit structure, current potential on Key Circuit node does not have direct signal to input, so now this node potential is in vacant state), cause shift register output bad stability.
As shown in Figure 1, be the shift register structure that a kind of simple three clock signals existed at present control, Fig. 2 is the GOA clocked sequential of its work.The principle of work of this structure is as follows, the course of work of this shift register is divided into 4 parts, specifically can referring to shown in shift register sequential chart 2.
First stage: CLK is low-pressure opening signal, and transistor M23 and M21 opens, and after M23 opens, STV low-voltage signal now reaches Node B by M23, and the M22 made opens, and makes the high pressure shutdown signal of now CLKB output to the output terminal OUT of shift register; B point also control transistor M12 simultaneously, makes node C be filled with high pressure VGH signal; After transistor M21 opens, low pressure VGL signal arrives node A by M21 makes M19 open, and high pressure VGH signal also outputs to the OUT output terminal of shift register by M19.
Second stage, CLK closes, and CLKB becomes low-voltage signal, is now kept at the low-voltage signal of Node B or M22 keeps and M12 is held open state.The unlatching of M22 makes the low-voltage signal of CLKB output to the output terminal OUT of shift register; The unlatching of M12 makes VGH continue to be input to node C, and the M20 controlled by CLKB now opens, and makes the VGH signal of node C be input to node A, makes M19 discrepancy closed condition, not affect output terminal OUT.
Three phases, CLK is low-voltage signal, and CLKB is high-voltage signal.CLK low-voltage signal makes M23 and M21 open, after M23 opens, the STV signal now becoming high pressure arrives Node B by M23, M22 and M12 is closed, and the unlatching of M21 makes VGL signal output to node A, M19 is opened again, high pressure VGH is input to the output terminal OUT of shift register.
Four-stage, CLKB is low-voltage signal, and CLK is high-voltage signal.When CLK is high-voltage signal, M21 closes, CLKB makes M20 open simultaneously, the current potential (VGL of three phases remain) of the current potential (VGH of second stage remains) of flaoating nodes C with flaoating nodes A is disturbed mutually, thus affect the opening of M19, thus affect the output OUT signal of now shift register, make output signal unstable.
Carry out interlacing output according to existing shift register as seen, can at n capable and n+2 capable between there is the vacant state of a sequential, output stability is deteriorated.
Utility model content
(1) technical matters that will solve
The technical problems to be solved in the utility model is: the gate driver circuit that the interlacing how realizing not existing between interlacing sequential vacant state exports.
(2) technical scheme
For solving the problems of the technologies described above, the utility model provides a kind of gate driver circuit, comprise some element circuits, each element circuit comprises: high level end, low level end, the first clock end, second clock end, gate output terminal, logic open input end, logic unlatching output terminal, control module, the first gating module and the second gating module;
Described control module connects described high level end, the first clock end, second clock end, logic unlatching input end, the first gating module and the second gating module; Described first gating module connects described low level end and described gate output terminal; Described second gating module connects described low level end and described logic opens output terminal; The logic of the logic unlatching output terminal connection of element circuit at the corresponding levels and the element circuit of described element circuit interval at the corresponding levels one-level opens input end; Described gate output terminal is for connecting grid line;
Described control module is used for opening input end control the high level signal of described first gating module gating from high level end to described gate output terminal according to described first clock end, second clock end, logic, or gating is from the low level signal extremely described gate output terminal of low level end;
Described control module also for open according to described first clock end, second clock end, logic input end control described second gating module only when described first clock end effective time sequence status gating open output terminal from the low level signal of low level end to described logic, the logic making low level signal transfer to the element circuit of interlacing opens input end, export to open interlacing, all the other time sequence status gatings open output terminal from the high level signal of high level end to described logic.
Wherein, described control module comprises: the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 8th transistor, the first electric capacity and the second electric capacity;
The grid of described the first transistor connects described first clock end, and source electrode connects described logic and opens input end, and drain electrode connects the grid of described third transistor;
The grid of described transistor seconds is connected described first clock end with source electrode, drain electrode connects the source electrode of described third transistor;
The drain electrode of described third transistor connects described high level end;
The grid of described 4th transistor connects the drain electrode of described third transistor, and source electrode connects the drain electrode of described 5th transistor, and drain electrode connects described high level end;
The grid of described 5th transistor connects the drain electrode of described the first transistor, second clock end described in source electrode;
The grid of described 8th transistor connects described second clock end, and source electrode connects described second gating module, and drain electrode connects the source electrode of described 4th transistor;
The first end of described first electric capacity connects described high level end, and the second end connects the grid of described 4th transistor;
The first end of described second electric capacity connects the drain electrode of described 5th transistor, and the second end connects the grid of described 5th transistor;
Described the first transistor is used for, under the control of described first clock end, institute's logic is opened the Signal transmissions of input end to described third transistor and the 5th transistor grid separately, and gives described second capacitor charging; Described transistor seconds and described third transistor shape imaging unit structure, described inverter structure for controlling opening or closing of described 4th transistor, and to described first capacitor charging; The voltage of described first electric capacity for making the grid of the 4th transistor remain the first electric capacity; The voltage of described second electric capacity for making the grid of the grid of third transistor and the 5th transistor remain the second electric capacity respectively; Described 4th transistor is used for, when it is opened, the high level signal of described high level end is transferred to the first gating module; Described 4th transistor is used for the Signal transmissions of described high level end to the drain electrode of described first gating module and described 8th transistor; Described 5th transistor is used for the Signal transmissions of described second clock end to the drain electrode of described first gating module and described 8th transistor; The Signal transmissions that described 8th transistor is used for the 4th transistor and the 5th transistor being transmitted under the control of second clock end is to described second gating module.
Wherein, described first gating module comprises: the 6th transistor and the 7th transistor;
The grid of described 6th transistor connects the source electrode of described 4th transistor, and source electrode connects described gate output terminal, and drain electrode connects described high level end;
The grid of described 7th transistor is connected described low level end with source electrode, and drain electrode connects described gate output terminal;
Described 6th transistor is used for the Signal transmissions of described high level end extremely described gate output terminal under the control of the signal coming extremely described 4th transistor or the 5th transistor; Described 7th transistor is used for the Signal transmissions of low level end extremely described gate output terminal when described 6th transistor turns off.
Wherein, described second gating module comprises: the 9th transistor, the tenth transistor, the 11 transistor and the 3rd electric capacity;
The grid of described 9th transistor connects gate output terminal, and source electrode connects the drain electrode of described 11 transistor, and drain electrode connects described low level end;
The grid of described tenth transistor is connected described logic with drain electrode and opens output terminal, and source electrode connects described high level end;
The grid of described 11 transistor connects the source electrode of described 8th transistor, and source electrode connects described logic and opens output terminal, and drain electrode connects the source electrode of described 9th transistor;
The first end of described 3rd electric capacity connects the grid of described 11 transistor, and the second end connects described logic and opens output terminal;
Described 8th transistor also for Signal transmissions that the 4th transistor and the 5th transistor are transmitted to described 3rd electric capacity, with to described 3rd capacitor charging, the voltage of described 3rd electric capacity for making the grid of described 11 transistor keep the 3rd electric capacity; Only when described first clock end is effective time sequence status, described 9th transistor and the 11 transistor are used for the Signal transmissions of low level end to open output terminal to described logic, and the tenth transistor described in during all the other time sequence status is used for the Signal transmissions of high level end to open output terminal to described logic.
The utility model additionally provides a kind of display device, comprises the gate driver circuit described in above-mentioned any one.
(3) beneficial effect
The utility model opens input end by logic and logic opens the unlatching that output terminal carrys out the element circuit (shift register) of control interval a line, thus under the condition keeping original two sequential, the gate driver circuit that the interlacing realizing not existing between interlacing sequential vacant state exports, namely eliminate the vacant state in the middle of two interlacing, ensure that the stable output of shift register.
Accompanying drawing explanation
Fig. 1 is the structural representation of an element circuit of a kind of gate driver circuit of prior art;
Fig. 2 is the sequential chart of input signal and output signal in Fig. 1 circuit;
Fig. 3 is the structural representation of an element circuit of a kind of gate driver circuit of the utility model embodiment;
Fig. 4 is the sequential chart of input signal and output signal in Fig. 3 circuit.
Embodiment
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.Following examples for illustration of the utility model, but are not used for limiting scope of the present utility model.
The grid electrode drive circuit structure of the utility model embodiment comprises some element circuits (i.e. a shift register) as shown in Figure 3, and each element circuit comprises: high level end VGH, low level end VGL, the first clock end CLK1, second clock end CLK2, gate output terminal OUT_PUT, logic open input end STV, logic unlatching output terminal NEXT_STV, control module, the first gating module and the second gating module.
Described control module connects described high level end VGH, the first clock end CLK1, second clock end CLK2, logic unlatching input end STV, the first gating module and the second gating module; Described first gating module connects described low level end VGL and described gate output terminal OUT_PUT; Described second gating module connects described low level end VGL and described logic opens output terminal NEXT_STV; The logic of the logic unlatching output terminal NEXT_STV connection of element circuit at the corresponding levels and the element circuit of described element circuit interval at the corresponding levels one-level opens input end STV; Described gate output terminal OUT_PUT is for connecting grid line, and the logic of certain first order element circuit opens the signal source that input end STV is connected to logic unlatching.
Described control module is used for opening input end STV control the high level signal of described first gating module gating from high level end VGH to described gate output terminal OUT_PUT according to described first clock end, second clock end CLK2, logic, or gating is from the low level signal extremely described gate output terminal OUT_PUT of low level end VGL.
Described control module also for open according to described first clock end CLK1, second clock end CLK2, logic input end STV control described second gating module only when described first clock end CKL1 effective time sequence status gating open output terminal NEXT_STV from the low level signal of low level end VGL to described logic, the logic making low level signal transfer to the element circuit of interlacing opens input end STV, export to open interlacing, all the other time sequence status gatings open output terminal NEXT_STV from the high level signal of high level end VGL to described logic.
In the present embodiment, described control module comprises: the first transistor M1, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 8th transistor M8, the first electric capacity C1 and the second electric capacity C2.
The grid of described the first transistor M1 connects described first clock end CLK1, and source electrode connects described logic and opens input end STV, and drain electrode connects the grid of described third transistor M3;
The grid of described transistor seconds M2 is connected described first clock end CLK1 with source electrode, drain electrode connects the source electrode of described third transistor M3.
The drain electrode of described third transistor M3 connects described high level end VGH.
The grid of described 4th transistor M4 connects the drain electrode of described third transistor M3, and source electrode connects the drain electrode of described 5th transistor M5, and drain electrode connects described high level end VGH.
The grid of described 5th transistor M5 connects the drain electrode of described the first transistor M1, second clock end CLK2 described in source electrode.
The grid of described 8th transistor M8 connects described second clock end CLK2, and source electrode connects described second gating module, and drain electrode connects the source electrode of described 4th transistor M4.
The first end of described first electric capacity C1 connects described high level end VGH, and the second end connects the grid of described 4th transistor M4.
The first end of described second electric capacity C2 connects the drain electrode of described 5th transistor M5, and the second end connects the grid of described 5th transistor M5.
Described the first transistor M1 is used for, under the control of described first clock end CLK1, institute's logic is opened the Signal transmissions of input end STV to described third transistor M3 and the 5th transistor M5 grid separately, and charges to described second electric capacity C2; Described transistor seconds M2 and described third transistor M3 shape imaging unit structure, described inverter structure for controlling opening or closing of described 4th transistor M4, and charges to described first electric capacity C1; The voltage of described first electric capacity C1 for making the grid of the 4th transistor M4 remain the first electric capacity C1; The voltage of described second electric capacity C2 for making the grid of the grid of third transistor M3 and the 5th transistor M5 remain the second electric capacity C2 respectively; Described 4th transistor M4 is used for, when it is opened, the high level signal of described high level end VGH is transferred to the first gating module; Described 4th transistor M4 is used for the Signal transmissions of described high level end VGH to the drain electrode of described first gating module and described 8th transistor M8; Described 5th transistor M5 is used for the Signal transmissions of described second clock end CLK2 to the drain electrode of described first gating module and described 8th transistor M8; The Signal transmissions that described 8th transistor M8 is used for being transmitted by the 4th transistor M4 and the 5th transistor M5 under the control of second clock end CLK2 is to described second gating module.
In the present embodiment, described first gating module comprises: the 6th transistor M6 and the 7th transistor M7.
The grid of described 6th transistor M6 connects the source electrode of described 4th transistor M4, and source electrode connects described gate output terminal OUT_PUT, and drain electrode connects described high level end VGH.
The grid of described 7th transistor M7 is connected described low level end VGL with source electrode, and drain electrode connects described gate output terminal OUT_PUT.
Described 6th transistor M6 is used for coming the Signal transmissions of described high level end VGH extremely described gate output terminal OUT_PUT to the control of the signal of described 4th transistor M4 or the 5th transistor M5; Described 7th transistor M7 is used for the Signal transmissions of low level end VGL extremely described gate output terminal OUT_PUT when described 6th transistor M6 turns off.
In the present embodiment, described second gating module comprises: the 9th transistor M9, the tenth transistor M10, the 11 transistor M11 and the 3rd electric capacity C3.
The grid of described 9th transistor M9 connects gate output terminal OUT_PUT, and source electrode connects the drain electrode of described 11 transistor M11, and drain electrode connects described low level end VGL.
The grid of described tenth transistor M10 is connected described logic with drain electrode and opens output terminal NEXT_STV, and source electrode connects described high level end VGH.
The grid of described 11 transistor M11 connects the source electrode of described 8th transistor M8, and source electrode connects described logic and opens output terminal NEXT_STV, and drain electrode connects the source electrode of described 9th transistor M9.
The first end of described 3rd electric capacity C3 connects the grid of described 11 transistor M11, and the second end connects described logic and opens output terminal NEXT_STV.
The Signal transmissions extremely described three electric capacity C3 of described 8th transistor M8 also for the 4th transistor M4 and the 5th transistor M5 is transmitted, to charge to described 3rd electric capacity C3, the voltage of described 3rd electric capacity C3 for making the grid of described 11 transistor M11 keep the 3rd electric capacity C3; Only when the first clock end is effective time sequence status, described 9th transistor M9 and the 11 transistor M11 is used for the Signal transmissions of low level end VGL to open output terminal NEXT_STV to described logic, and the tenth transistor M10 described in when all the other time sequence status is used for the Signal transmissions of high level end VGH to open output terminal NEXT_STV to described logic.
As shown in Figure 4, wherein the grid start signal of each transistor is low level signal (Low level effective) to the gate driver circuit working timing figure of the utility model embodiment, and shutdown signal is high level signal, and circuit working principle is as follows:
First stage a:CLK1 and STV is start signal, and CLK2 is shutdown signal.When CLK1 is start signal, transistor M1 opens, and respective grid STV start signal being transferred to transistor M3 and M5 makes M3 and M5 open, and to electric capacity C2 to carry out charging and keeping.The unlatching of M3, VGH Signal transmissions to the grid of transistor M4, makes transistor M4 close by the phase inverter that M2 and M3 is formed.Simultaneously the unlatching of M5, transfers to the grid of M6, makes by the phase inverter that M6 and M7 is formed by the shutdown signal of CLK2, by transistor M7 low level signal is transferred to OUT_PUT and outputs to the grid line be connected with this OUT_PUT.Simultaneously because now CLK2 is shutdown signal, transistor M8 is turned off, the inverter structure be now made up of transistor M10 and M11 is (namely when M11 is in closed condition, M10 is just in opening always, what export is high level shutdown signal, ensure that NEXT_STV only has the low level of a line with this, all the other are all high level outputs) in, by transistor M10, high level shutdown signal is transferred to NEXT_STV end, wherein this NEXT_STV signal end is the STV end of interlacing shift register therewith.
Subordinate phase b:CLK2 is start signal, CLK1 and STV becomes shutdown signal.Now at the grid of transistor M3 and M5, low level start signal when still remain the first stage by electric capacity C2.The wherein unlatching of M3, in the phase inverter form, makes M2 and M3 M4 close VGH Signal transmissions to the grid of transistor M4 by M3, and is undertaken charging and keeping by electric capacity C1.。The unlatching of transistor M5, transfers to the grid of transistor M6 by the low level signal of now CLK2, M6 opens, and makes by the phase inverter of transistor M6 and M7, is exported by the VGH Signal transmissions by M6 to OUT_PUT.The transistor M8 that CLK2 controls simultaneously opens, and by the CLK2 low level signal by M5, is input to the grid of M11 by M8, and charges and keep to electric capacity C3.Now in the gate be made up of M9, M10, M11, because M9 grid is shutdown signal, so the VGH high level signal by M10 transfers on NEXT_STV by gate.
Phase III c:CLK1 is start signal, CLK2 and STV is shutdown signal.When CLK1 is start signal, transistor M1 is opened, the shutdown signal of STV is transferred to the grid of transistor M3 and M5, and charge to electric capacity C2.The shutdown signal of STV makes transistor M5 and M3 be in closed condition.In the phase inverter be now made up of transistor M2 and M3, the low level signal through M2 is transferred to the grid of transistor M4, and kept by electric capacity C1.Transistor M4 opens by this signal, by VGH Signal transmissions to transistor M6 grid, makes, in the inverter structure be made up of transistor M6 and M7, the low level signal through M7 is transferred to OUT_PUT and exports.Simultaneously because CLK2 is shutdown signal, transistor M8 is made to be in closed condition.Now by transistor M9, M10, in the gate that M11 is formed, signal due to M11 passes through the low level signal that electric capacity C3 keeps subordinate phase, M11 opens, the OUT_PUT end that the grid of M9 connects simultaneously is low level signal, M9 is opened, in such gate, M9 and M11 opens simultaneously, VGL low level signal is transferred to NEXT_STV, so just, achieve the NEXT_STV signal with CLK2 synchronism output in available circuit, become the NEXT_STV signal controlled by the CLK1 of interlacing, achieve the condition precedent that interlacing exports.
Fourth stage d:CLK2 start signal, CLK1 and STV is shutdown signal.Still kept the high level current potential of phase III by electric capacity C2 at the grid of transistor M3 and M5, M3 and M5 closes.The low level that phase III C1 keeps makes M4 open, and VGH Signal transmissions to M6 grid, makes, by the phase inverter that M6 and M7 is formed, the low level signal by M7 is transferred to OUT_PUT and exports by M4.The transistor M8 that CLK2 controls simultaneously opens, and by the VGH signal through M4, transfers to the grid of M11, and to electric capacity C3 to carry out charging and keeping.Like this at gate M9, in the structure of M10, M11, due to the closedown of M11, make this structure that the high level signal through M10 is transferred to NEXT_STV.
Like this in each sequential section of remainder, because the grid of transistor M6 inputs shutdown signal always, so just ensure that gate M9, M10 and M11 export high level signal to NEXT_STV always, ensure the output of interlace signal.
The utility model opens input end by logic and logic opens the unlatching that output terminal carrys out the element circuit (shift register) of control interval a line, thus under the condition keeping original two sequential, achieve the gate driver circuit that interlacing exports, can find out that capable at n of n+2 does not exist (the output that the OUT_PUT that in Fig. 4, n-th line output is element circuit (i.e. shift register) in Fig. 3 holds of sequential vacant state between capable in conjunction with above-mentioned principle of work, the output that the output of the n-th+2 row is and in Fig. 3, the OUT_PUT of the shift register of interval a line holds), namely the vacant state in the middle of two interlacing is eliminated, ensure that the stable output of shift register.
The utility model additionally provides a kind of display device comprising above-mentioned gate driver circuit, and this display device can be: any product or parts with Presentation Function such as oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Above embodiment is only for illustration of the utility model; and be not limitation of the utility model; the those of ordinary skill of relevant technical field; when not departing from spirit and scope of the present utility model; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present utility model, and scope of patent protection of the present utility model should be defined by the claims.
Claims (5)
1. a gate driver circuit, comprise some element circuits, it is characterized in that, each element circuit comprises: high level end, low level end, the first clock end, second clock end, gate output terminal, logic are opened and opened output terminal, control module, the first gating module and the second gating module into end, logic;
Described control module connects described high level end, the first clock end, second clock end, logic unlatching input end, the first gating module and the second gating module; Described first gating module connects described low level end and described gate output terminal; Described second gating module connects described low level end and described logic opens output terminal; The logic of the logic unlatching output terminal connection of element circuit at the corresponding levels and the element circuit of described element circuit interval at the corresponding levels one-level opens input end; Described gate output terminal is for connecting grid line;
Described control module is used for opening input end control the high level signal of described first gating module gating from high level end to described gate output terminal according to described first clock end, second clock end, logic, or gating is from the low level signal extremely described gate output terminal of low level end;
Described control module also for open according to described first clock end, second clock end, logic input end control described second gating module only when described first clock end effective time sequence status gating open output terminal from the low level signal of low level end to described logic, the logic making low level signal transfer to the element circuit of interlacing opens input end, export to open interlacing, all the other time sequence status gatings open output terminal from the high level signal of high level end to described logic.
2. gate driver circuit as claimed in claim 1, it is characterized in that, described control module comprises: the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 8th transistor, the first electric capacity and the second electric capacity;
The grid of described the first transistor connects described first clock end, and source electrode connects described logic and opens input end, and drain electrode connects the grid of described third transistor;
The grid of described transistor seconds is connected described first clock end with source electrode, drain electrode connects the source electrode of described third transistor;
The drain electrode of described third transistor connects described high level end;
The grid of described 4th transistor connects the drain electrode of described third transistor, and source electrode connects the drain electrode of described 5th transistor, and drain electrode connects described high level end;
The grid of described 5th transistor connects the drain electrode of described the first transistor, second clock end described in source electrode;
The grid of described 8th transistor connects described second clock end, and source electrode connects described second gating module, and drain electrode connects the source electrode of described 4th transistor;
The first end of described first electric capacity connects described high level end, and the second end connects the grid of described 4th transistor;
The first end of described second electric capacity connects the drain electrode of described 5th transistor, and the second end connects the grid of described 5th transistor;
Described the first transistor is used for, under the control of described first clock end, institute's logic is opened the Signal transmissions of input end to described third transistor and the 5th transistor grid separately, and gives described second capacitor charging; Described transistor seconds and described third transistor form inverter structure, described inverter structure for controlling opening or closing of described 4th transistor, and to described first capacitor charging; The voltage of described first electric capacity for making the grid of the 4th transistor remain the first electric capacity; The voltage of described second electric capacity for making the grid of the grid of third transistor and the 5th transistor remain the second electric capacity respectively; Described 4th transistor is used for, when it is opened, the high level signal of described high level end is transferred to the first gating module; Described 4th transistor is used for the Signal transmissions of described high level end to the drain electrode of described first gating module and described 8th transistor; Described 5th transistor is used for the Signal transmissions of described second clock end to the drain electrode of described first gating module and described 8th transistor; The Signal transmissions that described 8th transistor is used for the 4th transistor and the 5th transistor being transmitted under the control of second clock end is to described second gating module.
3. gate driver circuit as claimed in claim 2, it is characterized in that, described first gating module comprises: the 6th transistor and the 7th transistor;
The grid of described 6th transistor connects the source electrode of described 4th transistor, and source electrode connects described gate output terminal, and drain electrode connects described high level end;
The grid of described 7th transistor is connected described low level end with source electrode, and drain electrode connects described gate output terminal;
Described 6th transistor is used for the Signal transmissions of described high level end extremely described gate output terminal under the control of the signal coming extremely described 4th transistor or the 5th transistor; Described 7th transistor is used for the Signal transmissions of low level end extremely described gate output terminal when described 6th transistor turns off.
4. gate driver circuit as claimed in claim 2, it is characterized in that, described second gating module comprises: the 9th transistor, the tenth transistor, the 11 transistor and the 3rd electric capacity;
The grid of described 9th transistor connects gate output terminal, and source electrode connects the drain electrode of described 11 transistor, and drain electrode connects described low level end;
The grid of described tenth transistor is connected described logic with drain electrode and opens output terminal, and source electrode connects described high level end;
The grid of described 11 transistor connects the source electrode of described 8th transistor, and source electrode connects described logic and opens output terminal, and drain electrode connects the source electrode of described 9th transistor;
The first end of described 3rd electric capacity connects the grid of described 11 transistor, and the second end connects described logic and opens output terminal;
Described 8th transistor also for Signal transmissions that the 4th transistor and the 5th transistor are transmitted to described 3rd electric capacity, with to described 3rd capacitor charging, the voltage of described 3rd electric capacity for making the grid of described 11 transistor keep the 3rd electric capacity; Only when described first clock end is effective time sequence status, described 9th transistor and the 11 transistor are used for the Signal transmissions of low level end to open output terminal to described logic, and the tenth transistor described in during all the other time sequence status is used for the Signal transmissions of high level end to open output terminal to described logic.
5. a display device, is characterized in that, comprises the gate driver circuit according to any one of Claims 1 to 4.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420736019.8U CN204242561U (en) | 2014-11-28 | 2014-11-28 | Gate driver circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420736019.8U CN204242561U (en) | 2014-11-28 | 2014-11-28 | Gate driver circuit and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332137A (en) * | 2014-11-28 | 2015-02-04 | 京东方科技集团股份有限公司 | Gate drive circuit and display device |
| CN109302057A (en) * | 2018-11-27 | 2019-02-01 | 珠海创飞芯科技有限公司 | One kind times source circuit, charge pump circuit and electronic equipment |
| WO2020206720A1 (en) * | 2019-04-08 | 2020-10-15 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display panel |
-
2014
- 2014-11-28 CN CN201420736019.8U patent/CN204242561U/en not_active Withdrawn - After Issue
Cited By (7)
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| CN104332137A (en) * | 2014-11-28 | 2015-02-04 | 京东方科技集团股份有限公司 | Gate drive circuit and display device |
| WO2016082374A1 (en) * | 2014-11-28 | 2016-06-02 | 京东方科技集团股份有限公司 | Gate drive circuit and display apparatus |
| CN104332137B (en) * | 2014-11-28 | 2016-11-16 | 京东方科技集团股份有限公司 | Gate driver circuit and display device |
| US9881559B2 (en) * | 2014-11-28 | 2018-01-30 | Boe Technology Group Co., Ltd. | Gate drive circuit and display device |
| CN109302057A (en) * | 2018-11-27 | 2019-02-01 | 珠海创飞芯科技有限公司 | One kind times source circuit, charge pump circuit and electronic equipment |
| CN109302057B (en) * | 2018-11-27 | 2020-02-11 | 珠海创飞芯科技有限公司 | Voltage-multiplying source circuit, charge pump circuit and electronic equipment |
| WO2020206720A1 (en) * | 2019-04-08 | 2020-10-15 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display panel |
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Granted publication date: 20150401 Effective date of abandoning: 20161116 |
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