CN109302057A - One kind times source circuit, charge pump circuit and electronic equipment - Google Patents
One kind times source circuit, charge pump circuit and electronic equipment Download PDFInfo
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- CN109302057A CN109302057A CN201811426789.1A CN201811426789A CN109302057A CN 109302057 A CN109302057 A CN 109302057A CN 201811426789 A CN201811426789 A CN 201811426789A CN 109302057 A CN109302057 A CN 109302057A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
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Abstract
This application discloses a kind of times source circuits, charge pump circuit and electronic equipment, wherein, described times of source circuit uses transmission transistor of the P-type transistor as voltage, and P-type transistor is using N trap as substrate, and N trap can connect any current potential above Ground, therefore the substrate of P-type transistor can directly be connect with the source electrode of P-type transistor, the source voltage for avoiding N-type transistor of the existing CMOS type times potential source due to playing voltage transfer function is higher than bulk effect caused by underlayer voltage, improve the efficiency of transistor transfer overvoltage, to improve the whole efficiency of times source circuit；And by giving the suitable dynamic bias circuit of P-type transistor gate design, based on the non-overlapping clock of two-phase orderly control the first transistor, second transistor, third transistor and the 4th transistor on and off, described times of source circuit can effectively avoid the current reflux problem that classical CMOS type times source circuit switching moments occur.
Description
Technical field
This application involves technical field of circuit design, more specifically to a kind of times source circuit, charge pump circuit and
Electronic equipment.
Background technique
Times source circuit refers to the circuit amplified to input voltage, under normal circumstances, the times magnification of times source circuit
Number is 2, i.e., such as input voltage of times source circuit is VDD, then by a times source circuit, treated that output voltage is then
2VDD。
Times source circuit is widely used in flash memory (Flash), dynamic random access memory (Dynamic Random
Access Memory, DRAM) and the chip of each class of electronic devices such as driving circuit of liquid crystal display in.Times source circuit
Efficiency directly affects the overall power consumption of the chip using times source circuit, in existing times of source circuit, due to transfer overvoltage
Transistor from preparation times source circuit wafer between doping type it is different, cause the substrate of transistor that can only be grounded, from
And make the source voltage of transistor be greater than basic voltage, therefore result in serious bulk effect, reduce these transistors biography
The efficiency for passing voltage thereby reduces the whole efficiency of times source circuit.
Summary of the invention
In order to solve the above technical problems, this application provides a kind of times source circuit, charge pump circuit and electronic equipment, with
Realize the purpose for promoting the efficiency of times source circuit.
To realize the above-mentioned technical purpose, the embodiment of the present application provides following technical solution:
A kind of times source circuit, comprising: the first transistor, second transistor, third transistor, the 4th transistor, first
Capacitor, the second capacitor, first choice biasing module, the second selection biasing module, the first clock module and second clock module；Its
In,
First clock module includes the first output terminal of clock and second clock output end, first output terminal of clock
For exporting the first clock signal, the second clock output end is for exporting second clock signal；
The second clock module includes third output terminal of clock and the 4th output terminal of clock, the third output terminal of clock
For exporting third clock signal, the 4th output terminal of clock is for exporting the 4th clock signal, first clock signal
With the timing of second clock signal on the contrary, the timing of the third clock signal and the 4th clock signal is on the contrary, when described first
The timing of clock signal and third clock signal is opposite；
The first choice biasing module includes first input end, the first output end and second output terminal, and described first is defeated
Entering end to connect with first output terminal of clock, first output end is connect with the grid of the first transistor, and described the
Two output ends are connect with one end of the source electrode of the first transistor and the first capacitor, and the first capacitor is far from described
One end of second output terminal is connect with the second clock output end；
The drain electrode of the first transistor connects the first power input；
The first choice biasing module is used in first clock signal be high level, and the second clock signal is
When low level, the first transistor is connected；It is low level in first clock signal, the second clock signal is high electricity
Usually, the first transistor is turned off；
The second selection biasing module includes the second input terminal, third output end and the 4th output end, and described second is defeated
Entering end to connect with the third output terminal of clock, the third output end is connect with the grid of the second transistor, and described the
Four output ends are connect with one end of the source electrode of the second transistor and second capacitor, and second capacitor is far from described
One end of 4th output end is connect with the 4th output terminal of clock；
The drain electrode of the second transistor connects second source input terminal；
Described second selects biasing module for being high level in the third clock signal, and the 4th clock signal is
When low level, the second transistor is connected；It is low level in the third clock signal, the 4th clock signal is high electricity
Usually, the second transistor is turned off；
The grid of the third transistor is connect with the second output terminal, and source electrode is connect with the 4th output end, leakage
Pole is connect with the drain electrode of the 4th transistor, as signal output end；
The grid of 4th transistor is connect with the 4th output end, and source electrode is connect with the second output terminal；
The first transistor, second transistor, third transistor and the 4th transistor are P-type transistor.
Optionally, the first choice biasing module includes: the 5th transistor and the 6th transistor；
The grid of 5th transistor and the grid of the 6th transistor are connected to the first input end, described
For receiving the first fixed current potential, the substrate of the 5th transistor is fixed for receiving described first for the drain electrode of 5th transistor
The source electrode of current potential, the 5th transistor is connect with the drain electrode of the 6th transistor, as first output end；
The substrate of 6th transistor is connect with the source electrode of the 6th transistor, as the second output terminal.
Optionally, the described first fixed current potential is low level or zero potential.
Optionally, the second selection biasing module includes: the 7th transistor and the 8th transistor；
The grid of 7th transistor and the grid of the 8th transistor are connected to the first input end, described
For receiving the second fixed current potential, the substrate of the 7th transistor is fixed for receiving described second for the drain electrode of 7th transistor
The source electrode of current potential, the 7th transistor is connect with the drain electrode of the 8th transistor, as first output end；
The substrate of 8th transistor is connect with the source electrode of the 8th transistor, as the second output terminal.
Optionally, the described second fixed current potential is low level or zero potential.
Optionally, first clock module is the first phase inverter；
The input terminal of first phase inverter is for receiving first clock signal, as first clock output
End；The output end of first phase inverter is as the second clock output end；
First phase inverter is used to export the second clock signal to after first clock signal processing.
Optionally, the second clock module is the second phase inverter；
The input terminal of second phase inverter is for receiving the third clock signal, as the third clock output
End；The output end of second phase inverter is as the 4th output terminal of clock；
Second phase inverter is used to export the 4th clock signal to after third clock signal processing.
Optionally, further includes: third capacitor；
One end of the third capacitor is connect with the drain electrode of the third transistor, another termination of the third capacitor
Ground.
A kind of charge pump circuit, including multiple times source circuits being sequentially connected in series, described times of source circuit is any of the above-described
Times source circuit described in.
A kind of electronic equipment, including as described in any one of the above embodiments times of source circuit.
It can be seen from the above technical proposal that the embodiment of the present application provide a kind of times source circuit, charge pump circuit and
Electronic equipment, wherein described times of source circuit uses the transmitting crystal of the first transistor and second transistor as input voltage
Pipe, using third transistor as first capacitor to the transmission transistor of the output voltage after input voltage multiplication of voltage, using the 4th
Transistor as the second capacitor to the transmission transistor of the output voltage after input voltage multiplication of voltage, and the first transistor, second
Transistor, third transistor and the 4th transistor are P-type transistor, and P-type transistor is using N trap as substrate, and N trap can be with
Any current potential above Ground is connected, therefore can directly can be connect with the source electrode of P-type transistor with the substrate of P-type transistor, is kept away
The source voltage for having exempted from N-type transistor of the existing CMOS type times potential source due to playing voltage transfer function is higher than underlayer voltage and leads
The bulk effect of cause improves the efficiency of transistor transfer overvoltage, to improve the whole efficiency of times source circuit.
It is orderly based on the non-overlapping clock of two-phase and by giving the suitable dynamic bias circuit of P-type transistor gate design
Control the first transistor, second transistor, third transistor and the 4th transistor on and off, described times of source circuit can be effective
The current reflux problem for avoiding classical CMOS type times source circuit switching moments from occurring.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the structural schematic diagram of in the prior art times of source circuit；
Fig. 2 is the time diagram of the non-overlapping clock signal of two-phase；
Fig. 3 is a kind of electrical block diagram for times source circuit that one embodiment of the application provides；
Fig. 4 is a kind of electrical block diagram for times source circuit that another embodiment of the application provides；
Fig. 5 is a kind of electrical block diagram for times source circuit that another embodiment of the application provides；
Fig. 6 is a kind of electrical block diagram for times source circuit that the further embodiment of the application provides.
Specific embodiment
As described in background, in existing times of source circuit, due to the transistor and preparation times potential source of transfer overvoltage
Between the wafer of circuit there are doping type difference, caused by bulk effect the problem of, reduce these transistor transfer overvoltages
Efficiency, thereby reduce the whole efficiency of times source circuit.
Concrete principle is explained as follows, and as shown in FIG. 1, FIG. 1 is the signals of the circuit structure of in the prior art times of source circuit
Figure, this times of source circuit is by the first transistor M1, second transistor M2, third transistor M3, the 4th transistor M4, first capacitor
C1 and the second capacitor C2 is constituted, wherein the first transistor M1, second transistor M2, third transistor M3 and the 4th transistor M4
Cross-coupling connection, specific connection relationship such as Fig. 1；In Fig. 1, the one end of first capacitor C1 far from the first transistor M1 is for defeated
Enter the one end of the first clock signal CK, the second capacitor C2 far from second transistor M2 for inputting second clock signal CKB, first
The timing of clock signal CK and second clock signal CKB are opposite.During the work time, when the first clock signal CK be high level,
When second clock signal CKB is low level, second transistor M2 and the 4th transistor M4 are opened, and the first transistor M1 and third are brilliant
Body pipe M3 shutdown, input voltage VDD are transmitted to one end of the second capacitor C2 by second transistor M2, and first capacitor C1 multiplication of voltage is formed
2VDD is exported by the 4th open transistor M4 to output end.When the first clock signal CK is low level, second clock signal
When CKB is high level, the first transistor M1 and third transistor M3 are opened, second transistor M2 and the 4th transistor M4 shutdown,
Input voltage VDD is transmitted to one end of first capacitor C1 by the first transistor M1, and the second capacitor C2 multiplication of voltage forms 2VDD by beating
The third transistor M3 opened is exported to output end VOUT.
But in circuit structure shown in Fig. 1, since the wafer that integrated circuit fabrication process uses is usually p-type crystalline substance
Circle, due to being N-type transistor, it is p-well that N-type transistor, which is needed using p-well as substrate, by the first transistor M1 and second transistor M2
It can be grounded (GND), and the source electrode of the first transistor M1 and second transistor M2 need to receive input voltage VDD, source voltage is big
It will make to lead to the first transistor there are serious bulk effect in the first transistor M1 and second transistor M2 in basic voltage
The threshold voltage and equivalent resistance of M1 and second transistor M2 rises, and not only improves the first transistor M1 and second transistor M2
Turn-on time, and reduce the first transistor M1 and second transistor M2 transmitting voltage amplitude so that first crystal
The efficiency of the transfer overvoltage of pipe M1 and second transistor M2 reduces, to reduce the whole efficiency of times source circuit.This is at certain
When under the conditions of a little special process angles and temperature, this problem is particularly acute.
And it should be noted that since the first clock signal CK and second clock signal CKB are generally not ideal
Reversed clock, when clock signal from high level to low transition or from low level to high level convert when, usually exist delay
(Fig. 2 be the non-overlapping clock of two-phase, herein be plain inverter introduce clock delay), this will lead to the first transistor M1 and
There is different degrees of current reflux in second transistor M2 and third transistor M3 and the 4th transistor M4, further
Reduce the efficiency of times source circuit.
Such as use the non-overlapping clock of two-phase shown in Fig. 2, it is assumed that the first clock signal CK is the letter of clock shown in waveform C11
Number, second clock signal CKB is clock signal shown in waveform C22, when the first clock signal CK is turned from high level to low level
When changing, second clock signal CKB postpones T1 due to existing, and is still within low level, at this time the first transistor M1 and the second crystal
Pipe M2 is turned off, but the source voltage of the 4th transistor M4 is 2VDD, grid voltage VDD, drain voltage VDD, therefore is protected
Opening state is held, due to not having input voltage, the output voltage of the 2VDD of output end is caused to pass through the 4th transistor M4 to multiplication of voltage
It is flowed into inside source circuit, causes the amplitude of the output voltage of times source circuit to reduce, further reduced the effect of times source circuit
Rate.
Likewise, postponing T2, second clock due to existing when the first clock signal CK is converted from low level to high level
Signal CKB time morning T2 is converted to low level by high level, it may appear that the output voltage of the 2VDD of output end by open the
Three transistor M3 enter to source circuit inside stream again, cause the amplitude of the output voltage of times source circuit to reduce, further decrease
The efficiency of times source circuit.
And assume that as the first clock signal CK be first high level by low transition, and after second clock signal CKB when T1
Between when being converted to low level by high level, and can have second transistor M2 and be stayed open within time delay time T1, thus
There is the case where leakage current.Therefore, in the prior art times of source circuit also will appear electricity in the non-overlapping clock of application two-phase
The case where flowing back to stream reduces the efficiency of times source circuit.
In view of this, the embodiment of the present application provides one kind times source circuit, charge pump circuit and electronic equipment, wherein
Described times of source circuit uses the transmission transistor of the first transistor and second transistor as input voltage, using third crystal
Pipe as first capacitor to the transmission transistor of the output voltage after input voltage multiplication of voltage, using the 4th transistor as the second electricity
Hold the transmission transistor to the output voltage after input voltage multiplication of voltage, and the first transistor, second transistor, third transistor
Be P-type transistor with the 4th transistor, and P-type transistor is using N trap as substrate, and N trap can connect it is any above Ground
Current potential, therefore can directly can be connect with the source electrode of P-type transistor with the substrate of P-type transistor, it avoids due to source voltage
Higher than bulk effect caused by underlayer voltage, the efficiency of transistor transfer overvoltage is improved, to improve times source circuit
Whole efficiency.
And described times of source circuit be in clock non-overlapping using two-phase as shown in Figure 2, due to third transistor and
In advance shutdown of 4th transistor in delay time, avoid output end voltage reflux the case where appearance, further promoted
The whole efficiency of times source circuit.
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
The embodiment of the present application provides a kind of times source circuit, as shown in Figure 3, comprising: the first transistor Q1, the second crystal
Pipe Q2, third transistor Q3, the 4th transistor Q4, first capacitor C1, the second capacitor C2, first choice biasing module 10, second
Select biasing module 20, the first clock module 30 and second clock module 40；Wherein,
First clock module 30 includes the first output terminal of clock and second clock output end, first clock output
End is for exporting the first clock signal, and the second clock output end is for exporting second clock signal；
The second clock module 40 includes third output terminal of clock and the 4th output terminal of clock, the third clock output
End is for exporting third clock signal, and the 4th output terminal of clock is for exporting the 4th clock signal, the first clock letter
Number and second clock signal timing on the contrary, the timing of the third clock signal and the 4th clock signal on the contrary, described first
The timing of clock signal and third clock signal is opposite；
The first choice biasing module 10 include first input end, the first output end and second output terminal, described first
Input terminal is connect with first output terminal of clock, and first output end is connect with the grid of the first transistor Q1, institute
It states second output terminal to connect with one end of the source electrode of the first transistor Q1 and the first capacitor C1, the first capacitor
The one end of C1 far from the second output terminal is connect with the second clock output end；
The drain electrode of the first transistor Q1 connects the first power input；
The first choice biasing module 10 is used in first clock signal be high level, the second clock signal
When for low level, the first transistor Q1 is connected；It is low level in first clock signal, the second clock signal is
When high level, the first transistor Q1 is turned off；
It is described second selection biasing module 20 include the second input terminal, third output end and the 4th output end, described second
Input terminal is connect with the third output terminal of clock, and the third output end is connect with the grid of the second transistor Q2, institute
It states the 4th output end to connect with one end of the source electrode of the second transistor Q2 and the second capacitor C2, second capacitor
C2 is connect far from one end of the 4th output end with the 4th output terminal of clock；
The drain electrode of the second transistor Q2 connects second source input terminal；
Described second selects biasing module 20 for being high level in the third clock signal, the 4th clock signal
When for low level, the second transistor Q2 is connected；It is low level in the third clock signal, the 4th clock signal is
When high level, the second transistor Q2 is turned off；
The grid of the third transistor Q3 is connect with the second output terminal, and source electrode is connect with the 4th output end,
Drain electrode is connect with the drain electrode of the 4th transistor Q4, as signal output end VOUT；
The grid of the 4th transistor Q4 is connect with the 4th output end, and source electrode is connect with the second output terminal；
The first transistor Q1, second transistor Q2, third transistor Q3 and the 4th transistor Q4 are P-type crystal
Pipe.
In the practical work process of provided in this embodiment times of source circuit, when the first clock signal and the 4th clock are believed
It number is high level, when second clock signal and third clock signal are low level, first choice biasing module 10 is connected described the
One transistor Q1, because the first transistor Q1 is P-type transistor, input voltage VDD is to efficiently transmit node N.This
Shi Jiedian NB is 2VDD current potential, and second clock signal and third clock signal are low level, and the 2VDD current potential at NB node is inclined
The grid of second transistor Q2 is set, second transistor Q2 is turned off, and during this, third transistor Q3 transmits 2VDD voltage extremely
The signal output end, the 4th transistor Q4 shutdown.
When the first clock signal and the 4th clock signal are low level, second clock signal and third clock signal are high electricity
Usually, first choice biasing module 10 turns off the first transistor Q1, and it is brilliant that the second selection biasing module 20 is connected described second
Body pipe Q2, low level are biased to the grid of second transistor Q2.Because second transistor Q2 is P-type transistor, input
Voltage VDD is to efficiently transmit node NB.Node N is 2VDD current potential at this time, and the first clock signal and the 4th clock signal are
The 2VDD current potential of N node is biased to the grid of the first transistor Q1, the first transistor by ground potential, the second selection biasing module 20
Q1 is turned off.At this stage, the 4th transistor Q4 transmits 2VDD voltage to the signal output end, and third transistor Q3 is closed
It is disconnected.
Still referring to Figure 2, when first clock signal is clock signal shown in C11, the third clock signal is
Shown in C22 when clock signal, second clock signal is the inverting clock signal of the first clock signal, the 4th clock signal
For the inverting clock signal of third clock signal.In the first clock signal from high level to low transition, third clock signal
When being converted from low level to high level, it is assumed that there are delay T1, within the T1 period, the first clock signal and third clock signal
It is low level, second clock signal and the 4th clock signal is high level, third transistor Q3 is turned off first, and at this time
Four transistor Q4 are also at off state, and after only delay T1, third clock signal is converted to high level, the 4th clock signal
When being converted to low level, the 4th transistor Q4 can just open the output for carrying out normal 2VDD, avoid signal output end
2VDD voltage occurs by third transistor Q3 to the case where potential source internal reflux again during switch conversion.
Likewise, the first clock signal is electric from low level to height in third clock signal from high level to low transition
When flat turn is changed, the third clock signal morning T2 time is converted to low level, likewise, in the present embodiment, the 4th transistor Q4 is first
It is first turned off, third transistor Q3 is also at off state at this time, and after only delay T2, the first clock signal is converted to high electricity
Usually, third transistor Q3 can just open the output for carrying out normal 2VDD, and the 2VDD voltage for avoiding signal output end is being opened
It closes in conversion process and occurs by the 4th transistor Q4 to the case where potential source internal reflux again.
On the basis of the above embodiments, one embodiment of the application provide a kind of feasible first biasing module and
The composition of second biasing module, as shown in figure 4, the first choice biasing module 10 includes: the 5th transistor Q5 and the 6th brilliant
Body pipe Q6；
The grid of the 5th transistor Q5 and the grid of the 6th transistor Q6 are connected to the first input end,
For receiving the first fixed current potential, the substrate of the 5th transistor Q5 is described for receiving for the drain electrode of the 5th transistor Q5
First fixed current potential, the source electrode of the 5th transistor Q5 is connect with the drain electrode of the 6th transistor Q6, as described first
Output end；
The substrate of the 6th transistor Q6 is connect with the source electrode of the 6th transistor Q6, as second output
End.
The second selection biasing module 20 includes: the 7th transistor Q7 and the 8th transistor Q8；
The grid of the 7th transistor Q7 and the grid of the 8th transistor Q8 are connected to the first input end,
For receiving the second fixed current potential, the substrate of the 7th transistor Q7 is described for receiving for the drain electrode of the 7th transistor Q7
Second fixed current potential, the source electrode of the 7th transistor Q7 is connect with the drain electrode of the 8th transistor Q8, as described first
Output end；
The substrate of the 8th transistor Q8 is connect with the source electrode of the 8th transistor Q8, as second output
End.
Optionally, the described first fixed current potential is low level or zero potential.
Optionally, the described second fixed current potential is low level or zero potential.Label VSS indicates zero potential or ground in Fig. 4
Current potential.
Optionally, the 5th transistor Q5 and the 7th transistor Q7 is N-type transistor, and the substrate of N-type transistor is grounded；
6th transistor Q6 and the 8th transistor Q8 is P-type transistor, and the substrate of P-type transistor is connect with source electrode.
On the basis of the above embodiments, the application another embodiment provides for a kind of first clock module 30 and the
The feasible composition of two clock modules 40, as shown in figure 5, first clock module 30 is the first phase inverter 31；
The input terminal of first phase inverter 31 is for receiving first clock signal, as first clock output
End；The output end of first phase inverter 31 is as the second clock output end；
First phase inverter 31 is used to export the second clock signal to after first clock signal processing.
The second clock module 40 is the second phase inverter 41；
The input terminal of second phase inverter 41 is for receiving the third clock signal, as the third clock output
End；The output end of second phase inverter 41 is as the 4th output terminal of clock；
Second phase inverter 41 is used to export the 4th clock signal to after third clock signal processing.
Referring still to Fig. 5, the first operating voltage input terminal of first phase inverter 31 (such as can for receiving high level
To be operating voltage VDD), the second operating voltage input terminal of first phase inverter 31 (such as can be with for receiving low level
It is zero potential or ground potential VSS)；First operating voltage input terminal of second phase inverter 41 is described for receiving high level
Second operating voltage input terminal of the second phase inverter 41 is for receiving low level.
On the basis of the above embodiments, in another embodiment of the application, as shown in fig. 6, described times of potential source electricity
Road further include:
Third capacitor C3；
One end of the third capacitor C3 is connect with the drain electrode of the third transistor Q3, and the third capacitor C3's is another
End ground connection.
The voltage signal that the third capacitor C3 is used to export the signal output end carries out decoupling processing.
Correspondingly, the embodiment of the present application also provides a kind of charge pump circuit, including multiple times potential source electricity being sequentially connected in series
Road, described times of source circuit are times source circuit described in any of the above-described embodiment.
Correspondingly, the embodiment of the present application also provides a kind of electronic equipment, including times as described in above-mentioned any embodiment
Source circuit.
In conclusion the embodiment of the present application provides one kind times source circuit, charge pump circuit and electronic equipment, wherein
Described times of source circuit uses the transmission transistor of the first transistor and second transistor as input voltage, using third crystal
Pipe as first capacitor to the transmission transistor of the output voltage after input voltage multiplication of voltage, using the 4th transistor as the second electricity
Hold the transmission transistor to the output voltage after input voltage multiplication of voltage, and the first transistor, second transistor, third transistor
Be P-type transistor with the 4th transistor, and P-type transistor is using N trap as substrate, and N trap can connect it is any above Ground
Current potential, therefore can directly can be connect with the source electrode of P-type transistor with the substrate of P-type transistor, avoid existing CMOS type times
The source voltage of N-type transistor of the potential source due to playing voltage transfer function is higher than bulk effect caused by underlayer voltage, is promoted
The efficiency of transistor transfer overvoltage, to improve the whole efficiency of times source circuit.
It is orderly based on the non-overlapping clock of two-phase and by giving the suitable dynamic bias circuit of P-type transistor gate design
Control the first transistor, second transistor, third transistor and the 4th transistor on and off, described times of source circuit can be effective
The current reflux problem for avoiding classical CMOS type times source circuit switching moments from occurring.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
The foregoing description of the disclosed embodiments makes professional and technical personnel in the field can be realized or use the application.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of times source circuit characterized by comprising the first transistor, second transistor, third transistor, the 4th crystalline substance
When body pipe, first capacitor, the second capacitor, first choice biasing module, the second selection biasing module, the first clock module and second
Clock module；Wherein,
First clock module includes the first output terminal of clock and second clock output end, and first output terminal of clock is used for
The first clock signal is exported, the second clock output end is for exporting second clock signal；
The second clock module includes third output terminal of clock and the 4th output terminal of clock, and the third output terminal of clock is used for
Third clock signal is exported, the 4th output terminal of clock is for exporting the 4th clock signal, first clock signal and the
The timing of two clock signals on the contrary, the timing of the third clock signal and the 4th clock signal on the contrary, first clock is believed
It is number opposite with the timing of third clock signal；
The first choice biasing module includes first input end, the first output end and second output terminal, the first input end
It is connect with first output terminal of clock, first output end is connect with the grid of the first transistor, and described second is defeated
Outlet is connect with one end of the source electrode of the first transistor and the first capacitor, and the first capacitor is far from described second
One end of output end is connect with the second clock output end；
The drain electrode of the first transistor connects the first power input；
The first choice biasing module is used in first clock signal be high level, and the second clock signal is low electricity
Usually, the first transistor is connected；It is low level in first clock signal, the second clock signal is high level
When, turn off the first transistor；
The second selection biasing module includes the second input terminal, third output end and the 4th output end, second input terminal
It is connect with the third output terminal of clock, the third output end is connect with the grid of the second transistor, and the described 4th is defeated
Outlet is connect with one end of the source electrode of the second transistor and second capacitor, and second capacitor is far from the described 4th
One end of output end is connect with the 4th output terminal of clock；
The drain electrode of the second transistor connects second source input terminal；
Described second selects biasing module for being high level in the third clock signal, and the 4th clock signal is low electricity
Usually, the second transistor is connected；It is low level in the third clock signal, the 4th clock signal is high level
When, turn off the second transistor；
The grid of the third transistor is connect with the second output terminal, and source electrode is connect with the 4th output end, drain electrode with
The drain electrode of 4th transistor connects, as signal output end；
The grid of 4th transistor is connect with the 4th output end, and source electrode is connect with the second output terminal；
The first transistor, second transistor, third transistor and the 4th transistor are P-type transistor.
2. according to claim 1 times of source circuit, which is characterized in that the first choice biasing module includes: the 5th
Transistor and the 6th transistor；
The grid of 5th transistor and the grid of the 6th transistor are connected to the first input end, and the described 5th
The drain electrode of transistor is for receiving the first fixed current potential, and the substrate of the 5th transistor is for receiving the described first fixed electricity
Position, the source electrode of the 5th transistor is connect with the drain electrode of the 6th transistor, as first output end；
The substrate of 6th transistor is connect with the source electrode of the 6th transistor, as the second output terminal.
3. according to claim 2 times of source circuit, which is characterized in that the described first fixed current potential is low level or zero electricity
Position.
4. according to claim 1 times of source circuit, which is characterized in that the second selection biasing module includes: the 7th
Transistor and the 8th transistor；
The grid of 7th transistor and the grid of the 8th transistor are connected to the first input end, and the described 7th
The drain electrode of transistor is for receiving the second fixed current potential, and the substrate of the 7th transistor is for receiving the described second fixed electricity
Position, the source electrode of the 7th transistor is connect with the drain electrode of the 8th transistor, as first output end；
The substrate of 8th transistor is connect with the source electrode of the 8th transistor, as the second output terminal.
5. according to claim 4 times of source circuit, which is characterized in that the described second fixed current potential is low level or zero electricity
Position.
6. according to claim 1 times of source circuit, which is characterized in that first clock module is the first phase inverter；
The input terminal of first phase inverter is for receiving first clock signal, as first output terminal of clock；Institute
The output end of the first phase inverter is stated as the second clock output end；
First phase inverter is used to export the second clock signal to after first clock signal processing.
7. according to claim 1 times of source circuit, which is characterized in that the second clock module is the second phase inverter；
The input terminal of second phase inverter is for receiving the third clock signal, as the third output terminal of clock；Institute
The output end of the second phase inverter is stated as the 4th output terminal of clock；
Second phase inverter is used to export the 4th clock signal to after third clock signal processing.
8. according to claim 1 times of source circuit, which is characterized in that further include: third capacitor；
One end of the third capacitor is connect with the drain electrode of the third transistor, the other end ground connection of the third capacitor.
9. a kind of charge pump circuit, which is characterized in that including multiple times source circuits being sequentially connected in series, described times of source circuit is
Described in any item times of source circuits of claim 1-8.
10. a kind of electronic equipment, which is characterized in that including such as described in any item times of source circuits of claim 1-8.
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| CN201811426789.1A CN109302057B (en) | 2018-11-27 | 2018-11-27 | Voltage-multiplying source circuit, charge pump circuit and electronic equipment |
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| CN201811426789.1A CN109302057B (en) | 2018-11-27 | 2018-11-27 | Voltage-multiplying source circuit, charge pump circuit and electronic equipment |
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| CN109302057B CN109302057B (en) | 2020-02-11 |
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| CN114204804A (en) * | 2020-09-17 | 2022-03-18 | 圣邦微电子（北京）股份有限公司 | Charge pump circuit |
| CN117526705A (en) * | 2023-12-29 | 2024-02-06 | 中茵微电子(南京)有限公司 | Voltage doubling circuit based on Dickson voltage doubler |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN109302057B (en) | 2020-02-11 |
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