CN108319324B - Power supply noise insensitive current mirror circuit, chip and communication terminal - Google Patents
Power supply noise insensitive current mirror circuit, chip and communication terminal Download PDFInfo
- Publication number
- CN108319324B CN108319324B CN201810243040.7A CN201810243040A CN108319324B CN 108319324 B CN108319324 B CN 108319324B CN 201810243040 A CN201810243040 A CN 201810243040A CN 108319324 B CN108319324 B CN 108319324B
- Authority
- CN
- China
- Prior art keywords
- current
- output
- current unit
- nmos transistor
- input current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a current mirror circuit, a chip and a communication terminal with insensitive power supply noise. The current mirror circuit comprises an input current unit, one or more output current units are connected in parallel with the input current unit; according to the preset ratio of the input current unit to the mirror current which is output by the output current unit and corresponds to the input current, the output current unit is controlled by the input current unit to output the mirror current which corresponds to the input current, and the noise component introduced by a power supply in the mirror current is eliminated, so that the current mirror circuit is not influenced by high-frequency noise of the power supply, and the characteristic that the current mirror circuit is insensitive to the noise of the power supply is realized.
Description
Technical Field
The invention relates to a current mirror circuit, in particular to a current mirror circuit insensitive to power supply noise, and also relates to an integrated circuit chip comprising the current mirror circuit insensitive to power supply noise and a corresponding communication terminal, belonging to the technical field of analog integrated circuits.
Background
The traditional current mirror circuit realizes the mirror image of a certain current through a transistor, and the mirrored current is the exact copy of the input current, namely, the direction of each output current is the same as the direction of the input current and the magnitude of each output current is in proportion to the magnitude of the input current. Therefore, the current mirror circuit is the most basic unit in an analog integrated circuit, and the current mirror circuit may constitute a basic block circuit of a current mode, such as a current mode transmitter, a differentiator, an integrator, and the like, or may constitute a current mode integrated circuit, such as a continuous time filter, an a/D converter, and the like.
However, a problem commonly encountered in conventional current mirror circuits is that the current generated by the mirror contains noise current components that are not present in the input current. For example, high frequency noise components in the power supply, which are widely present in integrated circuits, particularly mixed signal integrated circuits, can cause the noise current component.
As shown in FIG. 1, in a conventional current mirror circuit, a three-way mirror current is located to the right of the dotted lineOutput current I without considering noise factorout1～Iout3And an input current IinSame direction and size as IinThe magnitude of the current of (c) is a certain fixed ratio. However, when considering the supply voltage VDDWhen the high-frequency noise component is in the middle, the current I is outputout1～Iout3The same noise current is introduced.
Disclosure of Invention
The present invention provides a current mirror circuit with insensitive power supply noise.
Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the current mirror circuit insensitive to power supply noise and a corresponding communication terminal.
According to a first aspect of the embodiments of the present invention, there is provided a current mirror circuit insensitive to power supply noise, including an input current unit, the input current unit being connected in parallel with an output current unit;
according to the preset ratio of the input current unit and the mirror current which is output by the output current unit and corresponds to the input current, the output current unit is controlled to output the mirror current which corresponds to the input current through the input current unit, and the noise current component which is introduced by power supply noise in the mirror current is eliminated;
the mirror current output by each output current unit partially or completely flows into an output circuit in parallel, so that the total mirror current flowing into the output circuit is n times of the input current, and n is a positive integer.
According to a second aspect of the embodiments of the present invention, there is provided a current mirror circuit insensitive to power supply noise, including an input current unit connected in parallel with a plurality of output current units;
according to the preset ratio of the input current unit and the mirror current which is output by the output current unit and corresponds to the input current, the output current unit is controlled to output the mirror current which corresponds to the input current through the input current unit, and the noise current component which is introduced by power supply noise in the mirror current is eliminated;
the mirror current output by each output current unit partially or completely flows into an output circuit in parallel, so that the total mirror current flowing into the output circuit is n times of the input current, and n is a positive integer.
Preferably, the input current unit comprises a first PMOS transistor, a second PMOS transistor and a first NMOS transistor; the source electrodes of the first PMOS transistor and the second PMOS transistor are respectively connected with a power supply voltage, the grid electrode and the drain electrode of the first PMOS transistor are connected and connected to a bias current source, and the grid electrodes of the first PMOS transistor and the second PMOS transistor are connected together to form a P-type grid electrode voltage end of the input current unit; the drain electrode of the second PMOS transistor is connected with the drain electrode of the first NMOS transistor, the drain electrode of the first NMOS transistor is connected with the grid electrode of the first NMOS transistor to form an N-type grid electrode voltage end of the input current unit, the N-type grid electrode voltage end is connected with the input circuit, and the source electrode of the first NMOS transistor is grounded.
Preferably, the output current unit comprises a third PMOS transistor and a second NMOS transistor; the source electrode of the third PMOS transistor is connected with power supply voltage, the drain electrode of the third PMOS transistor is respectively connected with the drain electrode of the second NMOS transistor and the output circuit, and the grid electrode of the third PMOS transistor is a P-type grid electrode voltage end of the output current unit; the source electrode of the second NMOS transistor is grounded, and the grid electrode of the second NMOS transistor is the N-type grid electrode voltage end of the output current unit; the P-type grid voltage end of the output current unit is connected with the P-type grid voltage end of the input current unit, and the N-type grid voltage end of the output current unit is connected with the N-type grid voltage end of the input current unit.
Preferably, the input current unit comprises a third NMOS transistor, a fourth NMOS transistor and a fourth PMOS transistor; the drains of the third NMOS transistor and the fourth NMOS transistor are respectively connected with a power supply voltage, the gate and the drain of the third NMOS transistor are connected, the source of the third NMOS transistor is connected to a bias current source, and the gates of the third NMOS transistor and the fourth NMOS transistor are connected together to form an N-type gate voltage end of the input current unit; the source electrode of the fourth NMOS transistor is connected with the source electrode of the fourth PMOS transistor, the grid electrode of the fourth PMOS transistor is connected with the source electrode to form a P-type grid electrode voltage end of the input current unit, the P-type grid electrode voltage end is connected with the input circuit, and the drain electrode of the fourth PMOS transistor is grounded.
Preferably, the output current unit comprises a fifth NMOS transistor and a fifth PMOS transistor; the drain of the fifth NMOS transistor is connected with a power supply voltage, the source of the fifth NMOS transistor is respectively connected with the source of the fifth PMOS transistor and the output circuit, and the gate of the fifth NMOS transistor is an N-type gate voltage end of the output current unit; the drain electrode of the fifth PMOS transistor is grounded, and the grid electrode of the fifth PMOS transistor is a P-type grid electrode voltage end of the output current unit; the N-type grid voltage end of the output current unit is connected with the N-type grid voltage end of the input current unit, and the P-type grid voltage end of the output current unit is connected with the P-type grid voltage end of the input current unit.
Preferably, the size ratio of the NMOS transistor in the input current unit is the same as the size ratio of the NMOS transistor in the output current unit, and the size ratio of the PMOS transistor in the input current unit is the same as the size ratio of the PMOS transistor in the output current unit.
According to a third aspect of the embodiments of the present invention, there is provided an integrated circuit chip including the above-described power supply noise insensitive current mirror circuit.
According to a fourth aspect of the embodiments of the present invention, there is provided a communication terminal including the above-described current mirror circuit insensitive to power supply noise.
The power supply noise-insensitive current mirror circuit provided by the invention has the advantages that the input current unit is connected with one or more output current units in parallel, and the input current unit is used for eliminating the noise current component introduced by the power supply noise in the mirror current which is output by the current output unit and corresponds to the input current, so that the power supply noise-insensitive current mirror circuit is not influenced by the high-frequency noise of the power supply, and the characteristic of insensitivity to the power supply noise is realized.
Drawings
FIG. 1 is a schematic diagram of a conventional current mirror circuit;
FIG. 2 is a schematic diagram of a power supply noise insensitive current mirror circuit according to the present invention;
fig. 3 is a specific design example of the supply noise insensitive current mirror circuit shown in fig. 2.
Fig. 4 is a schematic diagram of another structure of a current mirror circuit with no power supply noise sensitivity according to the present invention.
Detailed Description
The technical contents of the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 2 to 4, the current mirror circuit insensitive to power supply noise provided by the present invention includes an input current unit 1, where the input current unit 1 is connected in parallel with one or more output current units 2. According to the preset ratio of the input current unit 1 and the mirror current output by the output current unit 2 corresponding to the input current, the output current unit 2 is controlled to output the mirror current corresponding to the input current through the input current unit 1, and the noise current component introduced by power supply noise in the mirror current output by the output current unit 2 is eliminated, so that the current mirror circuit insensitive to the power supply noise is not influenced by the high-frequency noise of the power supply, and the characteristic of insensitivity to the power supply noise is realized.
In one embodiment of the present invention, as shown in fig. 2, the input current unit 1 includes a first PMOS transistor M1, a second PMOS transistor M2, and a first NMOS transistor M4; wherein, the sources of the first PMOS transistor M1 and the second PMOS transistor M2 are respectively connected with the power voltage VDD(ii) a The gate and drain of the first PMOS transistor M1 are connected to a bias current source ISThe above step (1); gates of the first and second PMOS transistors M1 and M2The electrodes are connected together to form a P-type grid voltage end of the input current unit 1; the drain of the second PMOS transistor M2 is connected to the drain of the first NMOS transistor M4, the drain and the gate of the first NMOS transistor M4 are connected together to form an N-type gate voltage terminal of the input current unit 1, the N-type gate voltage terminal is connected to the input circuit 3, and the source of the first NMOS transistor M4 is grounded.
When the current of a reference branch flows from the P-type gate voltage end of the input current unit 1, an input current I is formedinThe input current IinThe N-type grid voltage ends respectively flowing into the input circuit 3 and the input current unit 1; due to the supply voltage VDDProviding a DC bias to the first PMOS transistor M1, thereby forming a bias current ISBias current ISIs determined by the device parameters of the first PMOS transistor M1, and the bias current I is constant under the condition that the device parameters of the first PMOS transistor M1 are not changedSIs a definite value. The bias current ISWhen a high frequency noise is present in the power supply voltage VDD, a noise current I is generated from the P-type gate voltage terminal of the input current unit 1 flowing into the second PMOS transistor M2nFlows into the second PMOS transistor M2, thereby forming a reference current Ir, which can be expressed as:
Ir＝IS+In(1)
the reference current Ir flows into the N-type gate voltage terminal of the input current cell 1, and therefore, the current I flowing to the ground in the first NMOS transistor M4dCan be expressed as:
Id＝Ir-Iin(2)
substituting equation (1) into equation (2) yields:
Id＝IS+In-Iin(3)
as shown in fig. 2, the output current unit 2 includes a third PMOS transistor M3 and a second NMOS transistor M5; wherein the source of the third PMOS transistor M3 is connected to the power supply voltage VDDThe drain of the third PMOS transistor M3 is connected to the drain of the second NMOS transistor M5 and the output circuit 4, respectively, and the gate of the third PMOS transistor M3 is the P-type gate of the output current unit 2Pressing the end; the source of the second NMOS transistor M5 is grounded, and the gate of the second NMOS transistor M5 is the N-type gate voltage terminal of the output current unit 2; the P-type gate voltage end of the output current unit 2 is connected with the P-type gate voltage end of the input current unit 1, that is, the gate of the third PMOS transistor M3 is connected with the gate of the second PMOS transistor M2; the N-type gate voltage terminal of the output current unit 2 is connected to the N-type gate voltage terminal of the input current unit 1, that is, the gate of the second NMOS transistor M5 is connected to the gate of the first NMOS transistor M4. Also, the size ratio of the PMOS transistors in the input current cell 1 and the output current cell 2 is the same as the size ratio of the NMOS transistors, i.e., the size of each PMOS transistor in the input current cell 1 is the same as the size of each PMOS transistor in the output current cell 2, and the size of the NMOS transistor in the input current cell 1 is the same as the size of the NMOS transistor in the output current cell 2.
When the current of a reference branch flows from the P-type gate voltage end of the input current unit 1, an input current I is formedinWhen the input current I isinMirror current I ofoutFlows into the drain of the second NMOS transistor M5 and the output circuit 4 through the drain of the third PMOS transistor M3, respectively. Since the reference current Ir flowing through the second PMOS transistor M2 flows into the third PMOS transistor M3 of each output current cell 2, the reference current Ir flows into the N-type gate voltage terminal of the output current cell 2 through the drain of the third PMOS transistor M3, and the size of the NMOS transistor in the input current cell 1 is the same as that of the NMOS transistor in the output current cell 2, the current flowing to the ground in the second NMOS transistor M5 is equal to the current flowing to the ground in the first NMOS transistor M4. Then, with the input current IinCorresponding mirror current IoutCan be expressed as:
Iout＝Ir-Id(4)
substituting equations (1) and (3) into equation (5) yields:
Iout＝Iin(5)
from this, it can be derived that the mirror current IoutFor the input current IinIs accurately reproduced. Therefore, it is a hollow ballThe overcurrent input unit 1 controls the mirror current output by the output current unit 2 and corresponding to the input current, and eliminates the noise current component introduced by the power supply noise in the mirror current output by the output current unit 2, so that the current mirror circuit insensitive to the power supply noise is not influenced by the high-frequency noise of the power supply, and the characteristic of insensitivity to the power supply noise is realized. Also, the mirror current output by each output current unit 2 may partially or entirely flow in parallel into the output circuit 4, so that the total mirror current flowing into the output circuit 4 is the input current IinN is a positive integer. Therefore, when it is necessary to realize the total mirror current and the input current I flowing into the output circuit 4inWhen n (n is a positive integer) times the mirror relationship, the input current unit 1 may be connected in parallel with n (n is a positive integer) output current units 2.
In order to make the technical solution of the current mirror circuit with no sensitivity to power supply noise provided by this embodiment clearer, a specific embodiment is typically described in detail below with reference to fig. 3.
In this embodiment, as shown in fig. 3, an input current unit 1 is used to connect three output current units 2 in parallel, and the total mirror current flowing into an output circuit 4 is the input current IinTo form a 1: a 3 times power supply noise insensitive current mirror circuit. The width-to-length ratios of the PMOS transistors in the input current unit 1 and the output current unit 2 are both 10um/2um, and the width-to-length ratios of the NMOS transistors in the input current unit 1 and the output current unit 2 are also both 10um/2um, i.e., the width-to-length ratios of the PMOS transistors M1-M3, the PMOS transistors M8 and M9, and the NMOS transistors M4-M7 are both 10um/2 um. Assumed to be driven by the supply voltage VDDA bias current I formed by providing a DC bias to the PMOS transistor M1SSize of 20uA, power supply voltage VDDUpper noise current I generated by high frequency noisenThe RMS value is 0.1uA, therefore, the bias current I is setSAnd noise current InSubstituting the formula (1) results in that the magnitude of the reference current Ir flowing into the PMOS transistors M2, M3, M8, and M9 is 20.1uA, respectively. When the current of a certain reference branch flows in from the P-type gate voltage end of the input current unit 1, an output is formedInput current IinWhen, assume the input current IinIs 10uA, and the reference current Ir and the input current I are comparedinThe current I flowing to the ground in the NMOS transistors M4-M7 is obtained by substituting the formula (2)dAll were 10.1 uA. Will input current IinAnd a current I to grounddRespectively substituting into formula (4) to obtain output mirror current Iout1～Iout3The sizes are all 10 uA. If the mirror current I to be outputout1～Iout3Flows in parallel into the output circuit 4, so that the total mirror current flowing into the output circuit 4 is the input current Iin3 times of the total mirror current I flowing in the output circuit 4 and the input current I are formedin3 times mirror image relationship.
In another embodiment of the present invention, as shown in fig. 4, the input current unit 1 includes a third NMOS transistor M10, a fourth NMOS transistor M11, and a fourth PMOS transistor M13; the drains of the third NMOS transistor M10 and the fourth NMOS transistor M11 are connected to a power supply voltage VDD(ii) a The gate and drain of the third NMOS transistor M10 are connected, and the source of the third NMOS transistor M10 is connected to a bias current source ISThe above step (1); the gates of the third NMOS transistor M10 and the fourth NMOS transistor M11 are connected together to form an N-type gate voltage terminal of the input current unit 1; the source of the fourth NMOS transistor M11 is connected to the source of the fourth PMOS transistor M13, the gate and the source of the fourth PMOS transistor M13 are connected together to form a P-type gate voltage terminal of the input current unit 1, the P-type gate voltage terminal is connected to the input circuit 3, and the drain of the fourth PMOS transistor M13 is grounded.
As shown in fig. 4, the output current unit 2 includes a fifth NMOS transistor M12 and a fifth PMOS transistor M14; the drain of the fifth NMOS transistor M12 is connected to the supply voltage VDDThe source of the fifth NMOS transistor M12 is connected to the source of the fifth PMOS transistor M14 and the output circuit, respectively, and the gate of the fifth NMOS transistor M12 is the N-type gate voltage terminal of the output current unit 2; the drain of the fifth PMOS transistor M14 is grounded, and the gate of the fifth PMOS transistor M14 is the P-type gate voltage terminal of the output current unit 2. N-type gate voltage terminal of output current unit 2 and N-type gate of input current unit 1The voltage terminal is connected, namely the gate of the fifth NMOS transistor M12 is connected with the gate of the third NMOS transistor M10; the P-type gate voltage terminal of the output current unit 2 is connected to the P-type gate voltage terminal of the input current unit 1, that is, the gate of the fifth PMOS transistor M14 is connected to the gate of the fourth PMOS transistor M13. Also, the size ratio of the PMOS transistors in the input current cell 1 and the output current cell 2 is the same as the size ratio of the NMOS transistors, i.e., the size of each NMOS transistor in the input current cell 1 is the same as the size of each NMOS transistor in the output current cell 2, and the size of the PMOS transistor in the input current cell 1 is the same as the size of the PMOS transistor in the output current cell 2.
When the current of a certain reference branch flows in from the N-type gate voltage end of the input current unit 1, an input current I is formedinThe input current IinThe P-type gate voltage ends respectively flowing into the input circuit 3 and the input current unit 1; due to the supply voltage VDDProviding a DC bias to the third NMOS transistor M10, thereby forming a bias current ISBias current ISIs determined by the device parameters of the third NMOS transistor M10, and the bias current I is constant under the condition that the device parameters of the third NMOS transistor M10 are not changedSIs a definite value. The bias current ISFlows into the fourth NMOS transistor M11 from the N-type gate voltage terminal of the input current unit 1 when the power supply voltage VDDWhen high frequency noise exists in the circuit, a noise current I is generatednFlows into the fourth NMOS transistor M11, thereby forming a reference current Ir, the magnitude of which is derived from equation (1). The reference current Ir flows into the P-type gate voltage terminal of the input current unit 1, and the magnitude of the current flowing to the ground in the fourth PMOS transistor and the fifth PMOS transistor M14 is obtained by formula (2).
Then, the input current IinMirror current I ofoutThe source through the fifth NMOS transistor M12 flows into the source of the fifth PMOS transistor M14 and the output circuit 4, respectively. Since the reference current Ir flowing through the fourth NMOS transistor M11 flows into the fifth NMOS transistor M12 of each output current cell 2, the reference current Ir flows into the output terminal through the source of the fifth NMOS transistor M12The P-type gate voltage terminal of the current output unit 2 is obtained from the formula (4) and the input current IinCorresponding mirror current Iout。
Therefore, in the present embodiment, the current input unit 1 is also used to control the mirror current output by the output current unit 2 and corresponding to the input current, and eliminate the noise current component introduced by the power supply noise in the mirror current output by the output current unit 2, so that the current mirror circuit insensitive to the power supply noise is not affected by the power supply high frequency noise, thereby implementing the characteristic of being insensitive to the power supply noise. Furthermore, the mirror current output by each output current unit 2 may partially or completely flow in parallel into the output circuit 4, so that the total mirror current flowing into the output circuit 4 is the input current IinN is a positive integer. Therefore, when it is necessary to realize the total mirror current and the input current I flowing into the output circuit 4inWhen n (n is a positive integer) times the mirror relationship, the input current unit 1 may be connected in parallel with n (n is a positive integer) output current units 2.
In summary, the power supply noise insensitive current mirror circuit provided by the present invention connects the input current unit in parallel with one or more output current units, and eliminates the noise current component introduced by the power supply noise in the mirror current corresponding to the input current output by the current output unit through the input current unit, so that the power supply noise insensitive current mirror circuit is not affected by the power supply high frequency noise, thereby realizing the characteristic of being insensitive to the power supply noise.
The current mirror circuit which is not sensitive to power supply noise provided by the invention can be used in an analog integrated circuit chip. The specific structure of the current mirror circuit which is insensitive to power supply noise in the analog integrated circuit chip is not described in detail herein.
In addition, the above-described current mirror circuit insensitive to power supply noise can also be used in a communication terminal as an important component of an analog integrated circuit. The communication terminal mentioned here refers to a computer device that can be used in a mobile environment and supports multiple communication systems such as GSM, EDGE, TD _ SCDMA, TDD _ LTE, FDD _ LTE, etc., and includes a mobile phone, a notebook computer, a tablet computer, a vehicle-mounted computer, etc. In addition, the technical scheme provided by the invention is also suitable for other occasions of analog integrated circuit application, such as a communication base station and the like.
The power supply noise insensitive current mirror circuit, chip and communication terminal provided by the present invention have been described in detail above. It will be apparent to those skilled in the art that any obvious modifications thereto can be made without departing from the true spirit of the invention, which is to be accorded the full scope of the claims herein.
Claims (10)
1. A current mirror circuit insensitive to power supply noise is characterized by comprising an input current unit, an output current unit and a current mirror unit, wherein the input current unit is connected in parallel with the output current unit;
the input current unit comprises a first PMOS transistor, a second PMOS transistor and a first NMOS transistor; the source electrodes of the first PMOS transistor and the second PMOS transistor are respectively connected with a power supply, the grid electrode and the drain electrode of the first PMOS transistor are connected and connected to a bias current source, and the grid electrodes of the first PMOS transistor and the second PMOS transistor are connected together to form a P-type grid electrode voltage end of the input current unit; the drain electrode of the second PMOS transistor is connected with the drain electrode of the first NMOS transistor, the drain electrode and the grid electrode of the first NMOS transistor are connected together to form an N-type grid electrode voltage end of the input current unit, the N-type grid electrode voltage end is connected with the input circuit, and the source electrode of the first NMOS transistor is grounded;
according to the preset ratio of the input current unit and the mirror current which is output by the output current unit and corresponds to the input current, the output current unit is controlled to output the mirror current which corresponds to the input current through the input current unit, and the noise current component which is introduced by power supply noise in the mirror current is eliminated;
the mirror current output by each output current unit partially or completely flows into an output circuit in parallel, so that the total mirror current flowing into the output circuit is n times of the input current, and n is a positive integer.
2. A current mirror circuit insensitive to power supply noise is characterized by comprising an input current unit, a plurality of output current units and a plurality of output current units, wherein the input current unit is connected in parallel;
according to the preset ratio of the input current unit and the mirror current which is output by the output current unit and corresponds to the input current, the output current unit is controlled to output the mirror current which corresponds to the input current through the input current unit, and the noise current component which is introduced by power supply noise in the mirror current is eliminated;
the input current unit comprises a first PMOS transistor, a second PMOS transistor and a first NMOS transistor; the source electrodes of the first PMOS transistor and the second PMOS transistor are respectively connected with a power supply, the grid electrode and the drain electrode of the first PMOS transistor are connected and connected to a bias current source, and the grid electrodes of the first PMOS transistor and the second PMOS transistor are connected together to form a P-type grid electrode voltage end of the input current unit; the drain electrode of the second PMOS transistor is connected with the drain electrode of the first NMOS transistor, the drain electrode and the grid electrode of the first NMOS transistor are connected together to form an N-type grid electrode voltage end of the input current unit, the N-type grid electrode voltage end is connected with the input circuit, and the source electrode of the first NMOS transistor is grounded;
the mirror current output by each output current unit partially or completely flows into an output circuit in parallel, so that the total mirror current flowing into the output circuit is n times of the input current, and n is a positive integer.
3. The supply noise insensitive current mirror circuit according to claim 1 or 2, wherein:
the output current unit comprises a third PMOS transistor and a second NMOS transistor; the source electrode of the third PMOS transistor is connected with a power supply, the drain electrode of the third PMOS transistor is respectively connected with the drain electrode of the second NMOS transistor and the output circuit, and the grid electrode of the third PMOS transistor is a P-type grid electrode voltage end of the output current unit; the source electrode of the second NMOS transistor is grounded, and the grid electrode of the second NMOS transistor is the N-type grid electrode voltage end of the output current unit; the P-type grid voltage end of the output current unit is connected with the P-type grid voltage end of the input current unit, and the N-type grid voltage end of the output current unit is connected with the N-type grid voltage end of the input current unit.
4. The supply noise insensitive current mirror circuit of claim 3, wherein:
the size ratio of the NMOS transistor in the input current unit is the same as the size ratio of the NMOS transistor in the output current unit, and the size ratio of the PMOS transistor in the input current unit is the same as the size ratio of the PMOS transistor in the output current unit.
5. A current mirror circuit insensitive to power supply noise is characterized by comprising an input current unit, an output current unit and a current mirror unit, wherein the input current unit is connected in parallel with the output current unit;
the input current unit comprises a third NMOS transistor, a fourth NMOS transistor and a fourth PMOS transistor; the drain electrodes of the third NMOS transistor and the fourth NMOS transistor are respectively connected with a power supply, the grid electrode of the third NMOS transistor is connected with the drain electrode of the fourth NMOS transistor, the source electrode of the third NMOS transistor is connected to a bias current source, and the grid electrodes of the third NMOS transistor and the fourth NMOS transistor are connected together to form an N-type grid electrode voltage end of the input current unit; the source electrode of the fourth NMOS transistor is connected with the source electrode of the fourth PMOS transistor, the grid electrode and the source electrode of the fourth PMOS transistor are connected together to form a P-type grid electrode voltage end of the input current unit, the P-type grid electrode voltage end is connected with the input circuit, and the drain electrode of the fourth PMOS transistor is grounded;
according to the preset ratio of the input current unit and the mirror current which is output by the output current unit and corresponds to the input current, the output current unit is controlled to output the mirror current which corresponds to the input current through the input current unit, and the noise current component which is introduced by power supply noise in the mirror current is eliminated;
the mirror current output by each output current unit partially or completely flows into an output circuit in parallel, so that the total mirror current flowing into the output circuit is n times of the input current, and n is a positive integer.
6. A current mirror circuit insensitive to power supply noise is characterized by comprising an input current unit, a plurality of output current units and a plurality of output current units, wherein the input current unit is connected in parallel;
the input current unit comprises a third NMOS transistor, a fourth NMOS transistor and a fourth PMOS transistor; the drain electrodes of the third NMOS transistor and the fourth NMOS transistor are respectively connected with a power supply, the grid electrode of the third NMOS transistor is connected with the drain electrode of the fourth NMOS transistor, the source electrode of the third NMOS transistor is connected to a bias current source, and the grid electrodes of the third NMOS transistor and the fourth NMOS transistor are connected together to form an N-type grid electrode voltage end of the input current unit; the source electrode of the fourth NMOS transistor is connected with the source electrode of the fourth PMOS transistor, the grid electrode and the source electrode of the fourth PMOS transistor are connected together to form a P-type grid electrode voltage end of the input current unit, the P-type grid electrode voltage end is connected with the input circuit, and the drain electrode of the fourth PMOS transistor is grounded;
according to the preset ratio of the input current unit and the mirror current which is output by the output current unit and corresponds to the input current, the output current unit is controlled to output the mirror current which corresponds to the input current through the input current unit, and the noise current component which is introduced by power supply noise in the mirror current is eliminated;
the mirror current output by each output current unit partially or completely flows into an output circuit in parallel, so that the total mirror current flowing into the output circuit is n times of the input current, and n is a positive integer.
7. The supply noise insensitive current mirror circuit according to claim 5 or 6, wherein:
the output current unit comprises a fifth NMOS transistor and a fifth PMOS transistor; the drain of the fifth NMOS transistor is connected with a power supply, the source of the fifth NMOS transistor is respectively connected with the source of the fifth PMOS transistor and the output circuit, and the gate of the fifth NMOS transistor is the N-type gate voltage end of the output current unit; the drain electrode of the fifth PMOS transistor is grounded, and the grid electrode of the fifth PMOS transistor is a P-type grid electrode voltage end of the output current unit; the N-type grid voltage end of the output current unit is connected with the N-type grid voltage end of the input current unit, and the P-type grid voltage end of the output current unit is connected with the P-type grid voltage end of the input current unit.
8. The supply noise insensitive current mirror circuit of claim 7, wherein:
the size ratio of the NMOS transistor in the input current unit is the same as the size ratio of the NMOS transistor in the output current unit, and the size ratio of the PMOS transistor in the input current unit is the same as the size ratio of the PMOS transistor in the output current unit.
9. An integrated circuit chip comprising the power supply noise insensitive current mirror circuit of any of claims 1 to 8.
10. A communication terminal comprising the power supply noise insensitive current mirror circuit as claimed in any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810243040.7A CN108319324B (en) | 2018-03-23 | 2018-03-23 | Power supply noise insensitive current mirror circuit, chip and communication terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810243040.7A CN108319324B (en) | 2018-03-23 | 2018-03-23 | Power supply noise insensitive current mirror circuit, chip and communication terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108319324A CN108319324A (en) | 2018-07-24 |
| CN108319324B true CN108319324B (en) | 2020-06-30 |
Family
ID=62898902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810243040.7A Active CN108319324B (en) | 2018-03-23 | 2018-03-23 | Power supply noise insensitive current mirror circuit, chip and communication terminal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108319324B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109298745A (en) * | 2018-10-12 | 2019-02-01 | 广州智慧城市发展研究院 | The synchronous circuit and method for realizing linear voltage stabilization and dual voltage domains reference current source |
| CN113190077B (en) * | 2021-04-30 | 2023-06-30 | 华润微集成电路(无锡)有限公司 | Voltage stabilizing circuit |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6124705A (en) * | 1999-08-20 | 2000-09-26 | Lucent Technologies Inc. | Cascode current mirror with amplifier |
| JP2000330657A (en) * | 1999-05-17 | 2000-11-30 | Toshiba Corp | Semiconductor device |
| EP1394649A2 (en) * | 2002-08-28 | 2004-03-03 | NEC Electronics Corporation | Band gap circuit |
| CN1601894A (en) * | 2003-09-26 | 2005-03-30 | 罗姆股份有限公司 | Current mirror circuit |
| CN102809982A (en) * | 2012-07-13 | 2012-12-05 | 电子科技大学 | Low voltage current mirror |
| CN103283144A (en) * | 2010-12-16 | 2013-09-04 | 吉林克斯公司 | Current mirror and high-ompliance single-stage amplifier |
| CN104090625A (en) * | 2014-07-03 | 2014-10-08 | 电子科技大学 | Current mirror for low supply voltage |
| EP3023855A1 (en) * | 2014-11-20 | 2016-05-25 | Dialog Semiconductor (UK) Ltd | Fast bias current startup with feedback |
-
2018
- 2018-03-23 CN CN201810243040.7A patent/CN108319324B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000330657A (en) * | 1999-05-17 | 2000-11-30 | Toshiba Corp | Semiconductor device |
| US6124705A (en) * | 1999-08-20 | 2000-09-26 | Lucent Technologies Inc. | Cascode current mirror with amplifier |
| EP1394649A2 (en) * | 2002-08-28 | 2004-03-03 | NEC Electronics Corporation | Band gap circuit |
| CN1601894A (en) * | 2003-09-26 | 2005-03-30 | 罗姆股份有限公司 | Current mirror circuit |
| CN103283144A (en) * | 2010-12-16 | 2013-09-04 | 吉林克斯公司 | Current mirror and high-ompliance single-stage amplifier |
| CN102809982A (en) * | 2012-07-13 | 2012-12-05 | 电子科技大学 | Low voltage current mirror |
| CN104090625A (en) * | 2014-07-03 | 2014-10-08 | 电子科技大学 | Current mirror for low supply voltage |
| EP3023855A1 (en) * | 2014-11-20 | 2016-05-25 | Dialog Semiconductor (UK) Ltd | Fast bias current startup with feedback |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108319324A (en) | 2018-07-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8120408B1 (en) | Voltage controlled oscillator delay cell and method | |
| US8988154B2 (en) | Voltage-to-current converter and voltage controlled oscillator having voltage-to-current converter | |
| US10168727B2 (en) | Adaptive low-dropout regulator having wide voltage endurance range, chip and terminal | |
| US8030972B2 (en) | High-speed latched comparator circuit with variable positive feedback | |
| US8373496B2 (en) | Temperature compensated current source | |
| US20080238521A1 (en) | Low differential output voltage circuit | |
| US20180164843A1 (en) | Linear regulator with real-time frequency compensation function | |
| US20190319596A1 (en) | Low voltage inverter-based amplifier | |
| CN108319324B (en) | Power supply noise insensitive current mirror circuit, chip and communication terminal | |
| CN105765859A (en) | Amplifier arrangement | |
| WO2023005806A1 (en) | Ldo circuit having power supply rejection function, chip and communication terminal | |
| US20200401169A1 (en) | Low leakage low dropout regulator with high bandwidth and power supply rejection, and associated methods | |
| CN109546981B (en) | Differential input circuit, amplifying circuit, and display device | |
| US20180302073A1 (en) | Duty cycle calibration circuit and frequency synthesizer using the same | |
| WO2012083781A1 (en) | Voltage comparator | |
| US20210090483A1 (en) | Switch timing controlling circuit, switch timing controlling method and display device | |
| US20140354351A1 (en) | Chopping circuit for multiple output currents | |
| CN107422773B (en) | Digital low-dropout regulator | |
| US6058033A (en) | Voltage to current converter with minimal noise sensitivity | |
| CN107346959A (en) | A kind of operational amplifier that offset voltage correction is carried out for output services point | |
| CN109150164B (en) | Chip for generating constant reference current | |
| JPH03132115A (en) | Semiconductor integrated circuit | |
| CN108628379B (en) | Bias circuit | |
| JPH1041788A (en) | Ring oscillator | |
| JP6771852B2 (en) | Frequency converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |