CN109150164B - Chip for generating constant reference current - Google Patents
Chip for generating constant reference current Download PDFInfo
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- CN109150164B CN109150164B CN201810918240.8A CN201810918240A CN109150164B CN 109150164 B CN109150164 B CN 109150164B CN 201810918240 A CN201810918240 A CN 201810918240A CN 109150164 B CN109150164 B CN 109150164B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L5/00—Automatic control of voltage, current, or power
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K2017/515—Mechanical switches; Electronic switches controlling mechanical switches, e.g. relais
Abstract
The application provides a chip for generating constant reference current, which comprises a first circuit, a current mirror, an adjustable resistor array circuit, a second circuit, a clock circuit and a switch circuit. The first circuit is used for outputting a reference voltage. The current mirror is connected to the first circuit. The adjustable resistor array circuit is connected with the first circuit. The second circuit is connected with the first circuit. The second circuit is connected with the adjustable resistor array circuit. The clock circuit is connected with the second circuit. The switch circuit is connected with the current mirror. The switch circuit is connected with the second circuit. The switch circuit is connected with the first capacitor. The first circuit is also used for outputting a voltage regulating signal to the current mirror. The second circuit is used for outputting an adjusting signal for adjusting the resistance value of the adjustable resistor array circuit and outputting a control signal for controlling the switching circuit to be switched on and switched off. Reference current can be corrected through the cooperation of the first circuit, the current mirror, the adjustable resistor array circuit, the second circuit, the clock circuit and the switch circuit, so that the reference current is output constantly.
Description
Technical Field
The present application relates to the field of chip technology, and more particularly, to a chip for generating a constant reference current.
Background
On chip technology, commonly used circuits such as BI-CMOS, etc., have been developed for reliable reference voltage circuits. As technology develops, the power supply and temperature stability of the bandgap reference can meet most of the requirements of use. The gain of active devices in the chip, such as the voltage-current conversion ratio GM of an MOS tube, the current amplification coefficient beta of a triode, the light-emitting coefficient of an off-chip element such as an LED, the temperature-voltage coefficient of a temperature sensor and the like are calculated through current. Therefore, the reference voltage is required to be converted into the reference current, so that each part of the chip has a fixed reference value for performance calculation.
Usually, inside a chip, a reference current is generated by dividing a reference voltage by a resistor using an operational amplifier. And then the output is copied by circuits such as a current mirror and the like, and each module of the chip is biased. Different from an off-chip original piece, in a chip process, a process for realizing the resistor is generally polysilicon, and modes such as an N-well or P-well resistor, a metal resistor and the like are doped actively. Because the polysilicon resistor is a passive device, voltage bias is not needed, and latch-up failure is not considered. The square resistance is about several hundred ohms and the temperature characteristic is good. In a circuit for generating a reference current, a polysilicon resistor is generally used. However, in chip processes, the resistance varies from +/-15% to +/-30% with process variations, and the reference current varies accordingly. The bias current has close relationship with performance parameters such as chip power consumption, circuit driving capability, amplifier gain, loop stability and the like, and even influences the normal function of the circuit.
In general, in order to cover the bias current variation generated by the process, a corresponding design margin is added in the circuit design to ensure that the circuit can work normally under the condition of the maximum or minimum bias current. But this increases the performance cost of the circuit. The design difficulty of the circuit is also increased if more power consumption is needed. Due to off-chip components such as off-chip capacitors, the error of off-chip resistance is small (the deviation on the common model is 5%, and the special device can reach 1%). In the conventional design, if the current which does not change with the chip is required, an external resistor pin needs to be added on the chip, and the bias is generated through an off-chip resistor. This adds peripheral components and the chip pins also need to be adjusted, making the subsequent re-versioned products incompatible with the previous generation.
Disclosure of Invention
In view of the above, it is necessary to provide a chip generating a constant reference current in order to solve the problem that the chip cannot output the constant reference current due to the variation of the on-chip resistance caused by the process variation.
A chip for generating a constant reference current, comprising:
a first circuit for outputting a reference voltage;
the input end of the current mirror is connected with the first output end of the first circuit, and the first output end of the current mirror is connected with the input end of the first circuit;
the output end of the adjustable resistor array circuit is connected with the input end of the first circuit;
a second circuit, a first input terminal of the second circuit is connected with a second output terminal of the first circuit, and a first output terminal of the second circuit is connected with an input terminal of the adjustable resistor array circuit;
the output end of the clock circuit is connected with the second input end of the second circuit;
a first input end of the switch circuit is connected with a second output end of the current mirror, a second input end of the switch circuit is connected with a second output end of the second circuit, a first output end of the switch circuit is respectively connected with a third input end of the second circuit and the first capacitor, and a second output end of the switch circuit is grounded;
the first circuit is further used for outputting a voltage adjusting signal to the current mirror, and the second circuit is used for outputting an adjusting signal for adjusting the resistance value of the adjustable resistor array circuit and outputting a control signal for controlling the switching circuit to be switched on and switched off.
In one embodiment, the first circuit comprises:
the output end of the band-gap reference source is connected with the first input end of the second circuit, and the band-gap reference source is used for generating band-gap reference voltage;
the first input end of the operational amplifier is connected with the output end of the band-gap reference source, the second input end of the operational amplifier is connected with the output end of the adjustable resistor array circuit, the output end of the operational amplifier is connected with the input end of the current mirror, and the operational amplifier outputs the voltage adjusting signal to the current mirror based on the reference voltage and the feedback voltage output by the output end of the adjustable resistor array circuit.
In one embodiment, the second circuit comprises:
the input end of the timer is connected with the output end of the clock circuit;
the output end of the control circuit is respectively connected with the second input end of the switch circuit, and the first input end of the control circuit is connected with the output end of the timer;
and the first input end of the comparator is connected with the second output end of the first circuit, the second input end of the comparator is connected with the first output end of the switch circuit, and the output end of the comparator is connected with the second input end of the control circuit.
In one embodiment, the timer comprises:
the pulse input end of the first-stage D flip-flop is connected with the output end of the clock circuit;
the Q output end of each stage of D flip-flop is connected with the input end of the decoder;
and the output end of the decoder is connected with the first input end of the digital comparator, the second input end of the digital comparator is connected with the output end of the preset target value, and the output end of the digital comparator is connected with the first input end of the control circuit.
In one embodiment, the control circuit comprises:
the pulse input end of the first D trigger is connected with the output end of the timer, and the D input end of the first D trigger is connected with the output end of the comparator;
the first input end of the digital logic controller is connected with the output end of the timer, the Q output end of the first D trigger and the Q non-output end of the first D trigger are both connected with the second input end of the digital logic controller, the first output end of the digital logic controller is connected with the input end of the adjustable resistor array circuit, and the second output end of the digital logic controller is connected with the second input end of the switch circuit.
In one embodiment, the adjustable resistor array circuit comprises:
a plurality of first resistors connected in series, one ends of the plurality of first resistors connected in series are connected with the input end of the first circuit, and the other ends of the plurality of first resistors connected in series are grounded; wherein the content of the first and second substances,
each first resistor is connected with a first control switch in parallel, and the control signal input end of each first control switch is connected with the first output end of the second circuit.
In one embodiment, the adjustable resistor array circuit comprises:
one end of each parallel branch is connected with the input end of the first circuit, and the other end of each parallel branch is grounded; wherein the content of the first and second substances,
each parallel branch comprises a second resistor and a second control switch connected with the second resistor in series, and a control signal input end of each second control switch is connected with a first output end of the second circuit.
In one embodiment, the switching circuit includes:
a first input end of the control switch is connected with a second output end of the current mirror, a second input end of the control switch is connected with a second output end of the second circuit, and a second output end of the control switch is grounded;
and the input end of the gating module is connected with the first output end of the control switch, and the output end of the gating module is respectively connected with the third input end of the second circuit and the first capacitor.
In one embodiment, the chip further comprises:
and the input end of the second capacitor is connected with the first output end of the switch circuit, and the output end of the second capacitor is grounded.
In one embodiment, the current mirror comprises:
the grid electrode of the first MOS tube is connected with the first output end of the first circuit, and the drain electrode of the first MOS tube is connected with the input end of the first circuit;
and the grid electrode of the second MOS tube is connected with the first output end of the first circuit, the drain electrode of the second MOS tube is connected with the first input end of the switch circuit, and the source electrode of the second MOS tube is connected with the source electrode of the first MOS tube.
Compared with the prior art, the chip for generating the constant reference current comprises the first circuit, the current mirror, the adjustable resistor array circuit, the second circuit, the clock circuit and the switch circuit. The first circuit is used for outputting a reference voltage. The input end of the current mirror is connected with the first output end of the first circuit. And the first output end of the current mirror is connected with the input end of the first circuit. And the output end of the adjustable resistor array circuit is connected with the input end of the first circuit. The first input end of the second circuit is connected with the second output end of the first circuit. And the first output end of the second circuit is connected with the input end of the adjustable resistor array circuit. The output end of the clock circuit is connected with the second input end of the second circuit.
And the first input end of the switching circuit is connected with the second output end of the current mirror. The second input end of the switch circuit is connected with the second output end of the second circuit. And the first output end of the switch circuit is respectively connected with the third input end of the second circuit and the first capacitor. The second output terminal of the switching circuit is grounded. The first circuit is also used for outputting a voltage regulating signal to the current mirror. The second circuit is used for outputting an adjusting signal for adjusting the resistance value of the adjustable resistor array circuit and outputting a control signal for controlling the switching circuit to be switched on and switched off.
Reference current can be corrected through the cooperation of the first circuit, the current mirror, the adjustable resistor array circuit, the second circuit, the clock circuit and the switch circuit, so that the reference current is output constantly. Meanwhile, the correction process can be performed in parallel with other functions of the chip, the use of other functions of the chip is not influenced during correction, and the practicability is high. The application also has the characteristics of simple circuit structure and easy realization.
Drawings
FIG. 1 is a schematic block circuit diagram of a chip for generating a constant reference current according to an embodiment of the present disclosure;
fig. 2 is a block diagram of a circuit structure of a chip for generating a constant reference current according to an embodiment of the present disclosure;
FIG. 3 is a schematic block diagram of a timer and a digital control circuit according to an embodiment of the present disclosure;
FIG. 4 is a circuit diagram of an adjustable resistor array circuit according to an embodiment of the present application;
FIG. 5 is a circuit diagram of an adjustable resistor array circuit according to another embodiment of the present application;
fig. 6 is a timing diagram of a control for generating a constant reference current according to an embodiment of the present disclosure.
100 first circuit
110 band gap reference source
120 operational amplifier
200 current mirror
210 first MOS transistor
220 second MOS transistor
230 power supply
300 adjustable resistor array circuit
310 first resistance
320 first control switch
330 parallel branch
340 second resistance
350 second control switch
400 second circuit
410 timer
411D flip-flop
412 decoder
413 digital comparator
420 control circuit
421 first D flip-flop
422 digital logic controller
430 comparator
500 clock circuit
600 switching circuit
610 control switch
620 gating module
700 first capacitance
800 second capacitance
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and those skilled in the art will be able to make similar modifications without departing from the spirit of the application and it is therefore not intended to be limited to the embodiments disclosed below.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, an embodiment of the present application provides a chip for generating a constant reference current, including: the first circuit 100, the current mirror 200, the adjustable resistor array circuit 300, the second circuit 400, the clock circuit 500, and the switch circuit 600.
The first circuit 100 is used for outputting a reference voltage. An input of the current mirror 200 is connected to a first output of the first circuit 100. A first output of the current mirror 200 is connected to an input of the first circuit 100. The output of the adjustable resistor array circuit 300 is connected to the input of the first circuit 100.
A first input of the second circuit 400 is connected to a second output of the first circuit 100. A first output of the second circuit 400 is connected to an input of the adjustable resistor array circuit 300. An output of the clock circuit 500 is connected to a second input of the second circuit 400.
A first input of the switching circuit 600 is connected to a second output of the current mirror 200. A second input of the switching circuit 600 is connected to a second output of the second circuit 400. A first output terminal of the switch circuit 600 is connected to a third input terminal of the second circuit 400 and the first capacitor 700, respectively. A second output terminal of the switching circuit 600 is connected to ground.
The first circuit 100 is further configured to output a voltage regulation signal to the current mirror 200. The second circuit 400 is configured to output an adjustment signal for adjusting the resistance of the adjustable resistor array circuit 300, and output a control signal for controlling the switch circuit 600 to open or close.
The first circuit 100 is configured to output a reference voltage to the current mirror 200, and output a voltage adjustment signal to the current mirror 200 based on a feedback voltage of the adjustable resistor array circuit 300. The specific structure of the first circuit 100 is not particularly limited as long as the functions of outputting a reference voltage and outputting a voltage adjustment signal to the current mirror based on the feedback voltage of the adjustable resistor array circuit 300 can be realized. In one embodiment, the first circuit 100 may be composed of a voltage reference source and a first operational amplifier. The voltage reference source outputs a reference voltage to the current mirror 200 through the first operational amplifier. Meanwhile, the first operational amplifier receives the feedback voltage of the adjustable resistor array circuit 300 and outputs a voltage adjustment signal to the current mirror 200 based on the feedback voltage and the reference voltage. The above function can be realized by the voltage reference source and the first operational amplifier.
The current mirror 200 receives the reference voltage output by the first circuit 100, and outputs a reference current to the adjustable resistor array circuit 300 through a first output terminal according to the reference voltage. And the reference current output from the first output terminal is copied to the second output terminal and output to the switch circuit 600. The specific structure of the current mirror 200 is not particularly limited as long as the reference current output from the first output terminal can be copied to the second output terminal and then output.
The adjustable resistor array circuit 300 receives the resistance value adjusting signal output by the second circuit 400, and generates an electrical feedback voltage according to the reference current output by the first output terminal of the current mirror 200 and the self-adjusted resistance value, and outputs the electrical feedback voltage to the first circuit 100. The specific structure of the adjustable resistor array circuit 300 is not limited, as long as the function of generating the feedback voltage based on the resistance value adjusting signal and the reference current and the self-adjusted resistance value and outputting the feedback voltage to the first circuit 100 can be realized.
The second circuit 400 outputs an adjustment signal for adjusting the resistance of the adjustable resistor array circuit 300 and a control signal for controlling the switch circuit 600 to open or close based on the reference clock generated by the clock circuit 500 and the voltage on the first capacitor 700. The specific structure of the second circuit 400 is not limited, as long as the functions of outputting an adjustment signal for adjusting the resistance of the adjustable resistor array circuit 300 and outputting a control signal for controlling the on/off of the switch circuit 600 can be achieved. In one embodiment, the second circuit 400 may be composed of a digital control circuit, a second operational amplifier, and a first timer. Specifically, the digital control circuit may be a conventional digital control circuit.
The clock circuit 500 is used to generate a reference clock. The specific structure of the clock circuit 500 may not be particularly limited as long as the function of generating the reference clock can be realized. In one embodiment, the reference clock is generated by a crystal oscillator. It is understood that the specific structure of the switch circuit 600 is not limited specifically, as long as the function of switching according to the control signal output by the second circuit 400 can be ensured. In one embodiment, the switching circuit 600 is a single pole double throw relay switch.
In this embodiment, the reference current can be corrected by the cooperation of the first circuit 100, the current mirror 200, the adjustable resistor array circuit 300, the second circuit 400, the clock circuit 500, and the switch circuit 600, so that the reference current output is constant. Simultaneously, peripheral elements and pins do not need to be added, and the method and the device have the advantages of being simple in design and strong in compatibility.
Referring to fig. 2, in one embodiment, the first circuit 100 includes the bandgap reference source 110 and the operational amplifier 120. The output terminal of the bandgap reference source 110 is connected to the first input terminal of the second circuit 400. The bandgap reference source 110 is used to generate a bandgap reference voltage. A first input terminal of the operational amplifier 120 is connected to an output terminal of the bandgap reference source 110. A second input terminal of the operational amplifier 120 is connected to an output terminal of the adjustable resistor array circuit 300. The output of the operational amplifier 120 is connected to the input of the current mirror 200. The operational amplifier 120 outputs the voltage adjustment signal to the current mirror 200 based on the reference voltage and the feedback voltage output from the output terminal of the adjustable resistor array circuit 300.
It is understood that the first circuit 100 includes, but is not limited to, the bandgap reference source 110 and the operational amplifier 120. In one embodiment, the operational amplifier 120 may be replaced with a first comparator, which is easy to implement. Similarly, the bandgap reference source 110 can be replaced by a component that performs the same function as the bandgap reference source 110, such as a conventional voltage source.
In one embodiment, the second circuit 400 includes the timer 410, the control circuit 420, and the comparator 430. An input of the timer 410 is connected to an output of the clock circuit 500. The output terminals of the control circuit 420 are respectively connected to the second input terminals of the switch circuit 600. A first input of the control circuit 420 is connected to an output of the timer 410. A first input of the comparator 430 is connected to a second output of the first circuit 100. A second input of the comparator 430 is connected to a first output of the switching circuit 600. An output terminal of the comparator 430 is connected to a second input terminal of the control circuit 420.
The control circuit 420 receives a timing completion signal output from the timer 410 and a high level or a low level output from the comparator 430. The control circuit 420 outputs an adjustment signal for adjusting the resistance of the adjustable resistor array circuit 300 based on the timing completion signal and the high level or the low level, and outputs a control signal for controlling the switching of the switch circuit 600. Thereby completing control of the adjustable resistor array circuit 300 and the switch circuit 600. The specific structure of the control circuit 420 is not particularly limited, as long as the functions of outputting an adjustment signal for adjusting the resistance of the adjustable resistor array circuit 300 and outputting a control signal for controlling the on/off of the switch circuit 600 can be achieved.
Referring to fig. 3, in one embodiment, the timer 410 includes a plurality of cascaded D flip-flops 411, a decoder 412 and a digital comparator 413. The pulse input terminal of the D flip-flop 411 of the first stage is connected to the output terminal of the clock circuit 500. The Q output of the D flip-flop 411 of each stage is connected to the input of the decoder 412. An output of the decoder 412 is connected to a first input of the digital comparator 413. A second input of the digital comparator 413 is connected to an output of the preset target value. An output of the digital comparator 413 is coupled to a first input of the control circuit 420.
The Q output of the first stage D flip-flop 411 is also connected to the pulse input of the second stage D flip-flop 411. The Q output of the second stage D flip-flop 411 is also connected to the pulse input of the third stage D flip-flop 411. By analogy, the Q output terminal of the D flip-flop 411 of the M-1 th stage is further connected to the pulse input terminal of the D flip-flop 411 of the M-th stage.
In one embodiment, the clock circuit 500 inputs a clock signal to the pulse input terminal of the D flip-flop 411 in the first stage. The result output from the Q output of the D flip-flop 411 at each stage is input to the decoder 412 for decoding. The comparison with the preset target value (a) is performed by implementing a digital comparator 413. The plurality of cascaded D flip-flops 411 flip-flops increments by 1 at a rising edge of each clock, outputs a timing completion signal when an output value of the timer 410 reaches a preset target value (a), and resets the plurality of cascaded D flip-flops 411. Wherein A is a positive integer.
In one embodiment, the number (H) of D flip-flops 411 is related to a counting duration, which is related to a preset target value. The number of D flip-flops 411: h > -log 2(N +1), N being a positive integer. In one embodiment, when N is 1023, at least 10D flip-flops 411 are needed.
In one embodiment, the control circuit 420 includes the first D flip-flop 421 and the digital logic controller 422. The pulse input terminal of the first D flip-flop 421 is connected to the output terminal of the timer 410. The D input of the first D flip-flop 421 is connected to the output of the comparator 430. A first input of the digital logic controller 422 is connected to an output of the timer 410. The Q output terminal of the first D flip-flop 421 and the Q non-output terminal of the first D flip-flop 421 are both connected to the second input terminal of the digital logic controller 422. A first output of the digital logic controller 422 is coupled to an input of the adjustable resistor array circuit 300. A second output of the digital logic controller 422 is connected to a second input of the switch circuit 600.
At the beginning of each cycle of the timer 410, the first capacitor 700 is connected to a current source through the switch circuit 600, and the first capacitor 700 is charged. When the timer 410 completes the counting period, the output of the digital comparator 413 has a rising edge, and the D input terminal of the first D flip-flop 421 is connected to the output terminal of the comparator 430. If the comparator 430 outputs a high level, the high level is latched at the output terminal (control signal a) of the first D flip-flop 421, i.e., the Q output terminal of the first D flip-flop 421 and the Q non-output terminal of the first D flip-flop 421.
If the control signal a is at a high level, the digital logic controller 422 outputs an adjustment signal to decrease the resistance of the adjustable resistor array circuit 300. If the control signal a is low, the digital logic controller 422 outputs an adjustment signal to increase the resistance of the adjustable resistor array circuit 300. After each counting cycle is completed, a pulse adjustment signal (i.e., a control signal for controlling the switching circuit 600 to open and close) is output, thereby resetting the capacitor voltage (i.e., grounding the first capacitor 700). At the same time, the adjustable resistor array circuit 300 adjusts the resistance from the high position.
In one embodiment, the adjustable resistor array circuit 300 includes: a plurality of series connected first resistors 310. One end of a plurality of resistors 310 connected in series is connected to the input end of the first circuit 100. The other ends of the plurality of series-connected first resistors 310 are grounded. Each of the first resistors 310 is connected in parallel with a first control switch 320. A control signal input terminal of each of the first control switches 320 is connected to a first output terminal of the second circuit 400.
When the adjustable resistor array circuit 300 adopts a series resistor array, the precision of the resistor to be adjusted is higher than 1%. In one embodiment, the number of the first resistors 310 is at least six. Meanwhile, the impedance of the selected first control switch 320 needs to be as small as possible, so as to avoid affecting the resistance adjustment of the adjustable resistor array circuit 300.
In one embodiment, the adjustable resistor array circuit 300 includes a plurality of parallel branches 330. One end of each of the parallel branches 330 is connected to an input terminal of the first circuit 100. The other end of each of the parallel branches 330 is grounded. Each of the parallel branches 330 includes a second resistor 340 and a second control switch 350 connected in series with the second resistor 340. A control signal input terminal of each of the second control switches 350 is connected to a first output terminal of the second circuit 400.
When the adjustable resistor array circuit 300 adopts a parallel resistor array, the precision of the resistor to be adjusted is higher than 1%. In one embodiment, the number of branches of the parallel branches 330 is at least six. Meanwhile, the impedance of the selected second control switch 350 needs to be as small as possible, so as to avoid affecting the resistance adjustment of the adjustable resistor array circuit 300.
In one embodiment, the switching circuit 600 includes the control switch 610 and the gating module 620. A first input of the control switch 610 is connected to a second output of the current mirror 200. A second input of the control switch 610 is connected to a second output of the second circuit 400. A second output of the control switch 610 is connected to ground. An input terminal of the gating module 620 is connected to a first output terminal of the control switch 610. The output terminal of the gating module 620 is connected to the third input terminal of the second circuit 400 and the first capacitor 700, respectively.
The specific structure of the control switch 610 is not particularly limited as long as the function of opening and closing based on the control signal can be realized. In one embodiment, the control switch 610 may be a relay switch. The gating module 620 has the function that when no proper off-chip capacitor (i.e. the first capacitor 700) exists, the gating module 620 can be connected to the on-chip capacitor (i.e. the second capacitor 800) for adjustment, and the gating module has the characteristic of strong applicability.
In one embodiment, the chip further comprises a second capacitor 800. The input terminal of the second capacitor 800 is connected to the first output terminal of the switch circuit 600. The output of the second capacitor 800 is connected to ground. When the chip performs the reference current calibration, if there is no suitable off-chip capacitor (i.e. the first capacitor 700), the chip can be connected to the second capacitor 800 (i.e. the on-chip capacitor) through the gating module 620 for adjustment, so that the chip has the characteristic of strong applicability.
Referring to fig. 2, in an embodiment, the current mirror 200 includes the first MOS transistor 210 and the second MOS transistor 220. The gate of the first MOS transistor 210 is connected to the first output terminal of the first circuit 100. The drain of the first MOS transistor 210 is connected to the input of the first circuit 100. The gate of the second MOS transistor 220 is connected to the first output terminal of the first circuit 100. The drain of the second MOS transistor 220 is connected to the first input terminal of the switch circuit 600. The source of the second MOS transistor 220 is connected to the source of the first MOS transistor 210.
In one embodiment, the current mirror 200 may implement current replication using PMOS transistors. When the PMOS transistor is used specifically, the size of the PMOS transistor can be selected according to different processes, and in order to meet the requirement of high output impedance, the long-channel PMOS transistor is generally adopted. In one embodiment, the source of the second MOS transistor 220 and the source of the first MOS transistor 210 are both electrically connected to a power supply 230. The required power is provided by power supply 230.
Referring to fig. 6, the charging voltage of the capacitor (i.e., the first capacitor 700) is compared with a reference level (i.e., a reference voltage). The charging duration is (capacitance value is reference voltage)/charging current, and the timing duration is reference clock period is number of clocks (i.e. the number of clock timing).
When the charging duration is longer than the timing length, the control circuit (i.e., the second circuit 400) adjusts the charging current by adjusting the resistor array (i.e., the adjustable resistor array circuit 300), and re-times the capacitor charging until the charging duration is equal to the timing length, and the adjustment is finished. At this time, the charging current (final value) is the timing length/(capacitance value × reference voltage), and all three parameters on the right side of the equation are independent of the chip process, i.e., the charging current (final value) does not change with the chip process. The charging current (final value) output can be used as a bias current (i.e., reference current) by current mirror replication.
The reference voltage is generated by the bandgap reference source 110, and the adjustable off-chip capacitor (i.e. the first capacitor 700) charging current is generated by the adjustable resistor array circuit 300 and the current mirror 200 through biasing. The off-chip capacitor is charged for a fixed time by the cooperation of the clock circuit 500 and the timer 410. The off-chip capacitor voltage is compared with a reference voltage by the comparator 430 at the end of charging. And adjusting the resistance value of the adjustable capacitor array circuit 300 according to the comparison result, and changing the charging current to enable the voltage of the capacitor after each charging to gradually approach the reference voltage. The configuration closest to the primary charging current is the reference current.
The adjustment process of the present application is as follows:
first, the bandgap reference source 110 provides a reference bias voltage Vref, and a current i1 ═ Vref/Rtrim is generated on the current mirror 200 through the operational amplifier 120 and the adjustable resistor array Rtrim (i.e. the adjustable resistor array circuit 300). I1 (i.e. the current output by the first output terminal of the current mirror 200) is then copied by the current mirror 200 to the external capacitor (i.e. the first capacitor 700) charging current source i2 (i.e. the current output by the second output terminal of the current mirror 200), i2 ═ i 1.
Next, the charging time is clocked by a reference clock Fin generated by a crystal oscillator (i.e., the clock circuit 500) and the timer 410 (counting K) (the capacitor charge is discharged to 0 before charging), and the charging time period is Tch ═ K/Fin. At the end of the charging, the voltage across the first capacitor 700(CO) is Vcap — i2 × Tch/C0 — i2 × K/(Fin × C0). Then, Vcap is compared with Vref using the comparator 430, and if Vcap is smaller than Vref, Rtrim is adjusted so that i1 increases. If Vcap is greater than Vref, Rtrim is adjusted such that i1 is decreased.
Finally, the above process is repeated to make Vcap equal to Vref, where i1 is i2 is Vref Fin C0/K. Because the error between the crystal oscillator frequency Fin and the first capacitor 700(CO) is very small, the constant bias current i1 (i.e., the reference current) can be output by selecting proper Vref, Fin, K and C0 according to the actual circuit design.
In summary, the reference current can be corrected by the cooperation of the first circuit 100, the current mirror 200, the adjustable resistor array circuit 300, the second circuit 400, the clock circuit 500 and the switch circuit 600, so that the reference current output is constant. Simultaneously, peripheral elements and pins do not need to be added, and the method and the device have the advantages of being simple in design and strong in compatibility. The method and the device can be used for performing the correction process and other functions of the chip in parallel, and the use of other functions of the chip is not influenced during correction. If the temperature detection control module is matched with the temperature detection control module and the like, the influence of the bias current on the temperature change can be further reduced.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A chip for generating a constant reference current, comprising:
a first circuit (100) for outputting a reference voltage;
a current mirror (200), wherein an input end of the current mirror (200) is connected with a first output end of the first circuit (100), a first output end of the current mirror (200) is connected with an input end of the first circuit (100), and the current mirror (200) is used for copying the reference current output by the first output end to a second output end and outputting a corrected reference current;
an adjustable resistor array circuit (300), an output terminal of the adjustable resistor array circuit (300) being connected to an input terminal of the first circuit (100);
a second circuit (400), a first input of the second circuit (400) being connected to a second output of the first circuit (100), a first output of the second circuit (400) being connected to an input of the adjustable resistor array circuit (300);
a clock circuit (500), an output of the clock circuit (500) being connected to a second input of the second circuit (400);
a first input end of the switch circuit (600) is connected with a second output end of the current mirror (200), a second input end of the switch circuit (600) is connected with a second output end of the second circuit (400), a first output end of the switch circuit (600) is respectively connected with a third input end of the second circuit (400) and the first capacitor (700), and a second output end of the switch circuit (600) is grounded;
the current mirror (200) is further configured to receive a reference voltage output by the first circuit (100), and output a reference current to the adjustable resistor array circuit (300) through a first output terminal according to the reference voltage; the adjustable resistor array circuit (300) receives a resistance value adjusting signal output by the second circuit (400), generates an electric feedback voltage according to the reference current output by the first output end of the current mirror (200) and the self-adjusted resistance value, and outputs the electric feedback voltage to the first circuit (100);
the first circuit (100) is further configured to output a voltage regulation signal to the current mirror (200); the second circuit (400) is used for outputting an adjusting signal for adjusting the resistance value of the adjustable resistor array circuit (300) and outputting a control signal for controlling the switch circuit (600) to be switched on and switched off; the second circuit (400) is further configured to: the adjustable resistor array circuit (300) is controlled, the current mirror (200) is enabled to generate a charging current of the first capacitor (700) in a biased mode, then the first capacitor (700) is charged in a fixed time through matching with the clock circuit (500), when charging is finished, the charging current is changed through comparing the charging voltage of the first capacitor (700) with the reference voltage and adjusting the resistance value of the adjustable resistor array circuit (300) according to the comparison result, the voltage of the capacitor after charging at each time is enabled to gradually approach the reference voltage until the difference value of the charging voltage and the reference voltage is within a preset range, and the closest one-time charging current is configured to be the reference current.
2. Chip for generating a constant reference current according to claim 1, characterized in that said first circuit (100) comprises:
a bandgap reference source (110), an output terminal of the bandgap reference source (110) being connected to a first input terminal of the second circuit (400), the bandgap reference source (110) being configured to generate a bandgap reference voltage;
an operational amplifier (120), a first input terminal of the operational amplifier (120) is connected to an output terminal of the bandgap reference source (110), a second input terminal of the operational amplifier (120) is connected to an output terminal of the adjustable resistor array circuit (300), an output terminal of the operational amplifier (120) is connected to an input terminal of the current mirror (200), and the operational amplifier (120) outputs the voltage adjusting signal to the current mirror (200) based on the reference voltage and a feedback voltage output from an output terminal of the adjustable resistor array circuit (300).
3. Chip for generating a constant reference current according to claim 1, characterized in that said second circuit (400) comprises:
a timer (410), an input of the timer (410) being connected to an output of the clock circuit (500);
the output ends of the control circuits (420) are respectively connected with the second input ends of the switch circuits (600), and the first input end of the control circuit (420) is connected with the output end of the timer (410);
a comparator (430), a first input of the comparator (430) being connected to the second output of the first circuit (100), a second input of the comparator (430) being connected to the first output of the switch circuit (600), an output of the comparator (430) being connected to the second input of the control circuit (420).
4. A chip for generating a constant reference current according to claim 3, wherein the timer (410) comprises:
a plurality of cascaded D flip-flops (411), wherein the pulse input end of the D flip-flop (411) of the first stage is connected with the output end of the clock circuit (500);
a decoder (412), wherein the Q output of each stage of the D flip-flop (411) is connected with the input of the decoder (412);
and the output end of the decoder (412) is connected with a first input end of the digital comparator (413), a second input end of the digital comparator (413) is connected with the output end of the preset target value, and the output end of the digital comparator (413) is connected with a first input end of the control circuit (420).
5. A chip for generating a constant reference current according to claim 3, wherein the control circuit (420) comprises:
a first D flip-flop (421), wherein a pulse input end of the first D flip-flop (421) is connected with an output end of the timer (410), and a D input end of the first D flip-flop (421) is connected with an output end of the comparator (430);
a digital logic controller (422), a first input end of the digital logic controller (422) is connected with an output end of the timer (410), a Q output end of the first D trigger (421) and a Q non-output end of the first D trigger (421) are both connected with a second input end of the digital logic controller (422), a first output end of the digital logic controller (422) is connected with an input end of the adjustable resistor array circuit (300), and a second output end of the digital logic controller (422) is connected with a second input end of the switch circuit (600).
6. The chip for generating a constant reference current according to claim 1, wherein the adjustable resistor array circuit (300) comprises:
a plurality of first resistors (310) connected in series, one end of each of the plurality of first resistors (310) connected in series being connected to an input terminal of the first circuit (100), and the other end of each of the plurality of first resistors (310) connected in series being grounded; wherein the content of the first and second substances,
each first resistor (310) is connected in parallel with a first control switch (320), and a control signal input end of each first control switch (320) is connected with a first output end of the second circuit (400).
7. The chip for generating a constant reference current according to claim 1, wherein the adjustable resistor array circuit (300) comprises:
a plurality of parallel branches (330), one end of each parallel branch (330) is connected with the input end of the first circuit (100), and the other end of each parallel branch (330) is grounded; wherein the content of the first and second substances,
each parallel branch (330) comprises a second resistor (340) and a second control switch (350) connected with the second resistor (340) in series, and a control signal input end of each second control switch (350) is connected with a first output end of the second circuit (400).
8. The chip for generating a constant reference current according to claim 1, wherein the switching circuit (600) comprises:
a control switch (610), a first input terminal of the control switch (610) is connected with a second output terminal of the current mirror (200), a second input terminal of the control switch (610) is connected with a second output terminal of the second circuit (400), and a second output terminal of the control switch (610) is grounded;
the input end of the gating module (620) is connected with the first output end of the control switch (610), and the output end of the gating module (620) is respectively connected with the third input end of the second circuit (400) and the first capacitor (700).
9. The chip for generating a constant reference current according to claim 1, further comprising:
and the input end of the second capacitor (800) is connected with the first output end of the switch circuit (600), and the output end of the second capacitor (800) is grounded.
10. Chip for generating a constant reference current according to claim 1, characterized in that said current mirror (200) comprises:
the grid electrode of the first MOS tube (210) is connected with the first output end of the first circuit (100), and the drain electrode of the first MOS tube (210) is connected with the input end of the first circuit (100);
the grid electrode of the second MOS tube (220) is connected with the first output end of the first circuit (100), the drain electrode of the second MOS tube (220) is connected with the first input end of the switch circuit (600), and the source electrode of the second MOS tube (220) is connected with the source electrode of the first MOS tube (210).
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