JP2000330657A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a current mirror circuit whose output dynamic range and output impedance is large without causing the remarkable increase of the scale and area of a circuit. SOLUTION: This semiconductor device is provided with a first current source 6 whose one end is connected with Vcc, a first MOS transistor 12 whose drain and gate are connected with the other end of the first current source, a second MOS transistor 14 whose gate is connected with the gate of the first MOS transistor, and whose drain is connected with an output terminal 7, a third MOS transistor 11 whose source is connected with Vss, and whose drain is connected with the source of the first MOS transistor, a fourth MOS transistor 13 whose source is connected with Vss, and whose drain is connected with the source of the second MOS transistor, a fifth MOS transistor 15 whose source is connected with Vss, and whose drain and gate are connected with the gates of the third and fourth MOS transistors, and a second current source 10 whose one end is connected with Vcc, and whose other end is connected with the drain and gate of the fifth MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a MOS transistor, and more particularly to a semiconductor device in which a MOS transistor is cascode-connected to form a current mirror circuit.

[0002]

2. Description of the Related Art Conventionally, a MOS transistor has been set to "0".
And "1" are used exclusively for digital circuits that handle digital signals. On the other hand, it has been strongly demanded in recent years to mix analog circuits in such MOS transistors and to reduce the gate length to promote high integration of the circuits. Here, an example of a conventional semiconductor device formed with such MOS transistors is shown in FIG. This semiconductor device has a drain and gate interconnected PM.
The OS transistors 21 and 22 and the current source 20 are connected to the power supply potential V.
cc and the ground potential Vss, and the PMOS transistors 23 and 24 whose respective gates are connected to the gates of the PMOS transistors 21 and 22 are connected to the power supply potential Vcc.
A current mirror circuit is formed by connecting the current mirror circuit and the output terminal 27. In other words, the current mirror circuit shown in FIG. 5 uses the pair of cascode-connected PMOS transistors 23 and 24 in consideration of the increase in the channel length modulation effect which is remarkable in a fine MOS transistor, and thereby allows the output terminal 27 and the like to be used. Thus, the variation in the amount of current due to the voltage change in the above is suppressed, and the output impedance is improved. However, in this case, the PMO operating in the saturation region
The output dynamic range is reduced by an amount corresponding to the voltage drop between the drain and the source of the S-transistor 23, which tends to be an obstacle in reducing the power consumption due to the low-voltage operation of the circuit.

On the other hand, a PMOS transistor 21,
22 and a pair of PMOS transistors 23 and 24,
By applying a predetermined bias to the pair of gates of the PMOS transistors 22 and 24 on the output terminal 27 side and controlling the operating voltages of the PMOS transistors 22 and 24,
A technology for reducing the voltage drop between the drain and the source of the transistors 21 and 23 and thereby improving the dynamic range of the output is disclosed in, for example, US Pat. No. 4,983,929. FIG. 6 is a circuit diagram of a conventional semiconductor device provided with a bias circuit for a current mirror circuit as described above. In FIG. 6, a PMOS transistor 25 having a drain and a gate interconnected and a current source 26 constitute a bias circuit for a current mirror circuit. The PMOS transistor 25 and the current source 26 are connected between the power supply potential Vcc and the ground potential Vss, and the drain and the gate of the PMOS transistor 25 are connected to the PMOS transistors 22, 2 on the output terminal 27 side in the current mirror circuit.
4 pairs of gates. In this semiconductor device, 2
When the current amounts of the two current sources 20 and 26 are equal, the ratio W / L of the channel width and length of the PMOS transistor 25 in the bias circuit is determined by the channel width and length of the PMOS transistors 21 to 24 forming the current mirror circuit. , The drain-source voltage of the PMOS transistors 21 and 23 can be set to an appropriate value, and as a result, the output dynamic range is improved.

[0004]

As described above, in the conventional semiconductor device shown in FIG. 6, the relationship between the channel width and length ratio W / L of the MOS transistors forming the bias circuit and the current mirror circuit. By controlling the operating region of the MOS transistor in the current mirror circuit, a voltage drop between the drain and the source of the MOS transistor can be suppressed, and a large output dynamic range can be obtained. However,
In order to set the voltage between the drain and the source of the MOS transistor to an appropriate value, the ratio W / L of the channel width and the length of the MOS transistor needs to be set to about four times or more on the current mirror circuit side and the bias circuit side. However, there is a problem that the circuit scale is significantly increased. Accordingly, an object of the present invention is to realize a current mirror circuit having a large output dynamic range and a large output impedance without increasing the circuit size so much in view of such a problem.

[0005]

In order to achieve the above object, the present invention provides a first current source having one end connected to a first potential supply node, and a drain and a gate connected to the first current source. A first MOS transistor connected to the other end of the source, a second MOS transistor having a gate connected to the gate of the first MOS transistor, a drain connected to the output terminal, and a source connected to the second MOS transistor. And a drain connected to the potential supply node of the third MOS transistor and a source connected to the source of the first MOS transistor.
A transistor, a fourth MOS transistor having a source connected to the second potential supply node and a drain connected to the source of the second MOS transistor, and gates of the third and fourth MOS transistors And a bias circuit for operating the third and fourth MOS transistors in a linear region. That is, the semiconductor device of the present invention is characterized in that a bias circuit is connected to the gates of a pair of MOS transistors far from the output terminal in a current mirror circuit using cascode-connected MOS transistors. According to the present invention, for example, the MO in the circuit
Even if the ratio W / L between the channel width and the length of the S transistor is not made so different, it is possible to operate the MOS transistor connected to the bias circuit in a linear region and sufficiently reduce the drain-source voltage thereof. Becomes Therefore,
The dynamic range of the output can be improved without significantly increasing the circuit scale.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. In this example, a current mirror circuit and a bias circuit are formed using PMOS transistors. That is, the PMOS transistor 1 whose drain and gate are interconnected,
2 and the current source 6 are connected between the power supply potential Vcc and the ground potential Vss, and the respective gates of the PMOS transistors 1 and 2 are connected to the gates of the PMOS transistors 1 and 2,
4 is connected between the power supply potential Vcc and the output terminal 7 to form a current mirror circuit 8. In addition, the ratios W / L of the channel widths and the lengths of the PMOS transistors 1 to 4 cascode-connected in this way are all substantially the same. It is connected. The bias circuit 9 supplies a predetermined gate voltage to the PMOS transistors 1 and 3 in the current mirror circuit 8 and operates in a linear region. These PMOS transistors 1, 3
Are PMOS transistors 2, 4 as described above, respectively.
And all the PMOS transistors 1 to 4 have substantially the same channel width to length ratio W / L. As a result, the PMOS transistor 1,
3, the voltage between the drain and the source is substantially equal to each other,
In addition, the value is sufficiently small.

Therefore, the cascode-connected P on the input side
The current flowing through the MOS transistors 1 and 2 is accurately turned back to the PMOS transistors 3 and 4 cascode-connected on the output side, and a large output dynamic range is obtained from the output terminal 7. In addition, by using the pair of the cascode-connected PMOS transistors 1 to 4, the PMOS transistors 3 and 4 are hardly affected by the voltage change of the output terminal 7 and generate a drain current with small voltage dependency. As a result, a current mirror circuit having a large output impedance can be formed. Next, FIG. 2 shows a specific circuit configuration of the semiconductor device according to the first embodiment of the present invention. That is, the bias circuit 9 in FIG. 1 comprises a PMOS transistor 5 and a current source 10 having a drain and a gate interconnected, and these are connected between the power supply potential Vcc and the ground potential Vss. A connection point between the drain and gate of the PMOS transistor 5 and the current source 10 is connected to a pair of gates of the PMOS transistors 1 and 3 in the current mirror circuit 8, and the current mirror circuit 8
Supply a bias to Here, the bias circuit 9
To operate the pair of the PMOS transistors 1 and 3 in the current mirror circuit 8 to which the current source 6 and the bias circuit 9 of the current mirror circuit 8 are connected in a linear region, for example,
Of the PMOS transistor 5 in the bias circuit 9 so that the ratio W / L of the channel width to the length of the PMOS transistor 5 in the bias circuit 9 is smaller than that of the PMOS transistors 1-4 in the current mirror circuit 8. What is necessary is just to form. Alternatively, assuming that the ratio W / L of the channel width and length of all the PMOS transistors 1 to 5 is substantially the same, the current amount of the current source 10 in the bias circuit 9 is made smaller than the current amount of the current source 6 in the current mirror circuit 8. The ratio W / L of the channel width and the length of the PMOS transistor 5 may be reduced and the current amount of the current source 10 may be increased on the bias circuit 9 side with respect to the current mirror circuit 8. It is possible.

That is, the bias circuit 9 described above
Is connected to the gate of the PMOS transistor 1,
The PMOS transistor 1 and the PMOS transistor 5 in the bias circuit 9 form a pair. Here, if the PMOS transistor 1 operates in the saturation region, the amount of current I flowing from the current source 6 of the current mirror circuit 8
A larger drain current should be obtained with PMOS transistor 1. However, in the circuit configuration shown in FIG.
Since a current flows to the current source 6 via the transistor 2,
Actually, the PMOS transistor 1 operates in the linear region,
The drain current is self-biased to a drain voltage that is substantially equal to the current amount I of the current source 6. In this way, the PMOS transistor 1 having the gate connected to the bias circuit 9 and the PMOS transistor paired with the PMOS transistor 1 in the current mirror circuit 8 are all controlled to operate in the linear region. The voltage between drain and source in 1 and 3 can be sufficiently reduced. Here, when the current amounts of the two current sources 6 and 10 in the circuit are made equal, the ratio W / L of the channel width and the length of the PMOS transistors 1 to 4 of the current mirror circuit 8 becomes the bias circuit 9 It is desirable that the ratio is not less than 1.2 times and not more than 3 times the ratio W / L of the channel width and the length of the middle MOS transistor 5. When the ratio W / L of the channel width to the length of all the PMOS transistors 1 to 5 is the same, the preferable current amount of the current source 10 in the bias circuit 9 is the current amount of the current source 6 in the current mirror circuit 8. It is 1.2 times or more and 3 times or less of the amount. That is, in any case, if less than 1.2 times, the improvement of the dynamic range of the output due to the provision of the bias circuit 9 is small, and if more than three times, the circuit area increases, and the output impedance decreases. Tend to.

FIG. 3 shows a semiconductor device according to a second embodiment of the present invention. In this semiconductor device, each PMOS transistor in the semiconductor device of the first embodiment is replaced with NMOS transistors 11 to 15, respectively, and the same parts as those of the semiconductor device shown in FIG. Detailed description is omitted. Also in this semiconductor device, the bias circuit 9 is connected to the N
Operating the MOS transistors 11 and 13 in the linear region,
The voltage drop between the drain and the source of the NMOS transistors 11 and 13 is suppressed, and a large output dynamic range can be obtained from the output terminal 7. By using a pair of cascode-connected NMOS transistors 11 to 14, a current mirror circuit having a large output impedance can be formed as in the case of the first embodiment. In the semiconductor device shown in FIG. 3, the ratio W / L of channel width to length of NMOS transistors 11 to 15 and
The optimum conditions for the current amounts of the current sources 6 and 10 in the current mirror circuit 8 and the bias circuit 9 are exactly the same as those in FIG. Here, FIG. 4 shows a simulation of the semiconductor device of the second embodiment under the optimum conditions regarding the current amount of the current sources 6 and 10 in the current mirror circuit 8 and the bias circuit 9. That is, FIG.
For all the NMOS transistors 11 to 15 in the circuit, the ratio W / L of the channel width to the length is formed equal, and the current source on the bias circuit 9 side with respect to the current amount I of the current source 6 in the current mirror circuit 8 10 when the ratio I ′ / I of the current amount I ′ of FIG.
13 shows a drain-source voltage Vds.

In the figure, when the current amount ratio I '/ I of the current sources 6 and 10 is 1, the same current amount is supplied from the current sources 6 and 10 in the current mirror circuit 8 and the bias circuit 9, respectively. The amount of drain current when the NMOS transistor 11 shown in FIG. 3 operates in the saturation region;
The current amounts I flowing from the current sources 6 of the current mirror circuit 8 are equal to each other. As a result, the NMOS transistor 11 and the NMOS transistor 13 forming a pair in the current mirror circuit 8 operate in a saturation region where a large drain-source voltage Vds occurs, and the obtained output dynamic range is biased. This is equivalent to the conventional semiconductor device shown in FIG. 5 having no circuit. on the other hand,
The ratio I '/ of the current amount I' of the current source 10 in the bias circuit 9 to the current amount I of the current source 6 in the current mirror circuit 8
As I is increased, the current sources 6, 10
Is about 1.1, the drain-source voltage Vds is significantly reduced. Therefore, considering the margin for the manufacturing variation of the circuit, the current source 6,
It can be seen that the current ratio I ′ / I of 10 is preferably about 1.2 times or more. In addition, when the current amount ratio I ′ / I of the current sources 6 and 10 exceeds 3 times and is in an excessively large range, the voltage Vds between the drain and the source decreases very little, causing an unnecessary increase in circuit area. It is clear that

Further, here, the optimum conditions regarding the current amount of the current source 6 in the current mirror circuit 8 and the current amount of the current source 10 on the bias circuit 9 side are particularly shown. In this case, the ratio W / L of the channel width and the length of the NMOS transistors 11 to 15 in the current mirror circuit 8 and the bias circuit 9 is determined based on the ratio W / L of the current mirror circuit 9 to the bias circuit 9.
, And the same relationship holds between the drain-source voltage Vds. Further, such a relationship is naturally applied to the semiconductor device shown in FIG. 2 using the PMOS transistor in the same manner. The bias circuit according to the present invention is not particularly limited to those shown in FIGS. 2 and 3 as long as a predetermined MOS transistor in the current mirror circuit can operate in a linear region. For example, a resistance element may be used in place of the MOS transistor in the bias circuit, and various modifications may be made without departing from the spirit of the present invention.

[0012]

As described above in detail, according to the present invention, it is possible to provide a current mirror circuit having a large output dynamic range and a large output impedance without significantly increasing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a specific circuit configuration of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a diagram illustrating a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining an optimum condition regarding a current amount of a current source in a current mirror circuit and a bias circuit.

FIG. 5 is a diagram illustrating an example of a conventional semiconductor device.

FIG. 6 is a diagram showing a conventional semiconductor device provided with a bias circuit for a current mirror circuit.

[Explanation of symbols]

1-5 PMOS transistor, 6, 10 current source, 7 output terminal, 8 current mirror circuit, 9
.Bias circuits, 11-15..NMOS transistors

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5H420 NB03 NB12 NB25 NB36 5J091 AA01 AA43 CA32 CA73 CA92 FA16 HA10 HA16 HA25 KA05 KA09 KA12 MA17 MA21 TA02 5J092 AA01 AA43 CA32 CA73 CA92 FA16 HA10 HA16 HA25 KA05 MA21

Claims (8)

[Claims] A first current source having one end connected to a first potential supply node; a first MOS transistor having a drain and a gate connected to the other end of the first current source; A second MOS transistor connected to a gate of the first MOS transistor and having a drain connected to an output terminal;
And a source connected to the second potential supply node,
A third MOS transistor having a drain connected to the source of the first MOS transistor; a source connected to the second potential supply node; and a drain connected to the source of the second MOS transistor. A semiconductor device comprising: a fourth MOS transistor; and a bias circuit connected to the gates of the third and fourth MOS transistors and operating the third and fourth MOS transistors in a linear region. . 2. A bias circuit comprising: a second current source having one end connected to the first potential supply node; a source connected to the second potential supply node; and a drain and a gate connected to the second potential source. A fifth MOS transistor connected to the other end of the second current source, wherein a gate of the fifth MOS transistor in the bias circuit is connected to gates of the third and fourth MOS transistors. The semiconductor device according to claim 1, wherein: 3. A first current source having one end connected to a first potential supply node; a first MOS transistor having a drain and a gate connected to the other end of the first current source; A second MOS transistor connected to a gate of the first MOS transistor and having a drain connected to an output terminal;
And a source connected to the second potential supply node,
A third MOS transistor having a drain connected to the source of the first MOS transistor; a source connected to the second potential supply node; and a drain connected to the source of the second MOS transistor. A fourth MOS transistor, a fifth MOS transistor having a source connected to the second potential supply node, a drain and a gate connected to the gates of the third and fourth MOS transistors, and one end. A second current source connected to the first potential supply node and having the other end connected to a drain and a gate of the fifth MOS transistor. 4. The ratio of the channel width to the length of the first to fourth MOS transistors, wherein the current amount of the first current source and the current amount of the second current source are substantially the same. W / L
4. The semiconductor device according to claim 2, wherein the first and second MOS transistors are substantially equal to each other, and are larger than a ratio W / L of a channel width and a length of the fifth MOS transistor. 5. The ratio W / L of channel width and length of said first to fourth MOS transistors is at least 1.2 times the ratio W / L of channel width and length of said fifth MOS transistor. 5. The semiconductor device according to claim 4, wherein the value is set to three times or less. 6. The first to fifth MOS transistors have substantially the same channel width / length ratio W / L, and the second current source has a current amount of the first current source. 4. The semiconductor device according to claim 2, wherein the current amount is larger than the current amount. 7. The semiconductor according to claim 6, wherein a current amount of said second current source is set to be 1.2 times or more and 3 times or less of a current amount of said first current source. apparatus. 8. The device according to claim 1, wherein said first current source and said first to fourth MOS transistors form a current mirror circuit.
13. The semiconductor device according to item 9.