CN108242921B

CN108242921B - Latch and frequency divider

Info

Publication number: CN108242921B
Application number: CN201611232567.7A
Authority: CN
Inventors: 赵亮; 赖玠玮; 何济柔
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2016-12-27
Filing date: 2016-12-27
Publication date: 2021-06-04
Anticipated expiration: 2036-12-27
Also published as: CN108242921A; CN110474628A; CN110474628B

Abstract

The latch comprises a first logic unit, a second logic unit, a third logic unit, a fourth logic unit and a control unit; the first logic unit and the second logic unit have the same structure, the third logic unit and the fourth logic unit have the same structure, the first logic unit and the third logic unit are connected between a reference power supply and a reference ground wire in series, and the second logic unit and the fourth logic unit are connected between the reference power supply and the reference ground wire in series; and the control unit is suitable for controlling the current path where the first logic unit and the third logic unit are located or the current path where the second logic unit and the fourth logic unit are located to be disconnected when the latch is in a preset working condition. By the scheme, the power consumption of the latch of the high-speed frequency divider can be reduced under static and dynamic working conditions.

Description

Latch and frequency divider

Technical Field

The present invention relates to the field of electronic circuit technology, and in particular, to a latch and a frequency divider.

Background

With the development of communication technology, a high-speed frequency divider realized based on a razavi structural latch is widely applied due to the advantages of high speed and wide bandwidth.

The high-speed frequency divider circuit with the frequency division of two is composed of two stages of latches, wherein any latch is a post-stage unit of another latch.

However, the high-speed divide-by-two device in the prior art has a problem of large power consumption under both static operation conditions and dynamic operation conditions.

Disclosure of Invention

The embodiment of the invention solves the problem of reducing the power consumption of the latch of the high-speed frequency-halving circuit.

In order to solve the above problem, an embodiment of the present invention provides a latch, where the latch includes a first logic unit, a second logic unit, a third logic unit, a fourth logic unit, and a control unit; the first logic unit and the second logic unit have the same structure, the third logic unit and the fourth logic unit have the same structure, the first logic unit and the third logic unit are connected between a reference power supply and a reference ground wire in series, and the second logic unit and the fourth logic unit are connected between the reference power supply and the reference ground wire in series; the control unit is suitable for controlling the current path where the first logic unit and the third logic unit are located or the current path where the second logic unit and the fourth logic unit are located to be disconnected when the latch is under a preset working condition.

Optionally, the first logic unit includes a first PMOS transistor; the second logic unit comprises a second PMOS tube; the third logic unit comprises a first NMOS transistor and a third NMOS transistor; the fourth logic unit comprises a second NMOS transistor and a fourth NMOS transistor; the gate end of the first PMOS tube is coupled with the clock signal input end, the source end of the first PMOS tube is coupled with the reference power supply, and the drain end of the first PMOS tube is coupled with the control unit; the gate terminal of the second PMOS transistor is coupled to the input clock signal, the source terminal of the second PMOS transistor is coupled to the reference power supply, and the drain terminal of the second PMOS transistor is coupled to the control unit; the drain terminal of the first NMOS tube is coupled with the inverted clock signal output terminal, the gate terminal of the first NMOS tube is coupled with the clock signal output terminal, and the source terminal of the first NMOS tube is coupled with the reference ground wire; the drain terminal of the third NMOS tube is coupled with the inverted clock signal output terminal, the gate terminal of the third NMOS tube is coupled with the preceding-stage clock signal output terminal, and the source terminal of the third NMOS tube is coupled with the reference ground wire; the drain terminal of the second NMOS transistor is coupled to the clock signal output terminal, the gate terminal of the second NMOS transistor is coupled to the inverted clock signal output terminal, and the source terminal of the second NMOS transistor is coupled to the reference ground; the drain terminal of the third NMOS transistor is coupled to the clock signal output terminal, the gate terminal of the third NMOS transistor is coupled to the preceding-stage inverted clock signal output terminal, and the source terminal of the third NMOS transistor is coupled to the reference ground.

Optionally, the control unit is adapted to control a current path in which the first logic unit and the third logic unit are located or a current path in which the second logic unit and the fourth logic unit are located to be disconnected when the input clock signal at the latch falls and when the signal at the clock signal output end of the latch and the signal at the inverted clock signal output end of the latch are stable.

Optionally, the control unit comprises a first control subunit and a second control subunit; the first control subunit is adapted to control a current path in which the first logic unit and the third logic unit are located, or to control a current path in which the second logic unit and the fourth logic unit are located to be disconnected, when the signal of the clock signal output end and the signal of the inverted clock signal output end are stable; the second control subunit is adapted to control a current path in which the first logic unit and the third logic unit are located, or to control a current path in which the second logic unit and the fourth logic unit are located to be disconnected at the moment when the input clock signal falls.

Optionally, the first control subunit is adapted to, when the signal output by the clock signal output end and the signal output by the inverted clock signal output end are stable, control, by using the signal output by the clock signal output end, the current path where the first logic unit and the third logic unit are located to be disconnected, or control, by using the signal output by the inverted clock signal output end, the current path where the second logic unit and the fourth logic unit are located to be disconnected.

Optionally, the second control subunit is adapted to, at the moment that the input clock signal falls, control, by using a clock signal output by the previous-stage clock signal output terminal, a current path where the first logic unit and the third logic unit are located to be disconnected, or control, by using an inverted clock signal output by the previous-stage inverted clock signal output terminal, a current path where the second logic unit and the fourth logic unit are located to be disconnected.

Optionally, the first control subunit includes a third PMOS transistor and a fourth PMOS transistor; the source end of the third PMOS tube is coupled with the drain end of the first PMOS tube, the gate end of the third PMOS tube is coupled with the clock signal output end, and the drain end of the third PMOS tube is coupled with the second control subunit; the source end of the fourth PMOS tube is coupled with the drain end of the second PMOS tube, the gate end of the fourth PMOS tube is coupled with the inverted clock signal output end, and the drain end of the fourth PMOS tube is coupled with the second control subunit.

Optionally, a source terminal of the third PMOS transistor is coupled to a source terminal of the fourth PMOS transistor.

Optionally, the second control subunit includes a fifth PMOS transistor and a sixth PMOS transistor; a source end of the fifth PMOS transistor is coupled to the first control subunit, a gate end of the fifth PMOS transistor is coupled to the preceding-stage clock signal output end, and a drain end of the fifth PMOS transistor is coupled to the inverted-phase clock signal output end; the source end of the sixth PMOS tube is coupled with the first control subunit, the gate end of the sixth PMOS tube is coupled with the preceding-stage inverted clock signal output end, and the drain end of the sixth PMOS tube is coupled with the clock signal output end.

Optionally, the first control subunit includes a seventh PMOS transistor and an eighth PMOS transistor; a source end of the seventh PMOS transistor is coupled to the reference power supply, a gate end of the seventh PMOS transistor is coupled to the clock signal output end, and a drain end of the seventh PMOS transistor is coupled to a source end of the first PMOS transistor; the source end of the eighth PMOS transistor is coupled to the reference power supply, the gate end of the eighth PMOS transistor is coupled to the inverted clock signal output end, and the drain end of the eighth PMOS transistor is coupled to the source end of the second PMOS transistor.

Optionally, the second control subunit includes a ninth PMOS transistor and a tenth PMOS transistor; a source end of the ninth PMOS transistor is coupled to a drain end of the seventh PMOS transistor, a gate end of the ninth PMOS transistor is coupled to the preceding-stage clock signal output end, and a drain end of the ninth PMOS transistor is coupled to the inverted-phase clock signal output end; the source end of the tenth PMOS transistor is coupled to the drain end of the eighth PMOS transistor, the gate end of the tenth PMOS transistor is coupled to the preceding stage inverted clock signal output end, and the drain end of the tenth PMOS transistor is coupled to the clock signal output end.

Optionally, the first logic unit includes a fifth NMOS transistor, the second logic unit includes a sixth NMOS transistor, the third logic unit includes an eleventh PMOS transistor and a thirteenth PMOS transistor, and the fourth logic unit includes a twelfth PMOS transistor and a fourteenth PMOS transistor; a source end of the fifth NMOS transistor is coupled to the reference ground, a gate end of the fifth NMOS transistor is coupled to an input clock signal, and a drain end of the fifth NMOS transistor is coupled to the control unit; a source end of the sixth NMOS transistor is coupled to the reference ground, a gate end of the sixth NMOS transistor is coupled to the input clock signal, and a drain end of the sixth NMOS transistor is coupled to the control unit; a source end of the eleventh PMOS transistor is coupled to the reference power supply, a gate end of the eleventh PMOS transistor is coupled to the clock signal output end, and a drain end of the eleventh PMOS transistor is coupled to the inverted clock signal output end; a source end of the thirteenth PMOS tube is coupled with the reference power supply, a gate end of the thirteenth PMOS tube is coupled with a preceding-stage clock signal output end, and a drain end of the thirteenth PMOS tube is coupled with an inverted-phase clock signal output end; a source end of the twelfth PMOS tube is coupled with the reference power supply, a gate end of the twelfth PMOS tube is coupled with the inverted clock signal output end, and a drain end of the twelfth PMOS tube is coupled with the clock signal output end; the source end of the fourteenth PMOS tube is coupled with the reference power supply, the gate end of the fourteenth PMOS tube is coupled with the preceding-stage inverted clock signal output end, and the drain end of the fourteenth PMOS tube is coupled with the clock signal output end.

Optionally, the control unit is adapted to control a current path in which the first logic unit and the third logic unit are located or a current path in which the second logic unit and the fourth logic unit are located to be disconnected at an instant when the input clock signal of the latch rises and when the signal at the clock signal output end of the latch and the signal at the inverted clock signal output end of the latch are stable.

Optionally, the control unit comprises a third control subunit and a fourth control subunit; the third control subunit is adapted to control a current path in which the first logic unit and the third logic unit are located, or to control a current path in which the second logic unit and the fourth logic unit are located to be disconnected, when the signal of the clock signal output terminal and the signal of the inverted clock signal output terminal are stable; the fourth control subunit is adapted to control a current path in which the first logic unit and the third logic unit are located, or to control a current path in which the second logic unit and the fourth logic unit are located to be disconnected at an instant when the input clock signal rises.

Optionally, the third control subunit is adapted to, when the signal output by the clock signal output end and the signal output by the inverted clock signal output end are stable, control, by using the signal output by the clock signal output end, the current path where the first logic unit and the third logic unit are located to be disconnected, or control, by using the signal output by the inverted clock signal output end, the current path where the second logic unit and the fourth logic unit are located to be disconnected.

Optionally, the fourth control subunit is adapted to, at the instant when the input clock signal rises, control the current path where the first logic unit and the third logic unit are located to be disconnected by using the clock signal output by the previous-stage clock signal output terminal, or control the current path where the second logic unit and the fourth logic unit are located to be disconnected by using the inverted clock signal output by the previous-stage inverted clock signal output terminal.

Optionally, the third control subunit includes a seventh NMOS transistor and an eighth NMOS transistor; a source end of the seventh NMOS transistor is coupled to a drain end of the fifth NMOS transistor, a gate end of the seventh NMOS transistor is coupled to the clock signal output end, and a drain end of the seventh NMOS transistor is coupled to the fourth control subunit; the source end of the eighth NMOS transistor is coupled to the drain end of the sixth NMOS transistor, the gate end of the eighth NMOS transistor is coupled to the inverted clock signal output end, and the drain end of the eighth NMOS transistor is coupled to the fourth control subunit.

Optionally, a source terminal of the seventh NMOS transistor is coupled to a drain terminal of the eighth NMOS transistor.

Optionally, the fourth control subunit includes a ninth NMOS transistor and a tenth NMOS transistor; a source end of the ninth NMOS transistor is coupled to the third control sub-element, a gate end of the ninth NMOS transistor is coupled to the preceding-stage clock signal output end, and a drain end of the ninth NMOS transistor is coupled to the inverted-phase clock signal output end; the source end of the tenth NMOS transistor is coupled to the third control subunit, the gate end of the tenth NMOS transistor is coupled to the preceding-stage inverted clock signal output end, and the drain end of the tenth NMOS transistor is coupled to the clock signal output end.

Optionally, the third control subunit includes an eleventh NMOS transistor and a twelfth NMOS transistor; a source end of the eleventh NMOS transistor is coupled to the reference ground, a gate end of the eleventh NMOS transistor is coupled to the clock signal output end, and a drain end of the eleventh NMOS transistor is coupled to a source end of the fifth NMOS transistor; the source end of the twelfth NMOS tube is coupled with the reference ground wire, the gate end of the twelfth NMOS tube is coupled with the inverted clock signal output end, and the drain end of the twelfth NMOS tube is coupled with the source end of the sixth NMOS tube.

Optionally, the fourth control subunit includes a thirteenth NMOS transistor and a fourteenth NMOS transistor; a source end of the thirteenth NMOS transistor is coupled to a drain end of the fifth NMOS transistor, a gate end of the thirteenth NMOS transistor is coupled to the preceding-stage clock signal output end, and a drain end of the thirteenth NMOS transistor is coupled to the inverted-phase clock signal output end; the source end of the fourteenth NMOS transistor is coupled to the drain end of the sixth NMOS transistor, the gate end of the fourteenth NMOS transistor is coupled to the preceding-stage inverted clock signal output end, and the drain end of the fourteenth NMOS transistor is coupled to the clock signal output end.

The embodiment of the present invention further provides a frequency divider, which includes two latches as described above, wherein a first input terminal and a second input terminal of any one latch of the two latches are coupled to a clock signal output terminal and an inverted clock signal output terminal of another latch, respectively.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the scheme, when the latch is in the preset working condition, the control unit controls the current path where the first logic unit and the third logic unit in the latch are located or the current path where the second logic unit and the fourth logic unit are located to be disconnected, so that the power consumption of the latch can be reduced under the dynamic and static working conditions, and resources are saved.

Further, at the instant that the input clock signal of the latch with the duty ratio of 25% rises and the output clock signal is stable, the control unit controls the current path where the first logic unit and the third logic unit in the latch are located or the current path where the second logic unit and the fourth logic unit are located to be disconnected, so that the power consumption of the latch can be reduced under the dynamic and static working conditions, and resources are saved.

Further, at the instant that the input clock signal of the latch with the duty ratio of 75% rises and the output clock signal is stable, the control unit controls the current path where the first logic unit and the third logic unit in the latch are located or the current path where the second logic unit and the fourth logic unit are located to be disconnected, so that the power consumption of the latch can be reduced under the dynamic and static working conditions, and resources are saved.

Drawings

FIG. 1 is a schematic diagram of a frequency divider;

FIG. 2 is a schematic diagram of a 25% duty cycle latch in a prior art frequency divider;

FIG. 3 is a schematic diagram of a 25% duty cycle latch according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a control unit in a 25% duty cycle latch according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a latch with a duty cycle of 25% according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a latch with a duty cycle of 25% according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a latch with a duty cycle of 25% according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a 75% duty cycle latch in the frequency divider of FIG. 1;

FIG. 9 is a schematic diagram of a control unit in a latch with 75% duty cycle according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a latch with a duty cycle of 75% according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a latch with a duty cycle of 75% according to an embodiment of the present invention;

fig. 12 is a schematic diagram of a latch with a duty cycle of 75% according to another embodiment of the present invention.

Detailed Description

Referring to fig. 1, a high-speed divide-by-two divider in the prior art may include

latches

101 and 102, wherein the latch 101 and the latch 102 are the subsequent units. The output signal frequency of the high-speed frequency divider is 1/2 of the input signal frequency, and the output of the quadrature frequency division signal with 25% or 75% duty ratio can be realized.

Fig. 2 shows a schematic circuit diagram of a latch in a high-speed frequency divider that implements a frequency divided signal with a duty ratio of 25%. Please refer to fig. 2. The latch includes a first logic cell 201 and a second logic cell 202 coupled between a reference power source VREF _1 and a reference ground line VREF _ 2.

The first logic cell 201 has a first clock signal input terminal CLK1, a previous stage clock signal input terminal D, and an inverted clock signal output terminal Qn, and the second logic cell has a second clock signal input terminal CLK2, a previous stage inverted clock signal input terminal Dn, and a clock signal output terminal Q.

The first logic unit 201 includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a third NMOS transistor MN 3. The second logic unit 202 includes a second PMOS transistor MP2, a second NMOS transistor MN2, and a fourth NMOS transistor MN 4. Wherein:

the source terminals of the first PMOS transistor MP1 and the second PMOS transistor MP2 are coupled to a reference power source VREF _1, the gate terminals of the first PMOS transistor MP1 and the second PMOS transistor MP2 are coupled to a first clock signal input terminal CLK1 and a second clock signal input terminal CLK2, the drain terminal of the first PMOS transistor MP1 is coupled to the drain terminals of the first NMOS transistor MN1 and the third NMOS transistor MN3, and the gate terminal of the inverted clock signal output terminal Qn and the second NMOS transistor MN2, the drain terminal of the second PMOS transistor MP2 is coupled to the drain terminals of the second NMOS transistor MN2 and the fourth NMOS transistor MN4, and the gate terminal of the clock signal output terminal Q and the first NMOS transistor MN1, and the source terminals of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are coupled to a ground line VREF _ 2.

When the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 are both at a low level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, and there is a current path from the reference power source VREF _1 to the inverted clock signal output terminal Qn and the clock signal output terminal Q. When differential signals are input to the previous-stage clock signal output end D and the previous-stage inverted clock signal output end Dn, for example, a high level is input to the previous-stage clock signal output end D, and a low level is input to the previous-stage inverted clock signal output end Dn, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 respectively sense a level difference between the previous-stage clock signal output end D and the previous-stage inverted clock signal output end Dn, and respectively amplify and output the clock signal output end Q and the inverted clock signal output end Qn under the action of the first NMOS transistor MN1 and the second NMOS transistor MN2, so that the level of the clock signal output end Q/the inverted clock signal output end Qn is ensured to be close to the level of the reference power supply VREF _ 1/the reference ground line _2 respectively.

When a high level is inputted to the previous-stage clock signal output terminal D and a low level is inputted to the previous-stage inverted clock signal output terminal Dn, the third NMOS transistor MN3 is turned on, and the fourth NMOS transistor MN4 is turned off, so that the first NMOS transistor MN1 is turned on and the second NMOS transistor MN2 is turned off. At this time, there is a dc path of the reference power source VREF _1 → the first PMOS transistor MP1 → the first NMOS transistor MN 1/the third NMOS transistor MN3 → the reference ground line VREF _2, that is, the latch has dc power consumption.

When the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 are both at a high level, i.e., VREF _3, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned off, the current path from the reference power source VREF _1 to the clock signal output terminal Q and the inverted clock signal output terminal Qn is turned off, and the clock signal output terminal Q and the inverted clock signal output terminal Qn of the latch are discharged through the third NMOS transistor MN3 and the fourth NMOS transistor MN4, respectively, so that the levels of the clock signals output from the clock signal output terminal Q and the inverted clock signal output terminal Qn are close to the level of the ground line VREF _ 2.

Under the dynamic condition, when the clock signal CLK is at a high level, a current path from the reference power source VREF _1 to the ground line VREF _2 also exists in the corresponding latch, so that the dynamic power consumption of the latch is increased.

Therefore, the latch applied to the high-speed frequency-halving device in the prior art has static power consumption and dynamic power consumption under the static working condition and the dynamic working condition respectively, and the application of the high-speed frequency-halving device is severely restricted.

In order to solve the above problems in the prior art, in the technical scheme adopted in the embodiment of the present invention, when the latch is in the static and dynamic conditions, the control unit controls the current path where the first logic unit and the third logic unit in the latch are located or the current path where the second logic unit and the fourth logic unit in the latch are located to be disconnected, so that the power consumption of the latch can be reduced under the dynamic and static operating conditions, and resources are saved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 shows a schematic structural diagram of a latch according to an embodiment of the present invention. The latch 300 shown in fig. 3 includes a first logic unit 301, a second logic unit 302, a third logic unit 303, a fourth logic unit 304 and a control unit 305;

the first logic unit 301 and the second logic unit 302 have the same structure, and the third logic unit 303 and the fourth logic unit 304 have the same structure. The first logic unit 301 and the third logic unit 303 are connected in series between a reference power source VREF _1 and a reference ground line VREF _ 2; the second logic unit 302 and the fourth logic unit 304 are connected in series between the reference power source VREF _1 and the reference ground line VREF _ 2.

The control unit 305 is coupled between the first logic unit 301 and the third logic unit 303, and between the second logic unit 302 and the fourth logic unit 304, and is adapted to control the current path in which the first logic unit 301 and the third logic unit 303 are located or the current path in which the second logic unit 302 and the fourth logic unit 304 are located to be disconnected at the moment when the input clock signal of the latch falls and when the signal at the clock signal output terminal of the latch and the signal at the inverted clock signal output terminal of the latch are stable.

Fig. 4 shows a schematic structural diagram of a control unit in the embodiment of the present invention. The control unit 400, as shown in fig. 4, may comprise at least one of a first control subunit 401 and a second control subunit 402, wherein:

the first control subunit 401 is adapted to control a current path where the first logic unit and the third logic unit are located, or a current path where the second logic unit and the fourth logic unit are located, to be disconnected when the signal at the clock signal output terminal and the signal at the inverted clock signal output terminal are stable. In an embodiment of the present invention, the first control subunit 401 is adapted to, when the signal output by the clock signal output terminal and the signal output by the inverted clock signal output terminal are stable, control the current paths where the first logic unit and the third logic unit are located to be disconnected by using the signal output by the clock signal output terminal, or control the current paths where the second logic unit and the fourth logic unit are located to be disconnected by using the signal output by the inverted clock signal output terminal.

The second control subunit 402 is adapted to control a current path where the first logic unit and the third logic unit are located, or a current path where the second logic unit and the fourth logic unit are located, to be disconnected at a moment when the input clock signal falls. In an embodiment of the present invention, the second control subunit 402 is adapted to, at the moment that the input clock signal falls, control the current path where the first logic unit and the third logic unit are located to be disconnected by using the clock signal output by the previous-stage clock signal output terminal, or control the current path where the second logic unit and the fourth logic unit are located to be disconnected by using the inverted clock signal output by the previous-stage inverted clock signal output terminal.

Fig. 5 shows a schematic diagram of a latch according to an embodiment of the present invention. The latch shown in fig. 5 may include a first logic unit 501, a second logic unit 502, a third logic unit 503, a fourth logic unit 504, and a first control subunit 505 and a second control subunit 504.

In a specific implementation, the first logic unit 301 includes a first PMOS transistor MP1, the second logic unit includes a second PMOS transistor MP2, the third logic unit 303 includes a first NMOS transistor MN1 and a third NMOS transistor MN3, and the fourth logic unit 504 includes a second NMOS transistor MN2 and a fourth NMOS transistor MN 4; the first control subunit comprises a third PMOS transistor MP3 and a fourth PMOS transistor MP 4; the second control subunit includes a fifth PMOS transistor MP5 and a sixth PMOS transistor MP 6.

The gate terminal of the first PMOS transistor MP1 is coupled to the input clock signal CLK, the source terminal of the first PMOS transistor MP1 is coupled to the reference power source VREF _1, and the drain terminal of the first PMOS transistor MP1 is coupled to the source terminal of the third PMOS transistor MP 3.

The gate terminal of the third PMOS transistor MP3 is coupled to the clock signal output terminal Q, and the drain terminal of the third PMOS transistor MP3 is coupled to the source terminal of the fifth PMOS transistor MP 5.

The gate terminal of the fifth PMOS transistor MP5 is coupled to the gate terminal of the third NMOS transistor MN3 and to the preceding clock signal output terminal D, and the drain terminal of the fifth PMOS transistor MP5 is coupled to the drain terminal of the first NMOS transistor MN1 and the drain terminal of the third NMOS transistor MN3 and serves as the inverted clock signal output terminal Qn.

The gate terminal of the first NMOS transistor MN1 is coupled to the clock signal output terminal Q, and the source terminal of the first NMOS transistor MN1 and the source terminal of the third NMOS transistor MN3 are both coupled to the ground reference line VREF _ 2.

The gate terminal of the second PMOS transistor MP2 is coupled to the input clock signal CLK, the source terminal of the second PMOS transistor MP2 is coupled to the reference power source VREF _1, and the drain terminal of the second PMOS transistor MP2 is coupled to the source terminal of the fourth PMOS transistor MP 4.

The gate terminal of the fourth PMOS transistor MP4 is coupled to the inverted clock signal output terminal Qn, and the drain terminal of the fourth PMOS transistor MP4 is coupled to the source terminal of the sixth PMOS transistor MP 6.

The gate terminal of the sixth PMOS transistor MP6 is coupled to the gate terminal of the fourth NMOS transistor MN4 and to the preceding-stage inverted clock signal output terminal Dn, and the drain terminal of the sixth PMOS transistor MP6 is coupled to the drain terminal of the second NMOS transistor MN2 and the drain terminal of the fourth NMOS transistor MN4 and serves as the clock signal output terminal Q.

The gate terminal of the second NMOS transistor MN2 is coupled to the inverted clock signal output terminal Qn, and the source terminals of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are both coupled to the ground reference line VREF _ 2.

The operation of the latch shown in fig. 5 will now be described in detail.

At the moment when the input clock signal at the clock signal input terminal CLK is at a falling edge, i.e., is converted from a high level to a low level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on. Meanwhile, when the previous-stage clock signal output end D is at a low level, the previous-stage inverted clock signal output end Dn is at a high level, and the clock signals output by the inverted clock signal output end Qn and the clock signal output end Q are both at a low level, the fourth NMOS transistor MN4 is turned on. Meanwhile, the sixth PMOS transistor MP6 turns off, so that the current path where the second logic unit and the fourth logic unit are located is disconnected, that is, there is no current path from the second PMOS transistor MP2 → the fourth PMOS transistor MP4 → the sixth PMOS transistor MP6 → the fourth NMOS transistor MN4, and the dynamic power consumption of the latch can be reduced to a great extent.

When the inverted clock signal output by the inverted clock signal output terminal Qn and the clock signal output by the clock signal output terminal Q are stable, the inverted clock signal output by the inverted clock signal output terminal Qn is at a high level, the clock signal output by the clock signal output terminal Q is at a low level, and the clock signals output by the preceding clock signal output terminal D and the preceding inverted clock signal output terminal Dn are both at a low level, the fourth PMOS transistor MP4 is turned off, so that the current path where the second logic unit and the fourth logic unit are located is disconnected, that is, the current path from the second PMOS transistor MP2 → the fourth PMOS transistor MP4 → the sixth PMOS transistor MP6 → the fourth NMOS transistor MN4 does not exist, and the static power consumption of the latch can be reduced to a great extent.

At the moment when the input clock signal at the clock signal input terminal CLK is at a falling edge, i.e., is converted from a high level to a low level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on. Meanwhile, when the previous-stage clock signal output end D is at a high level, the previous-stage inverted clock signal output end Dn is at a low level, and the clock signals output by the inverted clock signal output end Qn and the clock signal output end Q are both at a low level, the third NMOS transistor MN3 is turned on. Meanwhile, the fifth PMOS transistor MP5 is turned off, so that the current path where the first logic unit and the third logic unit are located is disconnected, that is, there is no current path from the first PMOS transistor MP1 → the third PMOS transistor MP3 → the fifth PMOS transistor MP5 → the third NMOS transistor MN3, and the dynamic power consumption of the latch can be greatly reduced.

When the inverted clock signal output by the inverted clock signal output terminal Qn and the clock signal output by the clock signal output terminal Q are stable, the inverted clock signal output by the inverted clock signal output terminal Qn is at a low level, the clock signal output by the clock signal output terminal Q is at a high level, and the clock signals output by the preceding clock signal output terminal D and the preceding inverted clock signal output terminal Dn are both at a high level, the third PMOS transistor MP3 is turned off, so that the current path where the first logic unit and the third logic unit are located is disconnected, that is, the current path from the first PMOS transistor MP2 → the third PMOS transistor MP4 → the fifth PMOS transistor MP6 → the third NMOS transistor MN3 does not exist, and therefore the static power consumption of the latch can be reduced to a great extent.

It can be seen that, through the third and fourth PMOS transistors MP3 and MP4 in the first control subunit and the fifth and sixth PMOS transistors MP5 and MP6 in the second control subunit, the corresponding paths between the reference power source VREF _1 and the reference ground line VREF _2 can be controlled to be disconnected under the static condition and the dynamic condition, respectively, so that the power consumption under the static condition and the dynamic condition can be reduced, respectively.

Fig. 6 shows a schematic diagram of a latch according to an embodiment of the present invention. The latch shown in fig. 6 may include a first logic unit 601, a second logic unit 602, a third logic unit 603, a fourth logic unit 604, and a first control subunit 605 and a second control subunit 606.

The first logic unit 601 includes a first PMOS transistor MP1, the second logic unit includes a second PMOS transistor MP2, the third logic unit 603 includes a first NMOS transistor MN1 and a third NMOS transistor MN3, and the fourth logic unit 604 includes a second NMOS transistor MN2 and a fourth NMOS transistor MN 4; the first control subunit 605 includes a third PMOS transistor MP3 and a fourth PMOS transistor MP 4; the second control subunit 606 includes a fifth PMOS transistor MP5 and a sixth PMOS transistor MP 6.

The gate terminal of the first PMOS transistor MP1 is coupled to the input clock signal CLK, the source terminal of the first PMOS transistor MP1 is coupled to the reference power source VREF _1, and the drain terminal of the first PMOS transistor MP1 is coupled to the source terminal of the third PMOS transistor MP3 and the source terminal of the fourth PMOS transistor MP 4.

The operation of the latch shown in fig. 6 will now be described in detail.

When the inverted clock signal output by the inverted clock signal output terminal Qn and the clock signal output by the clock signal output terminal Q are stable, the inverted clock signal output by the inverted clock signal output terminal Qn is at a low level, the clock signal output by the clock signal output terminal Q is at a high level, and the clock signals output by the preceding clock signal output terminal D and the preceding inverted clock signal output terminal Dn are both at a high level, the third PMOS transistor MP3 is turned off, so that the current path where the first logic unit and the third logic unit are located is disconnected, that is, the current path from the first PMOS transistor MP2 → the third PMOS transistor MP4 → the fifth PMOS transistor MP6 → the third NMOS transistor MN3 does not exist, and the static power consumption of the latch can be reduced to a great extent.

It can be seen that, through the third and fourth PMOS transistors MP3 and MP4 in the first control subunit and the fifth and sixth PMOS transistors MP5 and MP6 in the second control subunit, the corresponding paths between the reference power source VREF _1 and the reference ground line VREF _2 can be controlled to be disconnected under the static condition and the dynamic condition, respectively, and the power consumption under the static condition and the dynamic condition can be reduced, respectively.

Fig. 7 shows a schematic diagram of another latch in an embodiment of the invention. The latch shown in fig. 7 may include a first logic unit 701, a second logic unit 702, a third logic unit 703, a fourth logic unit 704, and a first control subunit 705 and a second control subunit 706.

In a specific implementation, the first logic unit 701 includes a first PMOS transistor MP1, the second logic unit 702 includes a second PMOS transistor MP2, the third logic unit 703 includes a first NMOS transistor MN1 and a third NMOS transistor MN3, and the fourth logic unit 704 includes a second NMOS transistor MN2 and a fourth NMOS transistor MN 4; the first control subunit 705 includes a seventh PMOS transistor MP7 and an eighth PMOS transistor MP 8; the second control subunit 706 includes a ninth PMOS transistor MP9 and a tenth PMOS transistor MP 10.

The gate of the first PMOS transistor MP1 is coupled to the input clock signal CLK, the source of the first PMOS transistor MP1 is coupled to the drain of the seventh PMOS transistor MP7, and the drain of the first PMOS transistor MP1 is coupled to the source of the ninth PMOS transistor MP 9.

The gate terminal of the seventh PMOS transistor MP7 is coupled to the clock signal output terminal Q, and the source terminal of the seventh PMOS transistor MP7 is coupled to the reference power source VREF _ 1;

the gate terminal of the ninth PMOS transistor MP9 is coupled to the previous clock signal output terminal D, and the drain terminal of the ninth PMOS transistor MP9 is coupled to the inverted clock signal output terminal Dn.

The gate terminal of the second PMOS transistor MP2 is coupled to the input clock signal CLK, the source terminal of the second PMOS transistor MP2 is coupled to the drain terminal of the eighth PMOS transistor MP8, and the drain terminal of the second PMOS transistor MP2 is coupled to the source terminal of the tenth PMOS transistor MP 10.

The source terminal of the eighth PMOS transistor MP8 is coupled to the reference power source VREF _1, and the gate terminal of the eighth PMOS transistor MP8 is coupled to the inverted clock signal output Qn.

The gate terminal of the tenth PMOS transistor MP10 is coupled to the previous stage inverted clock signal output terminal Dn, and the drain terminal of the tenth PMOS transistor MP10 is coupled to the clock signal output terminal Q.

The control process of the latch described in fig. 7 for static and dynamic power consumption will be explained in detail below:

at the moment when the input clock signal at the clock signal input terminal CLK is at a falling edge, i.e., is converted from a high level to a low level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on. Meanwhile, when the previous-stage clock signal output end D is at a low level, the previous-stage inverted clock signal output end Dn is at a high level, and the clock signals output by the inverted clock signal output end Qn and the clock signal output end Q are both at a low level, the fourth NMOS transistor MN4 is turned on, and the tenth PMOS transistor MP10 is turned off, so that the current path where the second logic unit and the fourth logic unit are located is disconnected, that is, the current path from the eighth PMOS transistor MP8 → the second PMOS transistor MP2 → the tenth PMOS transistor MP10 → the fourth NMOS transistor MN4 does not exist, and thus the dynamic power consumption of the latch can be reduced to a great extent.

When the inverted clock signal output by the inverted clock signal output terminal Qn and the clock signal output by the clock signal output terminal Q are stable, the inverted clock signal output by the inverted clock signal output terminal Qn is at a high level, the clock signal output by the clock signal output terminal Q is at a low level, and the clock signals output by the preceding clock signal output terminal D and the preceding inverted clock signal output terminal Dn are both at a low level, the eighth PMOS transistor MP8 is turned off, so that the current path where the second logic unit and the fourth logic unit are located is disconnected, that is, the current path from the eighth PMOS transistor MP8 → the second PMOS transistor MP2 → the tenth PMOS transistor MP10 → the fourth NMOS transistor MN4 can reduce the static power consumption of the latch to a great extent.

At the moment when the input clock signal at the clock signal input terminal CLK is at a falling edge, i.e., is converted from a high level to a low level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on. Meanwhile, when the previous-stage clock signal output end D is at a high level, the previous-stage inverted clock signal output end Dn is at a low level, and the clock signals output by the inverted clock signal output end Qn and the clock signal output end Q are both at a low level, the first NMOS transistor MN1 is turned on, and the third NMOS transistor MN3 is turned off, so that the current path where the first logic unit and the third logic unit are located is disconnected, that is, the current path from the seventh PMOS transistor MP7 → the first PMOS transistor MP1 → the ninth PMOS transistor MP9 → the third NMOS transistor MN3 does not exist, and the dynamic power consumption of the latch can be reduced to a great extent.

When the inverted clock signal output by the inverted clock signal output terminal Qn and the clock signal output by the clock signal output terminal Q are stable, the inverted clock signal output by the inverted clock signal output terminal Qn is at a low level, the clock signal output by the clock signal output terminal Q is at a high level, and the clock signals output by the preceding clock signal output terminal D and the preceding inverted clock signal output terminal Dn are both at a high level, the seventh PMOS transistor MP7 is turned off, so that the current path where the first logic unit and the third logic unit are located is disconnected, that is, the current path from the seventh PMOS transistor MP7 → the first PMOS transistor MP1 → the ninth PMOS transistor MP9 → the third NMOS transistor MN3 does not exist, and therefore the static power consumption of the latch can be reduced to a great extent.

It can be seen that, through the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 in the first control subunit and the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 in the second control subunit, the corresponding paths between the reference power source VREF _1 and the reference ground line VREF _2 can be controlled to be disconnected under the static condition and the dynamic condition, respectively, so that the power consumption under the static condition and the dynamic condition can be reduced, respectively.

The structure of the latch with the duty ratio of 25% is described above, and the structure of the latch with the duty ratio of 75% will be described in detail below.

Fig. 8 shows a circuit schematic of a latch with a duty cycle of 75% in the prior art. Referring to fig. 8, the latch includes a first logic unit 801 and a second logic unit 802 coupled between a reference power source VREF _1 and a reference ground line VREF _ 2.

The first logic unit 801 has a first clock signal input terminal CLK1, a previous stage clock signal input terminal D, and an inverted clock signal output terminal Qn, and the second logic unit has a second clock signal input terminal CLK2, a previous stage inverted clock signal input terminal Dn, and a clock signal output terminal Q.

The first logic unit 801 includes a fifth NMOS transistor MN5, an eleventh PMOS transistor MP11, and a thirteenth PMOS transistor MP 13. The second logic unit 802 includes a sixth NMOS transistor MN6, a twelfth PMOS transistor MP12, and a fourteenth PMOS transistor MP14, wherein:

a source terminal of a fifth NMOS transistor MN5 and a source terminal of a sixth NMOS transistor MN6 are coupled to a reference ground line VREF _2, a gate terminal of the fifth NMOS transistor MN5 and a gate terminal of the sixth NMOS transistor MN6 are coupled to a first clock signal input terminal CLK1 and a second clock signal input terminal CLK2, respectively, a drain terminal of the fifth NMOS transistor MN5 is coupled to drain terminals of an eleventh PMOS transistor MP11 and a thirteenth PMOS transistor MP13, respectively, and a gate terminal of an inverted clock signal output terminal Qn and a twelfth PMOS transistor MP12, a drain terminal of the sixth NMOS transistor MN6 is coupled to drain terminals of a twelfth PMOS transistor MP12 and a fourteenth PMOS transistor MP14, respectively, and a gate terminal of a clock signal output terminal Q and an eleventh PMOS transistor MP11, and source terminals of the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP14 are coupled to a reference ground line VREF _ 1.

When the level signals inputted from the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 are both at a high level, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on. At this time, when the level signal inputted from the previous stage clock signal input terminal D is at a low level and the level signal inputted from the previous stage inverted clock signal input terminal Dn is at a high level, the thirteenth PMOS transistor MP13 is turned on, the fourteenth PMOS transistor MP14 is turned off, and the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12 are turned off. At this time, there is a direct current path from the reference power source VREF _1 → the eleventh PMOS transistor MP 11/the thirteenth PMOS transistor MP13 → the fifth MOS transistor MN5 → the reference ground line VREF _2, that is, there is direct current power consumption in the latch.

When the level signals input by the first clock signal input end CLK1 and the second clock signal input end CLK2 are both low level, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned off, and the clock signal output end Q and the inverted clock absorption output end Qn of the latch are charged through the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP14, respectively, so that the clock signal output end Q and the inverted clock signal output end Qn output high level signals close to the reference power source VREF _ 1.

When the latch is in a dynamic condition and the level signals inputted from the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 are changed from a low level to a high level, the latch also has a current path from the reference power source VREF _1 to the reference ground line VREF _2, that is, the dynamic power consumption of the latch is increased.

Therefore, in the prior art, a latch with a duty ratio of 75% applied to a high-speed frequency-halving device has static power consumption and dynamic power consumption under a static working condition and a dynamic working condition respectively, and the application of the high-speed frequency-halving device is severely restricted.

In order to solve the above problems in the prior art, in the technical scheme adopted in the embodiment of the present invention, the current path in which the first logic unit and the third logic unit are located or the current path in which the second logic unit and the fourth logic unit are located is controlled to be disconnected at the instant when the input clock signal of the latch rises and when the signal of the clock signal output end of the latch and the signal of the inverted clock signal output end are stable, so that the power consumption of the latch under the static working condition can be eliminated, and the dynamic power consumption of the latch under the dynamic working condition can be reduced.

With continued reference to fig. 3, an embodiment of the present invention provides a 75% latch 300, which includes a first logic unit 301, a second logic unit 302, a third logic unit 303, a fourth logic unit 304, and a control unit 305.

The control unit 305 is coupled between the first logic unit 301 and the third logic unit 303, and between the second logic unit 302 and the fourth logic unit 304, and is adapted to control the current path of the first logic unit 301 and the third logic unit 303 or the current path of the second logic unit 302 and the fourth logic unit 304 to be disconnected at the instant when the input clock signal of the latch rises and when the signal of the clock signal output terminal and the signal of the inverted clock signal output terminal of the latch are stable.

Fig. 9 is a schematic diagram showing a configuration of a control unit in the embodiment of the present invention. The control unit 900 shown in fig. 9 may comprise at least one of a third control subunit 901 and a fourth control subunit 902, wherein:

the third control subunit 901 is adapted to control the current path where the first logic unit and the third logic unit are located, or the current path where the second logic unit and the fourth logic unit are located to be disconnected when the signal at the clock signal output terminal and the signal at the inverted clock signal output terminal are stable.

In an embodiment of the present invention, the third control subunit 901 is adapted to, when the signal output by the clock signal output terminal and the signal output by the inverted clock signal output terminal are stable, use the signal of the clock signal output terminal to control the current path where the first logic unit and the third logic unit are located to be disconnected, or use the signal of the inverted clock signal output terminal to control the current path where the second logic unit and the fourth logic unit are located to be disconnected.

The fourth control subunit 902 is adapted to control a current path where the first logic unit and the third logic unit are located, or a current path where the second logic unit and the fourth logic unit are located, to be disconnected at a moment when the input clock signal rises.

In an embodiment of the present invention, the fourth control subunit 902 is adapted to, at the instant when the input clock signal rises, control the current path where the first logic unit and the third logic unit are located to be disconnected by using the clock signal output by the previous-stage clock signal output terminal, or control the current path where the second logic unit and the fourth logic unit are located to be disconnected by using the inverted clock signal output by the previous-stage inverted clock signal output terminal.

Fig. 10 shows a schematic diagram of a further latch in an embodiment of the invention. The latch shown in fig. 10 may include a first logic unit 1001, a second logic unit 1002, a third logic unit 1003, a fourth logic unit 1004, and a third control sub-unit 1005 and a fourth control sub-unit 1004.

The first logic unit 1001 comprises a fifth NMOS transistor MN5, the second logic unit 1002 comprises a sixth NMOS transistor MN6, the third logic unit 1003 comprises an eleventh PMOS transistor MP11 and a thirteenth PMOS transistor MP13, and the fourth logic unit 1004 comprises a twelfth PMOS transistor MP12 and a fourteenth PMOS transistor MP 14; the third control subunit 1005 includes a seventh NMOS transistor MN7 and an eighth NMOS transistor MN 8; the fourth control subunit 1006 includes a ninth NMOS transistor MN9 and a tenth NMOS transistor MN 10.

The source terminal of the fifth NMOS transistor MN5 is coupled to the ground reference VREF _2, the gate terminal of the fifth NMOS transistor MN5 is coupled to the clock signal input terminal CLK, and the drain terminal of the fifth NMOS transistor MN5 is coupled to the source terminal of the seventh NMOS transistor MN 7.

The gate terminal of the seventh NMOS transistor MN7 is coupled to the clock signal output terminal Q, and the drain terminal of the seventh NMOS transistor MN7 is coupled to the source terminal of the ninth NMOS transistor MN 9.

The gate terminal of the ninth NMOS transistor MN9 is coupled to the previous-stage clock signal output terminal D, and the drain terminal of the ninth NMOS transistor MN9 is coupled to the inverted-phase clock signal output terminal Qn.

The source terminal of the eleventh PMOS transistor MP11 is coupled to the reference power supply, the gate terminal of the eleventh PMOS transistor MP11 is coupled to the clock signal output terminal Q, and the drain terminal of the eleventh PMOS transistor MP11 is coupled to the inverted clock signal output terminal Qn.

The gate terminal of the thirteenth PMOS transistor MP13 is coupled to the previous stage clock signal output terminal D, the source terminal of the thirteenth PMOS transistor MP13 is coupled to the reference power source VREF _1, and the drain terminal of the thirteenth PMOS transistor MP13 is coupled to the inverted clock signal output terminal Qn.

The source terminal of the sixth NMOS transistor MN6 is coupled to the ground reference VREF _2, the gate terminal of the sixth NMOS transistor MN6 is coupled to the clock signal input terminal CLK, and the drain terminal of the sixth NMOS transistor MN6 is coupled to the source terminal of the fourth NMOS transistor MN 4.

The gate terminal of the eighth NMOS transistor MN8 is coupled to the inverted clock signal output terminal Qn, and the drain terminal of the eighth NMOS transistor MN8 is coupled to the source terminal of the sixth NMOS transistor MN 6.

The gate terminal of the tenth NMOS transistor MN10 is coupled to the preceding-stage inverted clock signal output terminal Dn, and the drain terminal of the tenth NMOS transistor MN10 is coupled to the clock signal output terminal Q.

The source terminal of the twelfth PMOS transistor MP12 is coupled to the reference power source VREF _1, the gate terminal of the twelfth PMOS transistor MP12 is coupled to the inverted clock signal output terminal Qn, and the drain terminal of the twelfth PMOS transistor MP12 is coupled to the clock signal output terminal Q.

The gate terminal of the fourteenth PMOS transistor MP14 is coupled to the preceding stage inverted clock signal output terminal Dn, the source terminal of the fourteenth PMOS transistor MP14 is coupled to the reference power source VREF _1, and the drain terminal of the fourteenth PMOS transistor MP14 is coupled to the clock signal output terminal Q.

The process of how the latch described in fig. 10 controls power consumption under both dynamic and static conditions will now be described.

At the moment that the input clock signal at the clock signal input terminal CLK is at a rising edge, i.e., transitions from a low level to a high level, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on. Meanwhile, when the previous-stage clock signal output end D is at a low level, the previous-stage inverted clock signal output end Dn is at a high level, and the clock signals output by the inverted clock signal output end Qn and the clock signal output end Q are both at a high level, the ninth NMOS transistor MN9 is turned off, so that the current path where the first logic unit and the third logic unit are located is disconnected, that is, the current path from the eleventh PMOS transistor MP 11/the thirteenth PMOS transistor MP13 → the ninth NMOS transistor MN9 → the seventh NMOS transistor MN7 → the fifth NMOS transistor MN5 does not exist, and the dynamic power consumption of the latch can be reduced to a great extent.

When the inverted clock signal output by the inverted clock signal output terminal Qn and the clock signal output by the clock signal output terminal Q are stable, the inverted clock signal output by the inverted clock signal output terminal Qn is at a high level, the clock signal output by the clock signal output terminal Q is at a low level, and the clock signals output by the preceding clock signal output terminal D and the preceding inverted clock signal output terminal Dn are both at a high level, the third NMOS transistor MN3 is turned off, so that the current path where the first logic unit and the third logic unit are located is disconnected, that is, the current path from the eleventh PMOS transistor MP 11/the thirteenth PMOS transistor MP13 → the ninth NMOS transistor MN9 → the seventh NMOS transistor MN7 → the fifth NMOS transistor MN5 does not exist, and thus the static power consumption of the latch can be reduced to a great extent.

At the moment that the input clock signal at the clock signal input terminal CLK is at a rising edge, i.e., transitions from a low level to a high level, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on. Meanwhile, when the previous-stage clock signal output end D is at a high level, the previous-stage inverted clock signal output end Dn is at a low level, and the clock signals output by the inverted clock signal output end Qn and the clock signal output end Q are both at a high level, the tenth NMOS transistor MN10 is turned off, so that the current path where the second logic unit and the fourth logic unit are located is disconnected, that is, there is no current path from the eleventh PMOS transistor MP 11/the twelfth PMOS transistor MP12 → the tenth NMOS transistor MN10 → the eighth NMOS transistor MN8 → the sixth NMOS transistor MN6, and thus the dynamic power consumption of the latch can be reduced to a great extent.

When the inverted clock signal output by the inverted clock signal output terminal Qn and the clock signal output by the clock signal output terminal Q are stable, the inverted clock signal output by the inverted clock signal output terminal Qn is at a low level, the clock signal output by the clock signal output terminal Q is at a high level, and the clock signals output by the preceding clock signal output terminal D and the preceding inverted clock signal output terminal Dn are both at a high level, the eighth NMOS transistor MN8 is turned off, so that the current path where the second logic unit and the fourth logic unit are located is disconnected, that is, the current path from the eleventh PMOS transistor MP 11/the twelfth PMOS transistor MP12 → the tenth NMOS transistor MN10 → the eighth NMOS transistor MN8 → the sixth NMOS transistor MN6 does not exist, and the static power consumption of the latch can be reduced to a great extent.

Therefore, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 in the third control subunit, and the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 in the fourth control subunit can respectively control the corresponding paths between the reference power source VREF _1 and the reference ground line VREF _2 to be disconnected under the static condition and the dynamic condition, so that the power consumption under the static condition and the dynamic condition can be respectively reduced.

Fig. 11 shows a schematic diagram of a further latch in an embodiment of the invention. The latch shown in fig. 11 may include a first logic unit 1101, a second logic unit 1102, a third logic unit 1103, a fourth logic unit 1104, and a third control subunit 1105 and a fourth control subunit 1106.

The first logic unit 1101 comprises a fifth NMOS transistor MN5, the second logic unit 1102 comprises a sixth NMOS transistor MN6, the third logic unit 1103 comprises an eleventh PMOS transistor MP11 and a thirteenth PMOS transistor MP13, and the fourth logic unit 1104 comprises a twelfth PMOS transistor MP12 and a fourteenth PMOS transistor MP 14; the third control subunit 1105 includes a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8 the fourth control subunit 1106 includes a ninth NMOS transistor MN9 and a tenth NMOS transistor MN 10.

The source terminal of the fifth NMOS transistor MN5 is coupled to the ground reference line VREF _2, the gate terminal of the fifth NMOS transistor MN5 is coupled to the clock signal input terminal CLK, and the drain terminal of the fifth NMOS transistor MN5 is coupled to the source terminal of the seventh NMOS transistor MN7 and the source terminal of the eighth NMOS transistor MN 8.

The source terminal of the eleventh PMOS transistor MP11 is coupled to the ground reference VREF _2, the gate terminal of the eleventh PMOS transistor MP11 is coupled to the clock signal output terminal Q, and the drain terminal of the eleventh PMOS transistor MP11 is coupled to the inverted clock signal output terminal Qn.

The source terminal of the sixth NMOS transistor MN6 is coupled to the ground reference VREF _2, the gate terminal of the sixth NMOS transistor MN6 is coupled to the clock signal input terminal CLK, and the drain terminal of the sixth NMOS transistor MN6 is coupled to the source terminal of the eighth NMOS transistor MN 8.

The gate terminal of the eighth NMOS transistor MN8 is coupled to the inverted clock signal output terminal Qn, and the drain terminal of the eighth NMOS transistor MN8 is coupled to the source terminal of the tenth NMOS transistor MN 10.

The latch described in fig. 11 specifically controls the power consumption in the dynamic and static states as follows:

Therefore, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 in the third control subunit 1105, and the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 in the fourth control subunit 1106 can respectively control the corresponding paths between the reference power source VREF _1 and the reference ground line VREF _2 to be disconnected under the static condition and the dynamic condition, so that the power consumption under the static condition and the dynamic condition can be respectively reduced.

Fig. 12 shows a schematic diagram of a further latch in an embodiment of the invention. The latch shown in fig. 12 may include a first logic unit 1201, a second logic unit 1202, a third logic unit 1203, a fourth logic unit 1204, and a third control sub-unit 1205 and a fourth control sub-unit 1206.

The first logic unit 1201 comprises a fifth NMOS transistor MN5, the second logic unit 1202 comprises a sixth NMOS transistor MN6, the third logic unit 1203 comprises an eleventh PMOS transistor MP11 and a thirteenth PMOS transistor MP13, and the fourth logic unit 1204 comprises a twelfth PMOS transistor MP12 and a fourteenth PMOS transistor MP 14; the third control sub-unit 1205 includes an eleventh NMOS transistor MN11 and a twelfth NMOS transistor MN 12; the fourth control subunit 1206 includes a thirteenth NMOS transistor MN13 and a fourteenth NMOS transistor MN 14.

A gate of the fifth NMOS transistor MN5 is coupled to the clock signal input terminal CLK, a source of the fifth NMOS transistor MN5 is coupled to a drain of the eleventh NMOS transistor MN11, and a drain of the fifth NMOS transistor MN5 is coupled to a source of the thirteenth NMOS transistor MN 13.

The gate terminal of the eleventh NMOS transistor MN11 is coupled to the clock signal output terminal Q, and the source terminal of the eleventh NMOS transistor MN11 is coupled to the ground reference VREF _ 2.

The gate terminal of the thirteenth NMOS transistor MN13 is coupled to the previous-stage clock signal output terminal D, and the drain terminal of the thirteenth NMOS transistor MN13 is coupled to the inverted-phase clock signal output terminal Qn.

The gate terminal of the eleventh PMOS transistor MP11 is coupled to the clock signal output terminal Q, the source terminal of the eleventh PMOS transistor MP11 is coupled to the reference power source VREF _1, and the drain terminal of the eleventh PMOS transistor MP11 is coupled to the inverted clock signal output terminal Qn.

A gate terminal of the sixth NMOS transistor MN6 is coupled to the clock signal input terminal CLK, a source terminal of the sixth NMOS transistor MN6 is coupled to a drain terminal of the eighth NMOS transistor MN8, and a drain terminal of the sixth NMOS transistor MN6 is coupled to a source terminal of the fourteenth NMOS transistor MN 14.

The gate terminal of the twelfth NMOS transistor MN12 is coupled to the clock signal output terminal Q, and the source terminal of the twelfth NMOS transistor MN12 is coupled to the ground reference VREF _ 2.

The gate terminal of the fourteenth NMOS transistor MN14 is coupled to the preceding-stage inverted clock signal output terminal Dn, and the drain terminal of the fourteenth NMOS transistor MN14 is coupled to the clock signal output terminal Q.

The gate terminal of the twelfth PMOS transistor MP12 is coupled to the inverted clock signal output terminal Qn, the source terminal of the twelfth PMOS transistor MP12 is coupled to the reference power source VREF _1, and the drain terminal of the twelfth PMOS transistor MP12 is coupled to the clock signal output terminal Q.

In a specific implementation, the dynamic and static power consumption control processes of the latch are as follows:

at the moment that the input clock signal at the clock signal input terminal CLK is at a rising edge, i.e., transitions from a low level to a high level, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on. Meanwhile, when the previous-stage clock signal output end D is at a low level, the previous-stage inverted clock signal output end Dn is at a high level, and the clock signals output by the inverted clock signal output end Qn and the clock signal output end Q are both at a high level, the thirteenth NMOS transistor MN13 is turned off, so that the current path where the first logic unit and the third logic unit are located is disconnected, that is, the current path from the eleventh PMOS transistor MP 11/the thirteenth PMOS transistor MP13 → the thirteenth NMOS transistor MN13 → the fifth NMOS transistor MN5 → the eleventh NMOS transistor MN11 does not exist, and the dynamic power consumption of the latch can be reduced to a great extent.

When the inverted clock signal output by the inverted clock signal output terminal Qn and the clock signal output by the clock signal output terminal Q are stable, the inverted clock signal output by the inverted clock signal output terminal Qn is at a high level, the clock signal output by the clock signal output terminal Q is at a low level, and the clock signals output by the preceding clock signal output terminal D and the preceding inverted clock signal output terminal Dn are both at a high level, the eleventh NMOS transistor MN11 is turned off, so that the current path where the first logic unit and the third logic unit are located is disconnected, and thus the current path from the eleventh PMOS transistor MP 11/thirteenth PMOS transistor MP13 → thirteenth NMOS transistor MN13 → fifth NMOS transistor MN5 → eleventh NMOS transistor MN11 does not exist, so that the static power consumption of the latch can be reduced to a great extent.

At the moment that the input clock signal at the clock signal input terminal CLK is at a rising edge, i.e., transitions from a low level to a high level, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on. Meanwhile, when the previous-stage clock signal output end D is at a high level, the previous-stage inverted clock signal output end Dn is at a low level, and the clock signals output by the inverted clock signal output end Qn and the clock signal output end Q are both at a high level, the fourteenth NMOS transistor MN14 is turned off, so that the current path where the second logic unit and the fourth logic unit are located is disconnected, that is, there is no current path from the twelfth PMOS transistor MP 12/the fourteenth PMOS transistor MP14 → the fourteenth NMOS transistor MN14 → the sixth NMOS transistor MN6 → the twelfth NMOS transistor MN12, and thus the dynamic power consumption of the latch can be reduced to a great extent.

When the inverted clock signal output by the inverted clock signal output terminal Qn and the clock signal output by the clock signal output terminal Q are stable, the inverted clock signal output by the inverted clock signal output terminal Qn is at a low level, the clock signal output by the clock signal output terminal Q is at a high level, and the clock signals output by the preceding clock signal output terminal D and the preceding inverted clock signal output terminal Dn are both at a high level, the twelfth NMOS transistor MN12 is turned off, so that the current path where the second logic unit and the fourth logic unit are located is disconnected, that is, the current path from the twelfth PMOS transistor MP 12/the fourteenth PMOS transistor MP14 → the fourteenth NMOS transistor MN14 → the sixth NMOS transistor MN6 → the twelfth NMOS transistor MN12 does not exist, and the static power consumption of the latch can be reduced to a great extent.

Therefore, by the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 in the third control subunit, and the fourth control subunit including the thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14, the corresponding paths between the reference power source VREF _1 and the reference ground line VREF _2 can be controlled to be disconnected under the static condition and the dynamic condition, respectively, so that the power consumption under the static condition and the dynamic condition can be reduced, respectively.

The embodiment of the invention also provides a frequency divider, which comprises at least two latches. The latch structure may adopt the scheme described in the above embodiments, and details are not described again.

The embodiments of the present invention have been described in detail, but the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A latch is characterized by comprising a first logic unit, a second logic unit, a third logic unit, a fourth logic unit and a control unit;

the first logic unit and the second logic unit have the same structure, the third logic unit and the fourth logic unit have the same structure, the first logic unit and the third logic unit are connected between a reference power supply and a reference ground wire in series, and the second logic unit and the fourth logic unit are connected between the reference power supply and the reference ground wire in series;

the control unit is suitable for controlling the current path where the first logic unit and the third logic unit are located or the current path where the second logic unit and the fourth logic unit are located to be disconnected when the latch is in a preset working condition;

the control unit is suitable for controlling a current path where the first logic unit and the third logic unit are located or a current path where the second logic unit and the fourth logic unit are located to be disconnected at the moment that an input clock signal of the latch is lowered and when a signal of a clock signal output end of the latch and a signal of an inverted clock signal output end of the latch are stable.

2. The latch of claim 1, wherein the first logic cell comprises a first PMOS transistor; the second logic unit comprises a second PMOS tube; the third logic unit comprises a first NMOS transistor and a third NMOS transistor; the fourth logic unit comprises a second NMOS transistor and a fourth NMOS transistor;

the grid end of the first PMOS tube is coupled with the clock signal input end, and the drain end of the first PMOS tube is coupled with the control unit;

the gate end of the second PMOS tube is coupled with the input clock signal, and the drain end of the second PMOS tube is coupled with the control unit;

the drain terminal of the first NMOS tube is coupled with the inverted clock signal output terminal, the gate terminal of the first NMOS tube is coupled with the clock signal output terminal, and the source terminal of the first NMOS tube is coupled with the reference ground wire;

the drain terminal of the third NMOS tube is coupled with the inverted clock signal output terminal, the gate terminal of the third NMOS tube is coupled with the preceding-stage clock signal output terminal, and the source terminal of the third NMOS tube is coupled with the reference ground wire;

the drain terminal of the second NMOS transistor is coupled to the clock signal output terminal, the gate terminal of the second NMOS transistor is coupled to the inverted clock signal output terminal, and the source terminal of the second NMOS transistor is coupled to the reference ground;

the drain terminal of the fourth NMOS tube is coupled with the clock signal output terminal, the gate terminal of the fourth NMOS tube is coupled with the preceding-stage reverse-phase clock signal output terminal, and the source terminal of the fourth NMOS tube is coupled with the reference ground wire.

3. The latch of claim 2, wherein the control unit comprises a first control subunit and a second control subunit;

the first control subunit is adapted to control a current path in which the first logic unit and the third logic unit are located, or to control a current path in which the second logic unit and the fourth logic unit are located to be disconnected, when the signal of the clock signal output end and the signal of the inverted clock signal output end are stable;

the second control subunit is adapted to control a current path in which the first logic unit and the third logic unit are located, or to control a current path in which the second logic unit and the fourth logic unit are located to be disconnected at the moment when the input clock signal falls.

4. The latch according to claim 3, wherein the first control subunit is adapted to control the current paths of the first logic unit and the third logic unit to be disconnected using the signal from the clock signal output terminal, or control the current paths of the second logic unit and the fourth logic unit to be disconnected using the signal from the inverted clock signal output terminal, when the signal from the clock signal output terminal and the signal from the inverted clock signal output terminal are stable.

5. The latch according to claim 4, wherein the second control subunit is adapted to control the current path of the first logic unit to be disconnected from the current path of the third logic unit by using the clock signal output from the previous clock signal output terminal, or control the current path of the second logic unit to be disconnected from the current path of the fourth logic unit by using the inverted clock signal output from the previous inverted clock signal output terminal, at the moment the input clock signal falls.

6. The latch of claim 5, wherein the first control subunit comprises a third PMOS transistor and a fourth PMOS transistor;

the source end of the third PMOS tube is coupled with the drain end of the first PMOS tube, the gate end of the third PMOS tube is coupled with the clock signal output end, and the drain end of the third PMOS tube is coupled with the second control subunit;

the source end of the fourth PMOS tube is coupled with the drain end of the second PMOS tube, the gate end of the fourth PMOS tube is coupled with the inverted clock signal output end, and the drain end of the fourth PMOS tube is coupled with the second control subunit.

7. The latch of claim 6 wherein a source terminal of the third PMOS transistor is coupled to a source terminal of the fourth PMOS transistor.

8. The latch according to claim 6 or 7, wherein the second control subunit comprises a fifth PMOS tube and a sixth PMOS tube;

a source end of the fifth PMOS transistor is coupled to the first control subunit, a gate end of the fifth PMOS transistor is coupled to the preceding-stage clock signal output end, and a drain end of the fifth PMOS transistor is coupled to the inverted-phase clock signal output end;

the source end of the sixth PMOS tube is coupled with the first control subunit, the gate end of the sixth PMOS tube is coupled with the preceding-stage inverted clock signal output end, and the drain end of the sixth PMOS tube is coupled with the clock signal output end.

9. The latch of claim 5, wherein the first control subunit comprises a seventh PMOS transistor and an eighth PMOS transistor;

a source end of the seventh PMOS transistor is coupled to the reference power supply, a gate end of the seventh PMOS transistor is coupled to the clock signal output end, and a drain end of the seventh PMOS transistor is coupled to a source end of the first PMOS transistor;

the source end of the eighth PMOS transistor is coupled to the reference power supply, the gate end of the eighth PMOS transistor is coupled to the inverted clock signal output end, and the drain end of the eighth PMOS transistor is coupled to the source end of the second PMOS transistor.

10. The latch of claim 9 wherein the second control subunit includes a ninth PMOS transistor and a tenth PMOS transistor;

the source end of the ninth PMOS tube is coupled with the drain end of the first PMOS tube, the gate end of the ninth PMOS tube is coupled with the preceding-stage clock signal output end, and the drain end of the ninth PMOS tube is coupled with the inverted-phase clock signal output end;

the source end of the tenth PMOS transistor is coupled to the drain end of the second PMOS transistor, the gate end of the tenth PMOS transistor is coupled to the preceding stage inverted clock signal output end, and the drain end of the tenth PMOS transistor is coupled to the clock signal output end.

11. A frequency divider comprising at least two latches as claimed in any one of claims 1 to 10; and the first input end and the second input end of any latch in the two latches are respectively coupled with the clock signal output end and the inverted clock signal output end of the other latch.