JP2006203479A - Flip flop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip flop circuit which stably operates irrespective of a condition of manufacture and a temperature and of operation speed, especially the flip lop circuit which suitably operates from a high speed operation to a low speed operation. <P>SOLUTION: A 9 transistor D flip flop circuit which uses a dynamic circuit for high speed use and which is constituted of an input part 1, a transfer part 2 and an output part 3, is added with a control part 4 for stabilizing potentials of an output (node n1) of the input part 1 where a holding state of potential by parasitic capacity occurs, an output (node n2) of the transfer part 2 and an inverse output signal XQ of the output part 3 by using an input signal D, a clock signal CK and the inverse output signal XQ of the output part 3. In such constitution, the potential holding state with parasitic capacity is eliminated, and malfunction due to deterioration of the manufacture condition, the temperature and operation speed is prevented, thereby realizing the flip flop circuit enabling the stable operation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a flip-flop circuit, and more particularly to a flip-flop circuit that operates at high speed.

  In recent years, some logic circuits in a semiconductor integrated circuit are required to operate at a high speed such as a high data transfer speed. Further, in order to reduce power consumption in portable devices and the like, it is common to use high speed operation and low speed operation separately, and it is required to operate stably at high speed and low speed.

Conventionally, a 9-transistor D flip-flop circuit using a dynamic circuit has been used for high speed and high speed operation applications as described in Non-Patent Document 1.
A 9-transistor D flip-flop circuit using a conventional dynamic circuit will be described below.

FIG. 8 shows a 9-transistor D flip-flop circuit using a dynamic circuit.
In FIG. 8, D is an input terminal, CK is a clock terminal, and XQ is an inverted output terminal. MP1, MP2, MP3 and MP4 are PMOS transistors, and MN1, MN2, MN3, MN4 and MN5 are NMOS transistors. N1 and n2 are nodes.

  The first PMOS transistor MP1, the second PMOS transistor MP2, and the first NMOS transistor MN1 are connected in series. The source of the PMOS transistor MP1 is a power source, and the source of the NMOS transistor MN1 is a ground. Are connected to each other to constitute the input unit 1.

  In addition, the third PMOS transistor MP3, the second NMOS transistor MN2, and the third NMOS transistor MN3 are connected in series. The source of the PMOS transistor MP3 is a power source, and the source of the NMOS transistor MN3 is Are connected to the ground to constitute the transfer unit 2.

  The fourth PMOS transistor MP4, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 are connected in series. The source of the PMOS transistor MP4 is a power source, and the source of the NMOS transistor MN5 is Are connected to the ground to constitute the output unit 3.

  The gates of the two PMOS transistors MP2 and MP3 and the two NMOS transistors MN2 and MN4 are connected to a clock signal (hereinafter referred to as a clock signal CK) of a clock terminal CK.

The gates of the PMOS transistor MP1 and the NMOS transistor MN1 are connected to an input signal at the input terminal D (hereinafter referred to as input signal D).
The node n1 (output of the input unit 1) is a connection point between the PMOS transistor MP2 and the NMOS transistor MN1, and connects the gate of the NMOS transistor MN3.

  The node n2 (output of the transfer unit 2) is a connection point between the PMOS transistor MP3 and the NMOS transistor MN2, and connects the PMOS transistor MP4 and the gate of the NMOS transistor MN5.

The connection point between the PMOS transistor MP4 and the NMOS transistor MN4 is connected to the inverting output terminal XQ.
Operations of the input signal D, the clock signal CK, the node n1, the node n2, and the inverted output terminal XQ will be described (see the time chart in FIG. 9).

When the clock signal CK is at a low level, the input unit operates as an inverter, and the node n1 has a phase opposite to that of the input signal D.
[State 1]
When the clock signal CK changes from a low level to a high level, if the input signal D is at a low level, the node n1 is in a high impedance state while maintaining the high level. The NMOS transistor MN3 of the transfer unit 2 is turned on, the NMOS transistor MN2 is also turned on, the PMOS transistor MP3 is turned off, and the node n2 is at a low level.

When the clock signal CK is at a high level, the output unit 3 operates as an inverter, so that the inverted output terminal XQ becomes a high-level output with the opposite phase of the node n2, and the opposite phase of the input signal D. It becomes.
[State 2]
Next, when only the clock signal CK changes from a high level to a low level, the PMOS transistor MP3 of the transfer unit 2 is turned on and the NMOS transistor MN2 is turned off. The PMOS transistor MP4 of the output section 3 is turned off, the NMOS transistor MN5 is turned on, and the NMOS transistor MN4 is turned off, so that the inverting output terminal XQ remains at a high level. It becomes a high impedance state.
[State 3]
Similarly, the node n2 is at a high level when the clock signal CK is at a low level, and the node n1 is at a low level when the input signal D is at a high level.
[State 4]
When the clock signal CK changes from a low level to a high level, the node n1 remains at a low level, the NMOS transistor MN3 of the transfer unit 2 is in an off state, and the PMOS transistor MP3 is in an off state. Since the NMOS transistor MN2 is in an on state, the node n2 is in a high impedance state while maintaining a high level, so that the PMOS transistor MP4 of the output unit 3 is in an off state and the NMOS transistor MN5 is in an on state. Since the NMOS transistor MN4 is turned on, the inverting output terminal XQ becomes a low level output and is in a phase opposite to the input signal D.
[State 5]
When the clock signal CK is at a high level, the node n1 remains at a low level even if the input signal D is at a low level.
[State 6]
Next, when only the clock signal CK changes from a high level to a low level, the PMOS transistor MP3 of the transfer unit 2 is turned on, and the NMOS transistor MN2 is turned off. The PMOS transistor MP4 is turned off, the NMOS transistor MN5 of the output unit 3 is turned on, and the NMOS transistor MN4 is turned off, so that the inverted output terminal XQ is kept at a low level. It becomes a high impedance state.

The hatched portion shown in the time chart of FIG. 9 is a high impedance state portion of the three nodes n1, n2, and XQ, and is a period in which a potential is held by parasitic capacitance.
Moreover, there exists a thing of patent document 1 as a similar technique.
JP-A-6-152336 Design of a 3-V 300-MHz low-power 8-b × 8-b pipelined multiplier using pulse-triggered TSPC flip-flops ： Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng IEEE Journal Solid-State Circuits (Apr 2000) / 583-592, Volume: 35, Issue: 4

However, the 9-transistor D flip-flop circuit using the conventional dynamic circuit has the following drawbacks.
In the 9-transistor D flip-flop circuit using the conventional dynamic circuit shown in FIG. 8, when the clock signal CK is at a low level, the input section operates as an inverter, and the node n1 has a phase opposite to that of the input signal D. It becomes.

  When the clock signal CK changes from the low level to the high level, if the input signal D is at the low level, the node n1 is in the high impedance state while maintaining the high level. The potential of the node n1 is held by a parasitic capacitance existing between the gate and source of the NMOS transistor MN3 of the transfer unit 2.

For this reason, when off-leakage occurs in the NMOS transistor MN1, the potential of the node n1 changes from a high level to a low level, which may cause a malfunction.
Further, even when a gate leak occurs between the NMOS transistor MN3 of the transfer unit 2 and the ground, the potential of the node n1 may change from a high level to a low level and malfunction.

The leak value varies depending on the manufacturing conditions and temperature, and the possibility of malfunctioning increases as the operation speed decreases.
Similarly, there is a potential holding state due to parasitic capacitance at the node n2 and the inverted output terminal XQ, and there is a possibility that the potential transitions and malfunctions due to transistor off-leakage, gate leak, and operation speed reduction.

  Therefore, the present invention has an object to provide a flip-flop circuit that operates stably regardless of manufacturing, temperature conditions, and operation speed, particularly a flip-flop circuit that operates appropriately from high speed operation to low speed operation. It is.

  In order to solve the above problems, in the present invention, in the operation of a conventional flip-flop circuit, a circuit for stabilizing the potential of a node where a potential holding state due to a parasitic capacitance occurs is added, thereby stabilizing the flip-flop. Enable circuit operation.

That is, in the flip-flop circuit of the invention according to claim 1, the input terminal, the clock terminal, the output terminal, the input signal input to the input terminal and the clock signal input to the clock terminal are input. An input unit composed of 3 MOS transistors, the clock signal and the output signal of the input unit are input, a transfer unit composed of 3 MOS transistors, the clock signal and the output signal of the transfer unit are input, and a signal is output from the output terminal. A delay flip-flop circuit including an output unit composed of a 3MOS transistor for outputting,
A first control output unit connected to the output of the input unit; a second control output unit connected to the output of the transfer unit; and a third control output unit connected to the output of the output unit; Providing a control unit to which the input signal, the clock signal, and the output signal of the output unit are input;
When the clock signal is low level and the output signal of the output unit is low level, the output of the first control output unit is high impedance and the second control output unit is high The third control output unit outputs a low level, and when the clock signal is low level and the output signal of the output unit is high level, the output of the first control output unit is The output of the second control output unit becomes high impedance, the third control output unit outputs a high level, the input signal is low level, and the clock signal is high level. When the output signal of the output unit is low level, the first control output unit outputs low level, the second control output unit outputs high level, and the output of the third control output unit When the input signal is high level, the clock signal is high level, and the output signal of the output unit is low level, the output of the first control output unit is high impedance. The second control output unit outputs a high level, the output of the third control output unit is a high impedance, the input signal is low level, the clock signal is high level, and the output unit When the output signal of the second control output unit is high level, the first control output unit outputs high level, the output of the second control output unit becomes high impedance, and the output of the third control output unit is high impedance. When the input signal is high level, the clock signal is high level, and the output signal of the output unit is high level, the first control output The output of becomes a high impedance, the second control output unit outputs a low-level, the output of the third control output is characterized in that the structure where the high impedance.

  According to the above configuration, when the output of the input unit, the output of the transfer unit, and the output of the output unit are in a state of holding a potential due to parasitic capacitance in the operation state of the flip-flop circuit, the control unit The output of the first control output unit, the output of the second control output unit, and the output of the third control output unit are set to a high level, a low level, and a high impedance state, respectively. It is possible to realize a flip-flop operation that is stable even with fluctuations in temperature and temperature conditions, and with low-speed operation.

  A flip-flop circuit according to a second aspect of the present invention is the flip-flop circuit according to the first aspect, wherein a first resistor is provided between the output of the input unit and the first control output unit of the control unit. A second resistive element between the element and the output of the transfer unit and the second control output unit of the control unit; and between the output of the output unit and the third control output unit of the control unit. A third resistance element is provided.

  According to the above configuration, between the output of the input unit and the output of the first control output unit of the control unit, between the output of the transfer unit and the output of the second control output unit of the control unit, And an output of the first control output unit of the control unit and an output of the second control output unit of the control unit by providing a resistance element between the output of the output unit and the output of the third control output unit of the control unit. The output and the output capability of the third control output unit can be attenuated, the signal transmission rate from the input unit to the transfer unit, the signal transmission rate from the transfer unit to the output unit, and the It is possible to suppress a decrease in signal transmission speed from the output unit to the next stage circuit outside the circuit of the present invention.

  The flip-flop circuit of the invention according to claim 3 is an input terminal, a clock terminal, an output terminal, an input signal input to the input terminal and a clock signal input to the clock terminal. An input unit composed of 3 MOS transistors, the clock signal and the output signal of the input unit are input, a transfer unit composed of 3 MOS transistors, the clock signal and the output signal of the transfer unit are input, and a signal is output from the output terminal. A delay flip-flop circuit including an output unit composed of a 3MOS transistor, and having a first capacitive element between the output of the input unit and a reference fixed potential, and the output of the transfer unit and the output A second capacitive element between a reference fixed potential and a third capacitive element between the output of the output section and the reference fixed potential; It is characterized in that it has.

  According to the above configuration, when the output of the input unit, the output of the transfer unit, and the output of the output unit are in the operating state of the flip-flop circuit, the conventional circuit is in a potential holding state due to parasitic capacitance. Even if transistor off-leakage or gate leakage occurs due to the first capacitor element, the second capacitor element, and the third capacitor element, the potential holding time is longer than that of the conventional circuit, and the stable flip-flop Can be realized.

  A flip-flop circuit according to a fourth aspect of the present invention is the flip-flop circuit according to the third aspect, wherein a control terminal, a first switch unit to which a signal input to the control terminal is input, A second switch unit that receives a signal input to the control terminal; and a third switch unit that receives a signal input to the control terminal. The output of the input unit and the first capacitor The first switch unit is provided between the output unit, the second switch unit is provided between the output of the transfer unit and the second capacitor element, and the output of the output unit and the third capacitor are provided. The third switch unit is provided between the device and the element.

  According to the above configuration, when the three first switch units, the second switch unit, and the third switch unit are turned on by the signal input to the control terminal, the first capacitive element is Connected to the output of the input unit, the second capacitive element is connected to the output of the transfer unit, the third capacitive element is connected to the output of the output unit, the output of the input unit, the transfer unit And the output of the output unit when the output state of the flip-flop circuit is in a state of holding a potential due to a parasitic capacitance in the operation state of the flip-flop circuit, the first capacitor element and the second capacitor element And the third capacitor element can increase the potential holding time, and can realize a more stable flip-flop operation than the conventional circuit. The signal input to the control terminal allows the three first switches. The first capacitor element is disconnected from the output of the input unit, and the second capacitor element is disconnected from the output of the transfer unit. The third capacitive element is disconnected from the output of the output unit, and the output of the input unit, the output of the transfer unit, and the output of the output unit are equivalent to the conventional circuit in the operating state of the flip-flop circuit. Flip-flop operation can be realized. Depending on the frequency, use conditions, etc., it can be switched and used properly by input to the control terminal.

  A flip-flop circuit according to a fifth aspect of the present invention is the flip-flop circuit according to the third aspect, wherein the flip-flop circuit is input to the first control terminal, the second control terminal, and the first control terminal. A first switch unit to which a signal is input; a second switch unit to which a signal to be input to the first control terminal is input; and a signal to be input to the first control terminal. A third switch unit, a fourth switch unit to which a signal input to the second control terminal is input, a fifth switch unit to which a signal input to the second control terminal is input, A sixth switch unit to which a signal input to the second control terminal is input; a first capacitor; a second capacitor; a third capacitor; a fourth capacitor; A fifth capacitive element; a sixth capacitive element; and the output of the input unit and the first capacitive element. The first switch unit between the capacitive element and the second switch unit between the output of the transfer unit and the second capacitive element, the output of the output unit and the third capacitive element The fourth switch unit and the fourth capacitor are provided between the connection point between the first capacitor element and the first switch unit, and a fixed potential as a reference. An element is connected in series, and the fifth switch section and the fifth capacitor element are connected between a connection point between the second capacitor element and the second switch section and the reference fixed potential. Are connected in series, and the sixth switch unit and the sixth capacitive element are connected in series between the connection point of the third capacitive element and the third switch unit and the fixed potential serving as the reference. It is characterized by connecting to.

  According to the above configuration, in addition to the three first switch units, the second switch unit, and the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit are turned on. By switching between the state and the off state, the switching effect of the invention of claim 4 can be controlled in two stages.

  A flip-flop circuit according to a sixth aspect of the present invention is the flip-flop circuit according to any one of the first to fifth aspects, wherein the input section is connected to a first PMOS transistor and a second PMOS transistor. A PMOS transistor and a first NMOS transistor are connected in series between a power supply potential and a ground potential, the input signal is input to the gates of the first PMOS transistor and the first NMOS transistor, and the second The clock signal is input to the gate of the PMOS transistor, and an output signal is output from a connection point between the second PMOS transistor and the first NMOS transistor, and the transfer unit is connected to the third PMOS transistor. A second NMOS transistor and a third NMOS transistor are connected in series between the power supply potential and the ground potential. Subsequently, the clock signal is input to the gates of the third PMOS transistor and the second NMOS transistor, the output signal of the input unit is input to the gate of the third NMOS transistor, and the third An output signal is output from a connection point between the PMOS transistor and the second NMOS transistor, and the output section includes the fourth PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor as the power supply potential. And the ground potential, the output signal of the transfer unit is input to the gates of the fourth PMOS transistor and the fifth NMOS transistor, and the clock signal is input to the gate of the fourth NMOS transistor. Between the fourth PMOS transistor and the fourth NMOS transistor. It is characterized in that a configuration in which a signal outputted from the connection point and the output terminal.

  The flip-flop circuit of the present invention has an effect that it operates stably regardless of manufacturing, temperature conditions, and operating speed by providing a control or switch unit in a 9-transistor D flip-flop circuit using a conventional dynamic circuit. have.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the structure same as the structure of the conventional FIG. 8, and the description is abbreviate | omitted.
In the present invention, the potential of the output of the input unit 1 (node n1), the output of the transfer unit 2 (node n2), and the inverted output signal XQ of the output unit 3 in which a potential holding state due to parasitic capacitance occurs is stabilized. Yes.
[Embodiment 1]
FIG. 1 shows a circuit diagram of a flip-flop circuit according to Embodiment 1 of the present invention.

  As shown in FIG. 1, a control unit 4 is newly provided. In FIG. 1, MP5, MP6, MP7, MP8, MP9, MP10 are PMOS transistors, MN6, MN7, MN8, MN9, MN10, MN11, MN12, MN13 are NMOS transistors, INV1, INV2, INV3, INV4 are inverters Represents.

The configuration of the control unit 4 will be described.
In order, the three PMOS transistors MP5, MP6, and MP7, and the three NMOS transistors MN7, MN6, and MN10 are connected in series, the source of the PMOS transistor MP5 is a power source, and the NMOS transistor MN10 The sources are respectively connected to the ground, and the first control output unit 21 is configured.

  Further, the PMOS transistor MP10 and the three NMOS transistors MN11, MN12, and MN13 are connected in series, and the source of the PMOS transistor MP10 is connected to the power source, and the source of the NMOS transistor MN13 is connected to the ground. The second control output unit 22 is configured.

  Further, two PMOS transistors MP8 and MP9 and two NMOS transistors MN9 and MN8 are connected in series, and the source of the PMOS transistor MP8 is a power source and the source of the NMOS transistor MN8 is a ground. The third control output unit 23 is configured.

  The input of the inverter INV1 is connected to the clock signal CK, and the output of the inverter INV1 is connected to the gate of the PMOS transistor MP6, the gate of the NMOS transistor MN8, and the input of the inverter INV2.

The output of the inverter INV2 is connected to the gate of the PMOS transistor MP8 and the gates of the two NMOS transistors MN13 and MN6.
The input of the inverter INV3 is connected to the inverted output signal of the output terminal XQ (hereinafter referred to as inverted output signal XQ) and the gates of the two PMOS transistors MP10 and MP11. The output of the inverter INV3 is 2 The gates of the PMOS transistors MP9 and MP7 are connected to the gates of the two NMOS transistors MN9 and MN7.

  The input of the inverter INV4 is connected to the input signal of the input terminal D (hereinafter referred to as input signal D), the gate of the PMOS transistor MP5, and the gate of the NMOS transistor MN12. The output of the inverter INV4 is Connected to the NMOS transistor MN10.

  The connection point between the PMOS transistor MP9 and the NMOS transistor MN9 is connected to the inverted output signal XQ. A connection point between the PMOS transistor MP10 and the NMOS transistor MN11 is connected to the node n2. The connection point between the PMOS transistor MP7 and the NMOS transistor MN7 is connected to the node n1.

By the circuit configuration of the control unit 4,
a. When the clock signal CK is low level and the output signal of the output unit 3 is low level, the output of the first control output unit 21 is high impedance, the second control output unit 22 outputs high level, The third control output unit 23 outputs a low level,
b. When the clock signal CK is low level and the output signal of the output unit 3 is high level, the output of the first control output unit 21 becomes high impedance, the output of the second control output unit 22 becomes high impedance, The third control output unit 23 outputs a high level,
c. When the input signal D is low level, the clock signal CK is high level, and the output signal of the output unit 3 is low level, the first control output unit 21 outputs low level, and the second control output unit 22 outputs a high level, the output of the third control output unit 23 becomes a high impedance,
d. When the input signal D is high level, the clock signal CK is high level, and the output signal of the output unit 3 is low level, the output of the first control output unit 21 becomes high impedance, and the second control output unit 22 outputs a high level, the output of the third control output unit 23 becomes a high impedance,
e. When the input signal D is low level, the clock signal CK is high level, and the output signal of the output unit 3 is high level, the first control output unit 21 outputs high level, and the second control output unit The output of 22 is high impedance, the output of the third control output unit 23 is high impedance,
f. When the input signal D is high level, the clock signal CK is high level, and the output signal of the output unit 3 is high level, the output of the first control output unit 21 becomes high impedance, and the second control output unit 22 outputs a low level, and the output of the third control output unit 23 has a high impedance.

  FIG. 2 is a diagram in which the control unit 4 is extracted from FIG. 1 and node names of connection portions with the conventional circuit of FIG. 8 are added for easy understanding of the operation, and IND, INCK, OUTn1, OUTn2, OUTXQ, INXQ is a node.

  FIG. 3 is a truth table of the operation of the control unit 4 when the three nodes IND, INCK, and INXQ are input and the three nodes OUTn1, OUTn2, and OUTXQ are outputs. The three nodes IND , INCK, INXQ indicate that the three nodes OUTn1, OUTn2, OUTXQ are in a high level output H, a low level output L, or a high impedance state Z, respectively.

Here, the conventional circuit shown in FIG. 8 will be described in comparison with the present embodiment.
When the node n1 in the conventional example shown in the time chart of the conventional example shown in FIG. 9 is in a high impedance state, for example, the clock signal CK is at a high level and the input signal D is at a low level. When the level and the inverted output signal XQ are at a high level, the node n1 is in a high impedance state.

  On the other hand, in the circuit of FIG. 1 of the first embodiment, the node n1 of the control unit 4 is the same node as the node OUTn1, the clock signal CK is high level, and the input signal D is low level. When the inverted output signal XQ is at a high level, the three PMOS transistors MP5, MP6, and MP7 are turned on and the NMOS transistor MN7 is turned off, so that the node OUTn1 is High level as shown in the truth table.

  Further, when the node n2 which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9 is in a high impedance state, for example, the clock signal CK is at a high level, and the inverted output signal XQ When is low, the node n2 is in a high impedance state.

  On the other hand, in the circuit of FIG. 1 of the first embodiment, the node n2 of the control unit 4 is the same node as the node OUTn2, the clock signal CK is at a high level, and the inverted output signal XQ When is low, the PMOS transistor MP10 is turned on and the NMOS transistor MN11 is turned off, so that the node OUTn2 is at a high level as shown in the truth table of FIG.

  When the node XQ, which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9, is in a high impedance state, for example, the clock signal CK is at a low level, and the inverted output signal When XQ is at a high level, the inverted output signal XQ is in a high impedance state.

  On the other hand, in the circuit of FIG. 1 of the first embodiment, the inverted output signal XQ of the output unit 4 is the same node as the node OUTXQ, the clock signal CK is at a low level, and the inverted output When the signal XQ is at a high level, the PMOS transistors MP8 and MP9 are turned on and the NMOS transistor MN9 is turned off, so that the node OUTXQ has a high level as shown in the truth table of FIG. It is.

As described above, according to the first embodiment, the control unit 4 in FIG. 1 is added, the output of the first control output unit 21, the output of the second control output unit 22, and the third control output unit 23. By setting the output of each to the high level, low level, and high impedance states, it is possible to operate without generating the high impedance state that has been a problem in the past. Thus, it is possible to avoid malfunction caused by off-leakage, and it is possible to realize stable operation even in manufacturing and temperature condition fluctuations and low-speed operation.
[Embodiment 2]
FIG. 4 shows a circuit diagram of the flip-flop circuit according to the second embodiment of the present invention. Note that components having the same functions as those in the circuit of FIG. 1 described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 4, R1, R2, and R3 are a first resistance element, a second resistance element, and a third resistance element.
The resistor element R1 is inserted between the node n1 and the junction point between the PMOS transistor MP7 and the NMOS transistor MN7 of the control unit 4.

The resistance element R2 is inserted between the junction point of the PMOS transistor MP10 and the NMOS transistor MN11 of the control unit 4 and the node n2.
The resistor element R3 is inserted between the junction point of the PMOS transistor MP9 and NMOS transistor MN9 of the control unit 4 and the inverted output signal XQ.

Here, the first embodiment shown in FIG. 1 and the second embodiment will be compared and described.
In the first embodiment shown in FIG. 1, when the clock signal CK changes from low level to high level and the inverted output signal XQ changes from low level to high level, the two NMOS transistors of the control unit 4 A state in which the MN9 and MN8 and the PMOS transistor MP4 of the output unit 3 are simultaneously turned on occurs instantaneously, and a through current flows through the two NMOS transistors MN9 and MN8 and the PMOS transistor MP4, and the inverted output It may take time for the signal XQ to change from a low level to a high level. That is, the signal transmission speed may be reduced.

  In the second embodiment, when the inverted output signal XQ changes from the low level to the high level, the two NMOS transistors MN9 and MN8 and the PMOS transistor MP4 are simultaneously turned on, and the two NMOS transistors Even when a through current flows through the transistors MN9 and MN8 and the PMOS transistor MP4, the inverted output signal XQ is at a low level compared to the first embodiment shown in FIG. To change from high to high. That is, signal transmission can be speeded up.

  Similarly, when the node n1 changes from the low level to the high level, the voltage drop due to the resistance element R1 changes from the low level to the high level as compared with the first embodiment shown in FIG. When the node n2 changes from the low level to the high level, the voltage drop due to the resistance element R2 causes the change from the low level to the high level as compared with the first embodiment shown in FIG. The speed of signal transmission can be increased.

As described above, according to the second embodiment, the addition of the three resistance elements R1, R2, and R3 increases the number of elements as compared with the first embodiment, but the first of the control unit. It is possible to attenuate the output capability of the output of the control output unit 21, the output of the second control output unit 22, and the output of the third control output unit 23, and the signal transmission speed and transfer from the input unit 1 to the transfer unit 2 It is possible to suppress a decrease in the signal transmission speed from the unit 2 to the output unit 3 and the signal transmission speed from the output unit 3 to the next stage circuit, thereby realizing a higher speed operation.
[Embodiment 3]
FIG. 5 shows a circuit diagram of the flip-flop circuit in the third embodiment. The configuration of the input unit 1, the transfer unit 2, and the output unit 3 is the same as the conventional configuration of FIG.

In FIG. 8, C1, C2, and C3 are a first capacitor element, a second capacitor element, and a third capacitor element.
The capacitive element C1 is connected between ground and the node n1, the capacitive element C2 is connected between ground and the node n2, and the capacitive element C3 is connected between ground and the inverted output terminal XQ. .

Here, the conventional circuit shown in FIG. 8 is compared with the third embodiment.
When the node n1, which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9, is in a high impedance state, for example, the clock signal CK is at a high level and the input signal D is at a low level. When the level and the inverted output signal XQ are at a high level, the node n1 is in a high impedance state.

  Considering the case where the node n1 maintains a high level state and an off leak or a gate leak occurs in the transistor connected to the node n1, the third embodiment is compared with the conventional circuit shown in FIG. Then, the capacitance component attached to the node n1 is large, and the high level can be maintained for a long time.

  Further, when the node n2 which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9 is in a high impedance state, for example, the clock signal CK is at a high level, and the inverted output signal When XQ is at a low level, the node n2 is in a high impedance state.

  As an example, considering the case where the node n2 maintains a high level state and an off leak or a gate leak occurs in the transistor connected to the node n2, the present embodiment is compared with the conventional circuit shown in FIG. In the third embodiment, the capacitance component attached to the node n2 is large, and the high level can be maintained for a long time.

  When the node XQ, which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9, is in a high impedance state, for example, the clock signal CK is at a low level, and the inverted output signal When XQ is at a high level, the inverted output signal XQ is in a high impedance state.

  As an example, considering the case where the inverted output signal XQ is maintained at a high level and an off leak or a gate leak occurs in a transistor in the inverted output signal XQ, compared with the conventional circuit shown in FIG. In the second embodiment, the capacitance component attached to the inverted output signal XQ is large, and the high level can be maintained for a long time.

As described above, according to the third embodiment, even when transistor off-leakage or gate leak occurs, the potential holding time is longer than that in the conventional circuit, and a stable flip-flop operation can be realized. . If the capacitance elements C1, C2, and C3 are optimally set according to the frequency to be used, a stable operation can be realized although the number of elements increases.
[Embodiment 4]
FIG. 6 shows a circuit diagram of a flip-flop circuit according to Embodiment 4 of the present invention. The configuration of the input unit 1, the transfer unit 2, and the output unit 3 is the same as the conventional configuration of FIG.

  In FIG. 6, C1, C2, and C3 are a first capacitor element, a second capacitor element, and a third capacitor element, and 5, 6, and 7 are control signals input from a control terminal CNT1 (hereinafter referred to as control signal CNT1). ) Are a first switch unit, a second switch unit, and a third switch unit that are turned on / off.

  A switch unit 5 is inserted between the capacitive element C1 and the node n1, a switch unit 6 is inserted between the capacitive element C2 and the node n2, and a switch unit 7 is connected between the capacitive element C3 and the inverted output signal XQ. Inserted.

Here, the conventional circuit shown in FIG. 8 and the third example shown in FIG. 5 are compared with the present embodiment.
When the node n1, which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9, is in a high impedance state, for example, the clock signal CK is at a high level and the input signal D is at a low level. When the level and the inverted output signal XQ are at a high level, the node n1 is in a high impedance state.

  For example, when the node n1 is maintained at a high level and an off leak or a gate leak occurs in the transistor at the node n1, when the switch unit 5 is turned on by the control signal CNT1, The capacitive element C1 is connected between the ground and the node n1 and can perform the same operation as in FIG. 5 of the third embodiment. When the switch unit 5 is turned off by the control signal CNT1, the capacitive element C1 is connected to the ground. And the node n1 are separated, and the same operation as in FIG. 8 of the conventional example can be performed.

  Further, when the node n2 which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9 is in a high impedance state, for example, the clock signal CK is at a high level, and the node n1 is When the inverted output signal XQ is at a low level, the node n2 is in a high impedance state.

  As an example, when the case where the node n2 maintains a high level and an off leak or a gate leak occurs in the transistor at the node n2, when the switch unit 6 is turned on by the control signal CNT1, The capacitive element C2 is connected between the ground and the node n2, can perform the same operation as in FIG. 5 of the third embodiment, and when the switch unit 6 is turned off by the control signal CNT1, the capacitive element C2 And the node n2 are separated, and the same operation as in FIG. 8 of the conventional example can be performed.

  When the node XQ, which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9, is in a high impedance state, for example, the clock signal CK is at a low level, and the inverted output signal When XQ is at a high level, the inverted output signal XQ is in a high impedance state.

  As an example, considering the case where the inverted output signal XQ is maintained at a high level and an off leak or a gate leak occurs in a transistor in the inverted output signal XQ, the switch unit 7 is turned on by the control signal CNT1. At this time, the capacitive element C3 is connected between the ground and the inverted output signal XQ, and can perform the same operation as in FIG. 5 of the third embodiment. When the switch unit 5 is turned off by the control signal CNT1, The capacitive element C3 is disconnected between the ground and the inverted output signal XQ, and can perform the same operation as in FIG. 8 of the conventional example.

As described above, according to the fourth embodiment, the potential holding time is increased by the capacitive elements C1, C2, and C3, and a more stable flip-flop operation than the conventional circuit can be realized. 6 and 7, the capacitive elements C1, C2 and C3 are separated, and a flip-flop operation equivalent to that of the conventional circuit can be realized. Switching according to the frequency or use condition can be performed by inputting the control signal CNT1. Can be used properly. As described above, the high impedance state generated in the conventional circuit shown in FIG. 8 can be further stabilized, and the operation equivalent to the conventional circuit of FIG. 8 is performed by the control signal CNT1 when high speed operation is required. Can also be realized.
[Embodiment 5]
FIG. 7 shows a circuit diagram of a flip-flop circuit according to Embodiment 4 of the present invention. Note that components having the same operations as those of the circuit of FIG. 6 described in the fourth embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 7, C4, C5, and C6 are the fourth capacitor element, the fifth capacitor element, and the sixth capacitor element, and 8, 9, and 10 are control signals input from the control terminal CNT2 (hereinafter referred to as control signal CNT2). ), The fourth switch unit, the fifth switch unit, and the sixth switch unit that are turned on / off.

  The switch unit 8 and the capacitive element C4 are connected in series between the junction of the capacitive element C1 and the switch unit 5 and the ground, and the switch unit is connected between the junction of the capacitive element C2 and the switch unit 6 and the ground. 9 and the capacitive element C5 are connected in series, and the switch unit 10 and the capacitive element C6 are connected in series between the junction of the capacitive element C3 and the switch unit 7 and the ground.

Here, the conventional circuit shown in FIG. 8 and the fourth embodiment shown in FIG. 6 are compared with the fifth embodiment.
When the node n1, which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9, is in a high impedance state, for example, the clock signal CK is at a high level and the input signal D is at a low level. When the level and the inverted output signal XQ are at a high level, the node n1 is in a high impedance state.

  As an example, when the case where the node n1 maintains a high level and an off leak or a gate leak occurs in the transistor at the node n1, the switch unit 5 and the control unit CNT2 are controlled by the control signal CNT1 and the control signal CNT2, respectively. The switch unit 8 can be controlled to an on state and an off state, respectively, and the capacitive elements C1 and C4 added to the node n1 can be changed. This means that the capacitance value added to the node n1 can be controlled step by step.

  Further, when the node n2 which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9 is in a high impedance state, for example, the clock signal CK is at a high level, and the node n1 is When the inverted output signal XQ is at a low level, the node n2 is in a high impedance state.

  As an example, when the case where the node n2 maintains a high level and an off leak or a gate leak occurs in the transistor at the node n2, the switch unit 6 and the control unit CNT1 and the control signal CNT2, respectively, The switch unit 9 can be controlled to an on state and an off state, respectively, and the capacitive elements C2 and C5 added to the node n2 can be changed. This means that the capacitance value added to the node n2 can be controlled step by step.

  When the node XQ, which is a problem in the conventional example shown in the time chart of the conventional example shown in FIG. 9, is in a high impedance state, for example, the clock signal CK is at a low level, and the inverted output signal When XQ is at a high level, the inverted output signal XQ is in a high impedance state.

  As an example, when the inverted output signal XQ is maintained at a high level and an off leak or a gate leak occurs in a transistor in the inverted output signal XQ, the control signal CNT1 and the control signal CNT2 respectively The switch unit 7 and the switch unit 10 can be controlled to an on state and an off state, respectively, and the capacitive elements C3 and C6 added to the inverted output signal XQ can be changed. This means that the capacitance value added to the inverted output signal XQ can be controlled step by step.

  As described above, according to the fifth embodiment, switching is performed by adding the switch units 5, 6, 7, 8, 9, and 10 and the capacitive elements C1, C2, C3, C4, C5, and C6. The effect can be controlled in two stages, the high impedance state generated in the conventional circuit shown in FIG. 8 can be stabilized in a stepwise manner as compared with the fourth embodiment, and high-speed operation can be achieved. Even when necessary, the control signals CNT1 and CNT2 can realize an operation equivalent to the conventional one.

  The flip-flop circuit according to the present invention can stabilize the potential of the internal node regardless of the manufacturing, temperature conditions, and operation speed as compared with the conventional circuit, and thus is useful in the field of the flip-flop circuit that operates stably. is there.

1 is a circuit diagram illustrating a flip-flop circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of only a control unit of the flip-flop circuit of FIG. 1. It is a figure of the truth value which shows the operation | movement of FIG. It is a circuit diagram which shows the flip-flop circuit in Embodiment 2 of this invention. It is a circuit diagram which shows the flip-flop circuit in Embodiment 3 of this invention. It is a circuit diagram which shows the flip-flop circuit in Embodiment 4 of this invention. It is a circuit diagram which shows the flip-flop circuit in Embodiment 5 of this invention. It is a circuit diagram which shows the conventional flip-flop circuit. FIG. 9 is a time chart showing the operation of the flip-flop circuit of FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input part 2 Transfer part 3 Output part 4 Control part 5-10 Switch part 21-22 Control output part MP1-MP10 PMOS transistor MN1-MN11 NMOS transistor INV1-INV4 Inverter circuit R1-R3 Resistance element C1-C6 Capacitance element n01, n02 node CK clock signal D input signal XQ inverted output signal CNT1, CNT2 control signal

Claims (6)

An input terminal, a clock terminal, an output terminal, an input signal input to the input terminal and an input unit including a 3MOS transistor to which a clock signal input to the clock terminal is input; and the clock signal and the input A delay unit comprising: a transfer unit composed of a 3MOS transistor; an output unit composed of a 3MOS transistor that receives the clock signal and the output signal of the transfer unit and outputs a signal from the output terminal; A flip-flop circuit,
A first control output unit connected to the output of the input unit; a second control output unit connected to the output of the transfer unit; and a third control output unit connected to the output of the output unit; Providing a control unit to which the input signal, the clock signal, and the output signal of the output unit are input;
The control unit
When the clock signal is low level and the output signal of the output unit is low level, the output of the first control output unit is high impedance, the second control output unit outputs high level, The third control output unit outputs a low level;
When the clock signal is low level and the output signal of the output unit is high level, the output of the first control output unit is high impedance, the output of the second control output unit is high impedance, The third control output unit outputs a high level;
When the input signal is low level, the clock signal is high level, and the output signal of the output unit is low level, the first control output unit outputs low level, and the second control output Unit outputs a high level, the output of the third control output unit becomes high impedance,
When the input signal is high level, the clock signal is high level, and the output signal of the output unit is low level, the output of the first control output unit becomes high impedance, and the second control output Unit outputs a high level, the output of the third control output unit becomes high impedance,
When the input signal is low level, the clock signal is high level, and the output signal of the output unit is high level, the first control output unit outputs high level, and the second control output The output of the part becomes high impedance, the output of the third control output part becomes high impedance,
When the input signal is high level, the clock signal is high level, and the output signal of the output unit is high level, the output of the first control output unit becomes high impedance, and the second control output The flip-flop circuit is characterized in that the unit outputs a low level and the output of the third control output unit is a high impedance. A first resistive element between the output of the input unit and the first control output unit of the control unit, and a second between the output of the transfer unit and the second control output unit of the control unit. 2. The flip-flop circuit according to claim 1, further comprising: a resistance element; and a third resistance element between the output of the output unit and the third control output unit of the control unit. An input terminal, a clock terminal, an output terminal, an input signal input to the input terminal and an input unit including a 3MOS transistor to which a clock signal input to the clock terminal is input; and the clock signal and the input A delay unit comprising: a transfer unit composed of a 3MOS transistor; an output unit composed of a 3MOS transistor that receives the clock signal and the output signal of the transfer unit and outputs a signal from the output terminal; A flip-flop circuit,
A first capacitive element between the output of the input unit and a reference fixed potential;
A second capacitive element between the output of the transfer unit and the reference fixed potential;
A flip-flop circuit comprising a third capacitor element between the output of the output section and the fixed potential as the reference. A control terminal, a first switch unit to which a signal input to the control terminal is input, a second switch unit to which a signal input to the control terminal is input, and a signal input to the control terminal Has a third switch part to which is inputted,
The first switch unit is provided between the output of the input unit and the first capacitive element,
The second switch unit is provided between the output of the transfer unit and the second capacitive element,
4. The flip-flop circuit according to claim 3, wherein the third switch unit is provided between the output of the output unit and the third capacitive element. 5. A first control terminal; a second control terminal; a first switch unit to which a signal input to the first control terminal is input; and a signal input to the first control terminal. A second switch unit, a third switch unit to which a signal input to the first control terminal is input, and a fourth switch unit to which a signal input to the second control terminal is input A fifth switch unit to which a signal input to the second control terminal is input, a sixth switch unit to which a signal input to the second control terminal is input, and a first capacitor An element, a second capacitor element, a third capacitor element, a fourth capacitor element, a fifth capacitor element, and a sixth capacitor element;
The first switch unit between the output of the input unit and the first capacitive element, the second switch unit between the output of the transfer unit and the second capacitive element, and the output unit The third switch unit is provided between an output and the third capacitive element,
The fourth switch unit and the fourth capacitor element are connected in series between a connection point between the first capacitor element and the first switch unit and a fixed potential serving as a reference,
The fifth switch unit and the fifth capacitor element are connected in series between a connection point between the second capacitor element and the second switch unit and the fixed potential serving as the reference,
The sixth switch unit and the sixth capacitor element are connected in series between a connection point between the third capacitor element and the third switch unit and the reference fixed potential. The flip-flop circuit according to claim 3. The input section includes a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor connected in series between a power supply potential and a ground potential, and the first PMOS transistor and the first NMOS transistor. The input signal is input to the gate of the second PMOS transistor, the clock signal is input to the gate of the second PMOS transistor, and an output signal is output from a connection point between the second PMOS transistor and the first NMOS transistor. With configuration,
The transfer unit includes a third PMOS transistor, a second NMOS transistor, and a third NMOS transistor connected in series between the power supply potential and the ground potential, and the third PMOS transistor and the second NMOS transistor. The clock signal is input to the gate of the NMOS transistor, the output signal of the input unit is input to the gate of the third NMOS transistor, and from the connection point between the third PMOS transistor and the second NMOS transistor. It is configured to output an output signal,
The output unit includes a fourth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor connected in series between the power supply potential and the ground potential, and the fourth PMOS transistor and the fifth NMOS transistor are connected in series. The output signal of the transfer unit is input to the gate of the NMOS transistor, the clock signal is input to the gate of the fourth NMOS transistor, and from the connection point between the fourth PMOS transistor and the fourth NMOS transistor. 6. The flip-flop circuit according to claim 1, wherein an output signal is used as the output terminal.

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