CN115603732A - High-voltage-resistant interface circuit, interface equipment and CMOS chip - Google Patents

High-voltage-resistant interface circuit, interface equipment and CMOS chip Download PDF

Info

Publication number
CN115603732A
CN115603732A CN202211397842.6A CN202211397842A CN115603732A CN 115603732 A CN115603732 A CN 115603732A CN 202211397842 A CN202211397842 A CN 202211397842A CN 115603732 A CN115603732 A CN 115603732A
Authority
CN
China
Prior art keywords
transistor
input
control
signal
pull
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211397842.6A
Other languages
Chinese (zh)
Inventor
周倩
胡眺
胡万成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hunan Goke Microelectronics Co Ltd
Original Assignee
Hunan Goke Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hunan Goke Microelectronics Co Ltd filed Critical Hunan Goke Microelectronics Co Ltd
Priority to CN202211397842.6A priority Critical patent/CN115603732A/en
Publication of CN115603732A publication Critical patent/CN115603732A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The embodiment of the invention discloses a high-voltage-resistant interface circuit, interface equipment and a CMOS chip, wherein the high-voltage-resistant interface circuit comprises: the circuit comprises an input/output interface, a signal input interface, a signal output interface, an enable signal interface, a first inverter, a second inverter, a NAND gate, a NOR gate, a switch unit, a first control unit, a second control unit, a first isolation transistor, a second isolation transistor, a pull-up driving transistor and a pull-down driving transistor; based on the high-voltage-resistant interface circuit, the chip can directly carry out signal communication with external equipment, and when the signal voltage output by the external equipment is greater than the power supply voltage signal voltage of the chip, the switch unit, the first control unit, the second control unit and the isolation transistors can effectively prevent the signal of the external equipment from flowing backwards to the chip through the pull-up driving transistor or the pull-down driving transistor while ensuring the normal communication of the chip.

Description

High-voltage-resistant interface circuit, interface equipment and CMOS chip
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a high-voltage-resistant interface circuit, interface equipment and a CMOS chip.
Background
The level on the input/output interface of the chip is often higher than the operating power supply voltage of the chip, for example, the operating power supply voltage on the input/output interface of the CMOS chip generally does not exceed 3.3V, and the transistor-transistor logic (TTL) level is 5V. As shown in fig. 1, if a TTL level of 5V is connected to an input/output interface of a CMOS chip and a working power supply VDD in the CMOS chip is only 3.3V, a parasitic diode of the pull-up driving transistor MP1 may generate a back-flow current, and the chip may be burned down in a severe case.
In the existing scheme, an intermediate isolation device needs to be added between an interface of a CMOS chip and a TTL level to prevent the CMOS chip from being damaged, the scheme is high in cost, and when the CMOS chip needs to be connected with an external device, the operation is complex.
Disclosure of Invention
In order to solve the above technical problem, an embodiment of the present application provides a high voltage resistant interface circuit, an interface device, and a CMOS chip, and the specific scheme is as follows:
in a first aspect, an embodiment of the present application provides a high voltage tolerant interface circuit, configured to provide an interface for a CMOS chip, where the high voltage tolerant interface circuit includes: the circuit comprises an input/output interface, a signal input interface, a signal output interface, an enable signal interface, a first inverter, a second inverter, a NAND gate, a NOR gate, a switch unit, a first control unit, a second control unit, a first isolation transistor, a second isolation transistor, a pull-up driving transistor and a pull-down driving transistor;
the signal input interface and the signal output interface are both used for being connected with the CMOS chip, the signal input interface is used for receiving signals sent by the CMOS chip, and the signal output interface is used for inputting signals to the CMOS chip; the input and output interface is used for connecting external equipment;
the enable signal interface is connected with the first input end of the NAND gate through the first inverter, the enable signal interface is also connected with the first input end of the NOR gate, and the second input end of the NAND gate and the second input end of the NOR gate are both connected with the signal input interface;
the output end of the NAND gate is connected with the control end of the pull-up driving transistor through the first control unit, the source end of the pull-up driving transistor is used for accessing a power supply voltage signal, and the drain end of the pull-up driving transistor is used for connecting the input and output interface;
the output end of the NOR gate is connected with the control end of the pull-down driving transistor, the source end of the pull-down driving transistor is grounded, and the drain end of the pull-down driving transistor is connected with the input/output interface through the first isolation transistor;
the input/output interface is connected with the signal output interface through a divider resistor, a second isolation transistor and the second inverter;
one end of the second control unit is used for accessing the power supply voltage signal, the other end of the second control unit is connected with the substrate end of the pull-up driving transistor, and the second control unit is used for being switched off when the voltage at the input/output interface is greater than or equal to a preset voltage threshold value and being switched on when the voltage at the input/output interface is less than the preset voltage threshold value;
one end of the switch unit is connected with the input and output interface through the divider resistor, the other end of the switch unit is connected with the substrate end and the control end of the pull-up driving transistor, and the switch unit is used for being switched on when the voltage at the input and output interface is greater than or equal to a preset voltage threshold value and being switched off when the voltage at the input and output interface is less than the preset voltage threshold value.
According to a specific implementation of an embodiment of the present application, the first control unit includes a first control transistor and a second control transistor, and the second control unit includes a third control transistor and a weak pull-down body tube set;
the source end of the third control transistor is used for being connected with the power supply voltage signal, and the drain end of the third control transistor is connected with the substrate end of the pull-up driving transistor through a first potential point;
the output end of the NAND gate is connected with the control end of the pull-up driving transistor through the first control transistor and the second control transistor respectively, wherein the control end of the first control transistor is connected with the control end of the third control transistor through a second potential point, and the control end of the second control transistor is used for accessing the power supply voltage signal;
the weak pull-down transistor group comprises a preset number of N-type transistors connected in series, wherein the control end of each N-type transistor is connected with the drain end, and the control end voltage of each N-type transistor is obtained by voltage division of the second potential point.
According to a specific implementation of an embodiment of the present application, the switching unit includes a first switching transistor, a second switching transistor, and a third switching transistor;
the control ends of the first switch transistor, the second switch transistor and the third switch transistor are all used for accessing the power supply voltage signal;
the source ends of the first switch transistor, the second switch transistor and the third switch transistor are all connected with the input/output interface through the divider resistor;
a drain terminal of the first switching transistor is connected to substrate terminals of the first switching transistor, the second switching transistor, the third switching transistor, the first control transistor, the pull-up driving transistor, and the third control transistor, respectively, through the first potential point;
the drain terminal of the second switching transistor is connected to the control terminal of the third control transistor through the second potential point, the drain end of the three-switch transistor is connected with the control end of the pull-up driving transistor;
the first switch transistor, the second switch transistor, the third switch transistor, the first control transistor, the third control transistor and the pull-up driving transistor are all P-type transistors, and the second control transistor, the first isolation transistor, the second isolation transistor and the pull-down driving transistor are all N-type transistors.
According to a specific implementation manner of the embodiment of the present application, a source terminal of the first control transistor is connected to an output terminal of the nand gate, and a drain terminal of the first control transistor is connected to a control terminal of the pull-up driving transistor;
the source end of the second control transistor is connected with the output end of the NAND gate, and the drain end of the second control transistor is connected with the control end of the pull-up driving transistor.
According to a specific implementation manner of the embodiment of the present application, a drain of the pull-down driving transistor is connected to a source of the first isolation transistor, and a drain of the first isolation transistor is connected to the input/output interface;
and the source electrode of the second isolation transistor is connected with the input and output interface through the divider resistor, and the drain electrode of the second isolation transistor is connected with the signal output interface through the second inverter.
According to a specific implementation manner of the embodiment of the present application, when the enable signal interface is used for accessing a power supply voltage signal, the input/output interface is in an input mode; when the enabling signal interface is used for accessing a ground signal, the input/output interface is in an output mode;
the input/output interface is used for outputting signals to the external device in the output mode, and the input/output interface is used for receiving signals sent by the external device in the input mode.
According to a specific implementation manner of the embodiment of the present application, when the enable signal interface is used for accessing a power supply voltage signal, the second isolation transistor is turned on;
if the voltage value of the signal received by the input/output interface is greater than or equal to the preset voltage threshold, the first switch transistor, the second switch transistor and the third switch transistor are turned on, and the first control transistor, the second control transistor, the third control transistor, the pull-up driving transistor, the pull-down driving transistor and the first isolation transistor are all turned off;
if the voltage value of the signal received by the input/output interface is smaller than the preset voltage threshold, the first switch transistor, the second switch transistor and the third switch transistor are all turned off, the first control transistor and the third control transistor are all turned on, and the pull-up drive transistor, the pull-down drive transistor, the second control transistor and the first isolation transistor are all turned off.
According to a specific implementation manner of the embodiment of the present application, when the enable signal interface is used for accessing a ground signal, the first switch transistor, the second switch transistor, and the third switch transistor are all turned off, and the third control transistor is turned on;
if the signal input interface is used for accessing a high level signal, the first control transistor is turned off, the second control transistor is turned on, the pull-up driving transistor is turned on, the pull-down driving transistor is turned off, and the input/output interface is used for outputting the high level signal;
if the signal input interface is used for accessing a low level signal, the first control transistor is switched on, the second control transistor is switched off, the pull-up driving transistor is switched off, the pull-down driving transistor is switched on, and the input and output interface is used for outputting the low level signal.
In a second aspect, an embodiment of the present application provides an interface device, where the interface device includes the high voltage tolerant interface circuit described in any of the embodiments of the first aspect and the first aspect.
In a third aspect, an embodiment of the present application provides a CMOS chip, which includes the interface device according to the second aspect.
The embodiment of the application provides a high-voltage-resistant interface circuit, interface equipment and a CMOS chip, based on the high-voltage-resistant interface circuit provided by the invention, the CMOS chip can directly carry out signal communication with external equipment, and when the signal voltage output by the external equipment is greater than the power supply voltage signal voltage of the CMOS chip, a switch unit, a first control unit, a second control unit and isolation transistors effectively prevent the situation that the signal of the external equipment flows backwards to the CMOS chip through a pull-up driving transistor or a pull-down driving transistor while ensuring the normal communication of the CMOS chip, so that the communication safety of the CMOS chip is effectively improved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
Fig. 1 illustrates one of circuit schematic diagrams of a high voltage tolerant interface circuit according to an embodiment of the present application;
fig. 2 shows a second schematic circuit structure of a high voltage tolerant interface circuit according to an embodiment of the present application.
Summary of reference numerals:
input-output interface-PAD; signal input interface-IN; signal output interface-OUT; enable signal interface-OEN; a first inverter-INV 1; a second inverter-INV 2; a NAND gate-ND 1; nor gate-NR 1; a first switching transistor-MP 2; a second switching transistor-MP 4; a third switching transistor-MP 5; a first control transistor-MP 6; a second control transistor-MN 4; a third control transistor-MP 3; a first isolation transistor-MN 1, a second isolation transistor-MN 3; a pull-up drive transistor-MP 1; a pull-down drive transistor-MN 2; a first potential point-FNW; a second potential point-INT.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
Referring to fig. 1, a schematic circuit structure diagram of a high voltage tolerant interface circuit provided in an embodiment of the present application is shown, where the high voltage tolerant interface circuit provided in the embodiment of the present application is configured to provide an interface for a CMOS chip, and as shown in fig. 1, the high voltage tolerant interface circuit includes: the input/output circuit comprises an input/output interface PAD, a signal input interface IN, a signal output interface OUT, an enable signal interface OEN, a first inverter INV1, a second inverter INV2, a NAND gate ND1, a NOR gate NR1, a switch unit, a first control unit, a second control unit, a first isolation transistor MN1, a second isolation transistor MN3, a pull-up driving transistor MP1 and a pull-down driving transistor MN2;
the signal input interface IN and the signal output interface OUT are both used for being connected with the CMOS chip, the signal input interface IN is used for receiving signals sent by the CMOS chip, and the signal output interface OUT is used for inputting signals to the CMOS chip; the input/output interface PAD is used for connecting external equipment, when the input/output interface PAD is used as an input interface, the signal output interface OUT is used for outputting signals to the CMOS chip, and when the input/output interface PAD is used as an output interface, the signal input interface IN is used for receiving signals sent by the CMOS chip;
the enable signal interface OEN is connected with a first input end of the NAND gate ND1 through the first inverter INV1, the enable signal interface OEN is also connected with a first input end of the NOR gate NR1, and a second input end of the NAND gate ND1 and a second input end of the NOR gate NR1 are both connected with the signal input interface IN;
the output end of the nand gate ND1 is connected to the control end of the pull-up driving transistor MP1 through the first control unit, the source end of the pull-up driving transistor MP1 is used for accessing a power supply voltage signal, and the drain end of the pull-up driving transistor MP1 is used for connecting the input/output interface PAD;
the output end of the nor gate NR1 is connected to the control end of the pull-down driving transistor MN2, the source end of the pull-down driving transistor MN2 is grounded, and the drain end of the pull-down driving transistor MN2 is connected to the input/output interface PAD through the first isolation transistor MN 1;
the input/output interface PAD is connected with the signal output interface OUT through a voltage division resistor, a second isolation transistor MN3 and the second inverter INV2;
one end of the second control unit is used for accessing the power supply voltage signal VDD, the other end of the second control unit is connected with the substrate end of the pull-up driving transistor MP1, the second control unit is used for being turned off when the voltage at the input/output interface PAD is greater than or equal to a preset voltage threshold value, and is turned on when the voltage at the input/output interface PAD is less than the preset voltage threshold value;
one end of the switch unit is connected with the input and output interface PAD through the divider resistor, the other end of the switch unit is connected with the substrate end and the control end of the pull-up driving transistor MP1, and the switch unit is used for being switched on when the voltage at the input and output interface PAD is larger than or equal to a preset voltage threshold value and being switched off when the voltage at the input and output interface PAD is smaller than the preset voltage threshold value.
Specifically, the CMOS chip is a Complementary Metal Oxide Semiconductor (CMOS) chip, and in a specific application scenario, the CMOS chip is a readable and writable RAM chip and is used for storing hardware configuration information and user-defined setting parameters in a computer system.
The high voltage tolerant interface circuit provided by this embodiment may provide a connection design scheme for the CMOS chip to perform information communication with other devices IN the computer system, that is, the CMOS chip may implement information communication with external devices through the signal input interface IN and the signal output interface OUT.
The external device may be any device in the computer system that needs to communicate information with the CMOS chip, or may be a device outside the computer system that needs to communicate information with the CMOS chip, which is not limited in this embodiment.
The external equipment is in signal communication with the CMOS chip through the input-output interface PAD.
In addition, before the CMOS chip communicates signals with an external device, an enable signal may be sent to the enable signal interface OEN according to a sending function or a receiving function to be executed to determine whether the chip sends signals to the external device or receives signals from the external device, that is, to determine whether the input/output interface PAD is used as an input interface or an output interface.
Specifically, when the enable signal interface OEN is used for accessing a power supply voltage signal, the input/output interface PAD is in an input mode; when the enabling signal interface OEN is used for accessing a ground signal, the input/output interface PAD is in an output mode;
the input/output interface PAD is used for receiving a signal sent by the chip through the input interface IN and outputting the signal to the external device through the input/output interface PAD IN the output mode, and the input/output interface PAD is used for receiving the signal sent by the chip through the input/output interface PAD and outputting the signal to the external device through the output interface OUT IN the input mode.
In a specific embodiment, when an external device needs to send a signal to the CMOS chip, a power supply voltage signal is sent to the enable signal interface OEN, at this time, the input/output interface PAD serves as an input interface, and the signal sent by the external device is transmitted to the CMOS chip through the input/output interface PAD and the signal output interface OUT.
When the external device needs to obtain a signal from the CMOS chip, a ground signal is sent to the enable signal interface OEN, and at this time, the input/output interface PAD serves as an output interface, and the signal of the CMOS chip is transmitted to the external device through the signal input interface IN and the input/output interface PAD.
The switch unit may be a switch device that is turned on and off according to a change in the voltage of the input/output interface PAD, and specifically, when the voltage of the input/output interface PAD is greater than a preset voltage threshold, the switch unit is turned on, so that voltages of the substrate end and the control end of the pull-up driving transistor MP1 are kept synchronous with the voltage at the input/output interface PAD.
When the voltage of the input/output interface PAD is smaller than the preset voltage threshold, the switch unit is turned off, at this time, the voltage of the control end of the pull-up driving transistor MP1 is determined by the on-off condition of the first control unit, and the voltage of the substrate end of the pull-up driving transistor MP1 is determined by the on-off condition of the second control unit.
When the voltage of the input/output interface PAD is greater than or equal to the preset voltage threshold, at this time, the input/output interface PAD is in an input mode, and the voltage value of a signal sent by a connected external device is greater than the voltage value of a power supply voltage signal of the CMOS chip, the switch unit may synchronize the voltage at the input/output interface PAD to the control terminal and the substrate terminal of the second control unit, so that the second control unit remains off.
And when the voltage of the input/output interface PAD is smaller than the preset voltage threshold, the input/output interface PAD can be in an input mode or an output mode, the control end of the second control unit is grounded, the second control unit is conducted, and a power supply voltage signal of a source end is guided to the substrate end of the pull-up driving transistor through a first potential point FNW. And the first control unit is switched on and off according to the output signal of the NAND gate so as to control the on and off of the pull-up driving transistor.
In a specific embodiment, the first control unit comprises a first control transistor MP6 and a second control transistor MN4, the second control unit comprises a third control transistor MP3 and a weak pull-down body tube set;
the source end of the third control transistor MP3 is used for accessing the power supply voltage signal VDD, and the drain end of the third control transistor MP3 is connected to the substrate end of the pull-up driving transistor MP1 through a first potential point FNW; the control end of the third control transistor MP3 is grounded through the weak pull-down body tube group;
the output end of the nand gate ND1 is connected to the control end of the pull-up driving transistor MP1 through the first control transistor MP6 and the second control transistor MN4, respectively, wherein the control end of the first control transistor MP6 is connected to the control end of the third control transistor MP3 through a second potential point INT, and the control end of the second control transistor MN4 is used for receiving the power supply voltage signal VDD;
the switching unit includes a first switching transistor MP2, a second switching transistor MP4, and a third switching transistor MP5;
the first switch transistor MP2, the second switch transistor MP4 and the control terminal MP5 of the third switch transistor are all used for accessing the power voltage signal VDD;
the source ends of the first switch transistor MP2, the second switch transistor MP4 and the third switch transistor MP5 are all connected to the input/output interface PAD through the voltage dividing resistor;
the drain terminal of the first switch transistor MP2 is connected to the substrate terminals of the first switch transistor MP2, the second switch transistor MP4, the third switch transistor MP5, the first control transistor MP6, the pull-up drive transistor MP1 and the third control transistor MP3 through the first potential point FNW, respectively;
the drain terminal of the second switching transistor MP4 is connected to the control terminal of the third control transistor MP3 through the second potential point INT, and the drain terminal of the third switching transistor MP3 is connected to the control terminal of the pull-up driving transistor MP1;
the first inverter INV1 is configured to invert an enable signal received by the enable signal interface OEN, and when the enable signal interface OEN is connected to a power voltage signal, the first inverter INV1 outputs a ground signal, and when the enable signal interface OEN is connected to a ground signal, the first inverter INV1 outputs the power voltage signal.
A first input end of the nand gate ND1 is connected to an output end of the first inverter INV1, a second input end of the nand gate ND1 is connected to the signal input interface IN, an output end of the nand gate ND1 is connected to a source end of the first control transistor MP6 and a source end of the second control transistor MN4, wherein a gate of the first control transistor MP6 is connected to the second potential point INT, and a gate of the second control transistor MN4 is connected to a power supply voltage signal.
A first input terminal of the nor gate NR1 is directly connected to the enable signal interface OEN, a second input terminal of the nor gate NR1 is connected to the signal input interface IN, and an output terminal of the nor gate NR1 is connected to the gate of the pull-down driving transistor MN 2. The source electrode of the pull-down driving transistor MN2 is grounded, and the drain terminal of the pull-down driving transistor MN2 is connected with the input/output interface PAD through the first isolation transistor MN 1. When the pull-down driving transistor MN2 is conducted, the voltage signal at the input/output interface PAD is pulled down.
The second inverter INV2 is configured to invert an external device signal received by the input/output interface PAD, so as to transmit the external device signal to the signal output interface OUT. Specifically, the voltage at the input terminal of the second inverter INV2 should not be higher than the voltage of the power supply voltage signal.
When the input/output interface PAD is used as an input interface, the voltage dividing resistor is used for bearing the voltage of an input signal at the input/output interface PAD. The voltage dividing resistor in this embodiment may be one resistor, or may be formed by connecting a plurality of resistors in series or in parallel, and this embodiment limits the type of the voltage dividing resistor. The resistance value of the divider resistor can be adaptively set according to the voltage of an external device signal accessed by the input/output interface PAD in an actual application scene.
According to a specific implementation manner of the embodiment of the present application, the high voltage tolerant interface circuit further comprises a weak pull-down transistor group, the weak pull-down transistor group comprises a preset number of N-type transistors connected in series, wherein a control terminal of each N-type transistor is connected with a drain terminal, a control terminal voltage of each N-type transistor is obtained by dividing a voltage of the second potential point, a source terminal of a first-stage N-type transistor of the weak pull-down transistor group is grounded, and a drain terminal of an N-type transistor of a preset order of magnitude of the weak pull-down transistor group is connected with the second potential point INT.
For example, as shown in fig. 2, the weak pull-down transistor group includes 4N-type transistors MN5, MN6, MN7, and MN8 connected in series, where the control terminal voltage of MN5 is equal to the voltage at the second potential point, the control terminal voltage of MN6 is equal to 3/4 of the voltage at the second potential point, the control terminal voltage of MN7 is equal to 1/2 of the voltage at the second potential point, and the control terminal voltage of mn8 is equal to 1/4 of the voltage at the second potential point.
The weak pull-down transistor group is configured to pull down the voltage at the second potential point INT when the first, second, and third switching transistors MP2, MP4, and MP5 are all turned off, so that the third control transistor MP3 remains turned on.
When the second switching transistor MP4 is turned on and the voltage at the second potential point INT coincides with the voltage at the input/output interface PAD, the pull-down effect of the weak pull-down transistor group on the voltage at the second potential point INT is negligible, so that the third control transistor MP3 is kept turned off.
Specifically, the number of the weak pull-down transistor groups may be adaptively set according to a maximum voltage that can be accessed by the input/output interface PAD in an actual application scenario, which is not specifically limited in this embodiment.
According to a specific implementation manner of the embodiment of the present application, the first switch transistor MP2, the second switch transistor MP4, the third switch transistor MP5, the first control transistor MP6, the third control transistor MP3 and the pull-up driving transistor MP1 are P-type transistors, and the second control transistor MN4, the first isolation transistor MN1, the second isolation transistor MN3 and the pull-down driving transistor MN2 are N-type transistors.
Specifically, each transistor in this embodiment may also be configured by using a different type of transistor, and when each transistor is replaced by a different type of transistor, the connection condition of each transistor needs to be further changed to ensure that the flow of signals conforms to the principle of the high voltage resistant interface circuit design in this embodiment.
According to a specific implementation manner of the embodiment of the present application, a source terminal of the first control transistor MP6 is connected to the output terminal of the nand gate ND1, and a drain terminal of the first control transistor MP6 is connected to the control terminal of the pull-up driving transistor MP1;
the source end of the second control transistor MN4 is connected to the output end of the nand gate ND1, and the drain end of the second control transistor MN4 is connected to the control end of the pull-up driving transistor MP 1.
Specifically, as shown in fig. 2, the on/off of the first control transistor MP6 and the second control transistor MN4 determine the on/off of the pull-up driving transistor MP 1.
The on/off of the first control transistor MP6 and the second control transistor MN4 is determined by signals at a first potential point FNW and a second potential point INT.
Specifically, when the potential of the second potential point INT is a high-level signal and the potential of the first potential point FNW is also a high-level signal, the first control transistor MP6 and the second control transistor MN4 are always kept off. When the potential of the second potential point INT is a low level signal and the potential of the first potential point FNW is a high level signal, both the first control transistor MP6 and the second control transistor MN4 are kept on.
According to a specific implementation manner of the embodiment of the present application, a drain of the pull-down driving transistor MN2 is connected to a source of the first isolation transistor MN1, and a drain of the first isolation transistor MN1 is connected to the input/output interface PAD;
the source electrode of the second isolation transistor MN3 is connected with the input/output interface PAD through the voltage-dividing resistor, and the drain electrode of the second isolation transistor MN3 is connected with the signal output interface OUT through the second inverter INV 2.
Specifically, when the voltage at the input/output interface PAD is greater than the power supply voltage signal, the first isolation transistor MN1 is configured to ensure that the voltage at the pull-down driving transistor MN2 is not higher than the power supply voltage signal.
When the voltage at the input/output interface PAD is greater than the power supply voltage signal, the second isolation transistor MN3 is configured to ensure that the voltage at the input terminal of the second inverter INV2 is not higher than the power supply voltage signal.
For example, when the voltage at the input/output interface PAD is 3.8V and the power supply voltage signal is 3.3V, the first isolation transistor MN1 is configured to ensure that the voltage at the pull-down driving transistor MN2 is not higher than 3.3V, and the second isolation transistor MN3 is configured to ensure that the voltage at the input terminal of the second inverter INV2 is not higher than 3.3V.
According to a specific implementation manner of the embodiment of the present application, when the enable signal interface OEN is used for accessing a power supply voltage signal, the second isolation transistor MN3 is turned on;
if the voltage value of the signal received by the input/output interface PAD is greater than the preset voltage threshold, the first switch transistor MP2, the second switch transistor MP4, and the third switch transistor MP5 are turned on, and the first control transistor MP6, the second control transistor MN4, the third control transistor MP3, the pull-up drive transistor MP1, the pull-down drive transistor MN2, and the first isolation transistor MN1 are all turned off;
if the voltage value of the signal received by the input/output interface PAD is smaller than the preset voltage threshold, the first switch transistor MP2, the second switch transistor MP4 and the third switch transistor MP5 are all turned off, the first control transistor MP6, the second control transistor MN4 and the third control transistor MP3 are all turned on, and the pull-up drive transistor MP1, the pull-down drive transistor MN2 and the first isolation transistor MN1 are all turned off.
Specifically, when the enable signal interface OEN is connected to the power supply voltage signal, the input/output interface PAD in this embodiment is in an input mode, and the voltage value of the external device signal received at the input/output interface PAD includes two cases, which are a case greater than a preset voltage threshold and a case smaller than the preset voltage threshold.
The setting of the preset voltage threshold is determined according to a voltage value of a power supply voltage signal of the CMOS chip, for example, when the voltage value of the power supply voltage signal is 3.3V, the preset voltage threshold may be set to 3.8V. The specific value of the preset voltage threshold is not limited in this embodiment, and can be set adaptively according to the actual application scenario.
Assuming that the voltage value of the external device signal inputted at the input/output interface PAD is higher than the preset voltage threshold, i.e. higher than 3.8V, the first switch transistor MP2 is turned on, so that the voltage at the first potential point FNW is pulled up to be the same as the voltage of the external device signal inputted at the input/output interface PAD. At this time, the voltages at the substrate ends of MP1-MP6 are all pulled to the same voltage as the external device signal connected at the input-output interface PAD.
The second switch transistor MP4 is turned on, so that the voltage at the second potential point INT is pulled up to be the same as the voltage of the external device signal inputted at the input/output interface PAD. At this time, the weak pull-down body tube group is neglected, and the third control transistor MP3 is turned off, so that the external device signal cannot flow back to the power supply through the third control transistor MP 3.
The third switching transistor MP5 is turned on, and the voltage of the control terminal of the pull-up driving transistor MP1 is pulled up to be the same as the voltage of the external device signal connected at the input/output interface PAD. At this time, the pull-up driving transistor MP1 is turned off, so that the external device signal cannot flow back to the power supply through the pull-up driving transistor MP 1.
The signal accessed by the enable signal interface OEN is a power supply voltage signal, the signal output by the second inverter INV2 is a ground signal, and the signal input interface IN does not work, so the first input end and the second input end of the nand gate ND1 are both accessed with ground signals, and the nand gate ND1 outputs the power supply voltage signal. At this time, the first control transistor MP6 and the second control transistor MN4 are both turned off.
The first input end of the NOR gate NR1 is connected with a power supply voltage signal, the second input end of the NOR gate NR1 is connected with a ground signal, and the NOR gate NR1 outputs a low signal. At this time, the pull-down driving transistor MN2 is turned off.
Therefore, when the voltage value of the external device signal input at the input/output interface PAD is higher than the preset voltage threshold, that is, higher than 3.8V, the external device signal can be normally transmitted to the CMOS chip through the voltage dividing resistor, the second isolating transistor MN3, the second inverter INV2, and the signal output interface OUT.
And when the external device signal is higher than the preset voltage threshold, the first isolation transistor MN1 isolates the input/output interface PAD from the pull-down driving transistor MN2, so that the drain voltage of the pull-down driving transistor MN2 is not higher than the power supply voltage signal. The second isolation transistor MN3 isolates the input/output interface PAD from the second inverter INV2, so that the voltage at the input end of the second inverter INV2 is not higher than the power supply voltage signal.
It should be noted that, when the voltage value of the external device signal connected to the input/output interface PAD is equal to the preset voltage threshold, the specific implementation process of the high voltage tolerant interface circuit in this embodiment refers to the above situation that is greater than the preset voltage threshold, which is not described herein again.
Assuming that the voltage value of the external device signal input at the input/output interface PAD is lower than the preset voltage threshold, i.e. lower than 3.8V, at this time, the first switch transistor MP2, the second switch transistor MP4 and the third switch transistor MP5 are all turned off. The voltage at the second potential point INT is pulled down to ground by the weak pull-down transistor group, at which time the third control transistor MP3 is turned on and the voltage at the first potential point FNW is pulled up to the same voltage as the power supply voltage signal.
The substrate ends of the MP1-MP6 are all pulled to the same voltage as the power supply voltage signal.
The nand gate ND1 outputs a power voltage signal, the control terminal of the first control transistor MP6 is connected to a ground signal, the first control transistor MP6 is turned on, the voltage of the control terminal of the pull-up driving transistor MP1 is the same as the voltage of the power voltage signal, and the pull-up driving transistor MP1 is turned off.
The nor gate NR1 outputs a low signal and the pull-down drive transistor MN2 remains off.
Therefore, when the voltage value of the external device signal input at the input/output interface PAD is lower than the preset voltage threshold, that is, lower than 3.8V, the external device signal may also be transmitted to the CMOS chip through the voltage dividing resistor, the second isolation transistor MN3, the second inverter INV2, and the signal output interface OUT.
According to a specific implementation manner of the embodiment of the present application, when the enable signal interface OEN is used for accessing a ground signal, the first switch transistor MP2, the second switch transistor MP4, and the third switch transistor MP5 are all turned off, and the first control transistor MP6, the second control transistor MN4, and the third control transistor MP3 are all turned on;
if the signal input interface IN is used for accessing a high-level signal, the pull-up driving transistor MP1 is turned on, the pull-down driving transistor MN2 is turned off, and the input-output interface PAD is used for outputting a high-level signal;
if the signal input interface IN is used for accessing a low level signal, the pull-up driving transistor MP1 is turned off, the pull-down driving transistor MN2 is turned on, and the input-output interface PAD is used for outputting a low level signal.
Specifically, when the enable signal interface OEN is used for accessing a ground signal, the input/output interface PAD IN this embodiment is IN an output mode, and a signal output by the input/output interface PAD is adaptively changed according to a signal received by the signal input interface IN.
When the input/output interface PAD is used for outputting a signal, the voltage at the input/output interface PAD is not greater than the voltage of the power supply voltage signal, the first switch transistor MP2, the second switch transistor MP4 and the third switch transistor MP5 are all turned off, at this time, the voltage at the second potential point INT is pulled down to the ground by the weak pull-down transistor group, the third control transistor MP3 is turned on, and the voltage at the first potential point FNW is pulled up to be the same as the voltage of the power supply voltage signal.
The first control transistor MP6 and the second control transistor MN4 are both turned on.
When the signal received by the signal input interface IN is a high level signal, i.e., a power supply voltage signal, the signals of the first input end and the second input end of the nand gate ND1 are both high level signals, and the signal output by the nand gate ND1 is a low level signal. The signal of the first input end of the nor gate NR1 is a ground signal, the signal of the second input end is a high level signal, and the signal output by the nor gate NR1 is a low level signal.
At this time, the pull-up driving transistor MP1 is turned on, the pull-down driving transistor MN2 is turned off, and the input/output interface PAD outputs a high level signal.
When the signal received by the signal input interface IN is a low level signal, i.e., a ground signal, the first input terminal of the nand gate ND1 is a high level signal, the second input terminal is a ground signal, and the nand gate ND1 outputs a high level signal. The first input end of the nor gate NR1 is a ground signal, the second input end is a low level signal, and the nor gate NR1 outputs a high level signal.
At this time, the pull-up driving transistor MP1 is turned off, the pull-down driving transistor MN2 is turned on, and the input/output interface PAD outputs a low level signal.
When the enable signal is a ground signal, the high voltage tolerant interface circuit provided by this embodiment can normally transmit a signal received by the signal input interface IN to the input/output interface PAD, so that the external device can obtain data IN the CMOS chip.
In summary, the present embodiment provides a high voltage tolerant interface circuit, which controls the magnitudes of the first potential point, the second potential point and the gate of the pull-up driving transistor respectively by turning on and off the first switching transistor, the second switching transistor and the third switching transistor. When the input voltage of the input/output interface PAD is greater than the input signal of the power supply voltage signal, the substrate end of the pull-up driving transistor and the potential at the input/output interface PAD can be synchronized by turning on the first switching transistor, the second switching transistor and the third switching transistor, so that the pull-up driving transistor cannot be subjected to voltage backflow and is damaged under the condition that the high-voltage resistant interface circuit can normally work.
In addition, in this embodiment, by providing the first isolation transistor and the second isolation transistor, when the voltage at the PAD of the input/output interface is high, it is ensured that the potential at the interface between the pull-down driving transistor and the signal output interface is not damaged by the transistor due to too high voltage, thereby further ensuring the safety of the high voltage resistant interface circuit.
Through the high voltage resistant interface circuit that this embodiment provided, need not to set up extra step-down device between CMOS chip and external equipment, can realize the direct communication between CMOS chip and the external equipment, carry out direct communication with 5V's TTL interface for example, effectively promoted the availability factor of CMOS chip, reduced manufacturing cost.
In addition, an embodiment of the present application provides an interface device, where the interface device includes the high voltage tolerant interface circuit in the foregoing circuit embodiment.
Specifically, the interface device in this embodiment may be any communication connector that carries the high voltage resistant interface circuit in the foregoing circuit embodiment, and the type of the interface device is not limited in this embodiment.
It should be understood that the interface device may also be directly disposed inside the CMOS chip, which is not limited in this embodiment.
The embodiment of the present application further provides a CMOS chip, where the CMOS chip includes the interface device in the foregoing embodiment.
Specifically, the CMOS chip in this embodiment performs signal communication with an external device through the interface device, and a voltage of a signal output by the external device may be greater than a supply voltage of the CMOS chip.
For the specific implementation process of the interface device and the CMOS chip mentioned in the above embodiments, reference may be made to the specific implementation process of the above circuit embodiment, and details are not described here.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.

Claims (10)

1. A high voltage tolerant interface circuit for interfacing a CMOS chip, the high voltage tolerant interface circuit comprising: the circuit comprises an input/output interface, a signal input interface, a signal output interface, an enable signal interface, a first inverter, a second inverter, a NAND gate, a NOR gate, a switch unit, a first control unit, a second control unit, a first isolation transistor, a second isolation transistor, a pull-up driving transistor and a pull-down driving transistor;
the signal input interface and the signal output interface are both used for being connected with the CMOS chip, the signal input interface is used for receiving signals sent by the CMOS chip, and the signal output interface is used for inputting signals to the CMOS chip; the input and output interface is used for connecting external equipment;
the enable signal interface is connected with the first input end of the NAND gate through the first inverter, the enable signal interface is also connected with the first input end of the NOR gate, and the second input end of the NAND gate and the second input end of the NOR gate are both connected with the signal input interface;
the output end of the NAND gate is connected with the control end of the pull-up driving transistor through the first control unit, the source end of the pull-up driving transistor is used for accessing a power supply voltage signal, and the drain end of the pull-up driving transistor is used for connecting the input and output interface;
the output end of the NOR gate is connected with the control end of the pull-down driving transistor, the source end of the pull-down driving transistor is grounded, and the drain end of the pull-down driving transistor is connected with the input/output interface through the first isolation transistor;
the input/output interface is connected with the signal output interface through a divider resistor, a second isolation transistor and the second inverter;
one end of the second control unit is used for accessing the power supply voltage signal, the other end of the second control unit is connected with the substrate end of the pull-up driving transistor, and the second control unit is used for being switched off when the voltage at the input/output interface is greater than or equal to a preset voltage threshold value and being switched on when the voltage at the input/output interface is less than the preset voltage threshold value;
one end of the switch unit is connected with the input and output interface through the divider resistor, the other end of the switch unit is connected with the substrate end and the control end of the pull-up driving transistor, and the switch unit is used for being switched on when the voltage at the input and output interface is greater than or equal to a preset voltage threshold value and being switched off when the voltage at the input and output interface is less than the preset voltage threshold value.
2. The high voltage tolerant interface circuit of claim 1, wherein the first control unit comprises a first control transistor and a second control transistor, the second control unit comprises a third control transistor and a weak pull-down transistor bank;
the source end of the third control transistor is used for being connected with the power supply voltage signal, and the drain end of the third control transistor is connected with the substrate end of the pull-up driving transistor through a first potential point;
the output end of the NAND gate is connected with the control end of the pull-up driving transistor through the first control transistor and the second control transistor respectively, wherein the control end of the first control transistor is connected with the control end of the third control transistor through a second potential point, and the control end of the second control transistor is used for accessing the power supply voltage signal;
the weak pull-down transistor group comprises a preset number of N-type transistors connected in series, wherein the control end of each N-type transistor is connected with the drain end, and the control end voltage of each N-type transistor is obtained by voltage division of the second potential point.
3. The high voltage tolerant interface circuit of claim 2, wherein said switching unit comprises a first switching transistor, a second switching transistor, and a third switching transistor;
the control ends of the first switching transistor, the second switching transistor and the third switching transistor are all used for accessing the power supply voltage signal;
the source ends of the first switch transistor, the second switch transistor and the third switch transistor are all connected with the input/output interface through the divider resistor;
a drain terminal of the first switching transistor is connected to substrate terminals of the first switching transistor, the second switching transistor, the third switching transistor, the first control transistor, the pull-up driving transistor, and the third control transistor, respectively, through the first potential point;
the drain terminal of the second switching transistor is connected with the control terminal of the third control transistor through the second potential point, and the drain terminal of the third switching transistor is connected with the control terminal of the pull-up driving transistor;
the first switch transistor, the second switch transistor, the third switch transistor, the first control transistor, the third control transistor and the pull-up driving transistor are all P-type transistors, and the second control transistor, the first isolation transistor, the second isolation transistor and the pull-down driving transistor are all N-type transistors.
4. The high voltage tolerant interface circuit of claim 3, wherein a source terminal of the first control transistor is connected to an output terminal of the NAND gate, and a drain terminal of the first control transistor is connected to a control terminal of the pull-up driving transistor;
the source end of the second control transistor is connected with the output end of the NAND gate, and the drain end of the second control transistor is connected with the control end of the pull-up driving transistor.
5. The high voltage tolerant interface circuit of claim 3, wherein a drain of the pull-down driving transistor is connected to a source of the first isolation transistor, and a drain of the first isolation transistor is connected to the input/output interface;
and the source electrode of the second isolation transistor is connected with the input/output interface through the divider resistor, and the drain electrode of the second isolation transistor is connected with the signal output interface through the second phase inverter.
6. The high voltage tolerant interface circuit of claim 3, wherein the input-output interface is in an input mode when the enable signal interface is used to access a supply voltage signal; when the enabling signal interface is used for accessing a ground signal, the input/output interface is in an output mode;
the input/output interface is used for outputting signals to the external device in the output mode, and the input/output interface is used for receiving signals sent by the external device in the input mode.
7. The high voltage tolerant interface circuit of claim 6, wherein the second isolation transistor is turned on when the enable signal interface is used to access a supply voltage signal;
if the voltage value of the signal received by the input/output interface is greater than or equal to the preset voltage threshold, the first switch transistor, the second switch transistor and the third switch transistor are turned on, and the first control transistor, the second control transistor, the third control transistor, the pull-up driving transistor, the pull-down driving transistor and the first isolation transistor are all turned off;
if the voltage value of the signal received by the input/output interface is smaller than the preset voltage threshold, the first switch transistor, the second switch transistor and the third switch transistor are all turned off, the first control transistor and the third control transistor are all turned on, and the pull-up drive transistor, the pull-down drive transistor, the second control transistor and the first isolation transistor are all turned off.
8. The high voltage tolerant interface circuit of claim 6, wherein when said enable signal interface is configured to access a ground signal, said first switch transistor, said second switch transistor, said third switch transistor are all turned off, and said third control transistor is all turned on;
if the signal input interface is used for accessing a high level signal, the first control transistor is turned off, the second control transistor is turned on, the pull-up driving transistor is turned on, the pull-down driving transistor is turned off, and the input and output interface is used for outputting the high level signal;
if the signal input interface is used for accessing a low level signal, the first control transistor is switched on, the second control transistor is switched off, the pull-up driving transistor is switched off, the pull-down driving transistor is switched on, and the input and output interface is used for outputting the low level signal.
9. An interface device, characterized in that it comprises a high voltage tolerant interface circuit according to any of claims 1-8.
10. A CMOS chip comprising the interface device of claim 9.
CN202211397842.6A 2022-11-09 2022-11-09 High-voltage-resistant interface circuit, interface equipment and CMOS chip Pending CN115603732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211397842.6A CN115603732A (en) 2022-11-09 2022-11-09 High-voltage-resistant interface circuit, interface equipment and CMOS chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211397842.6A CN115603732A (en) 2022-11-09 2022-11-09 High-voltage-resistant interface circuit, interface equipment and CMOS chip

Publications (1)

Publication Number Publication Date
CN115603732A true CN115603732A (en) 2023-01-13

Family

ID=84853525

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211397842.6A Pending CN115603732A (en) 2022-11-09 2022-11-09 High-voltage-resistant interface circuit, interface equipment and CMOS chip

Country Status (1)

Country Link
CN (1) CN115603732A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117749158A (en) * 2024-02-19 2024-03-22 北京中天星控科技开发有限公司成都分公司 Anti-backflow protection circuit for power failure of interface chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117749158A (en) * 2024-02-19 2024-03-22 北京中天星控科技开发有限公司成都分公司 Anti-backflow protection circuit for power failure of interface chip
CN117749158B (en) * 2024-02-19 2024-04-19 北京中天星控科技开发有限公司成都分公司 Anti-backflow protection circuit for power failure of interface chip

Similar Documents

Publication Publication Date Title
US20150171858A1 (en) Semiconductor integrated circuit
US6184716B1 (en) High voltage output stage for driving an electric load
EP0961206B1 (en) High voltage tolerant and compliant driver circuit
JP3687422B2 (en) Interface circuit
CN108768381B (en) GPIO circuit and chip
JPH0832434A (en) Output circuit
CN107005237B (en) Method, system, apparatus and device for buffer circuit
EP1717955B1 (en) Buffer circuit
CN114895738B (en) Fail-safe control voltage generating circuit and anti-backflow circuit
CN115603732A (en) High-voltage-resistant interface circuit, interface equipment and CMOS chip
KR100363381B1 (en) Two-supply protection circuit
CN113992199A (en) Integrated circuit and signal transmission method thereof
US6201428B1 (en) 5-volt tolerant 3-volt drive push-pull buffer/driver
EP2957985B1 (en) Control circuit and control system
EP0874462B1 (en) Pull-up circuit and semiconductor device using the same
CN101438491A (en) High voltage tolerant port driver
KR19990083515A (en) CMOS Output Buffer Protection Circuit
US11177808B2 (en) Semiconductor device
JP3923397B2 (en) Level translator circuit
CN215871359U (en) IO architecture for preventing current backflow
CN113821068B (en) Multi-power-supply system management circuit and method in chip
CN113676172A (en) IO architecture for preventing current backflow
KR100384778B1 (en) Bus line driving circuit
CN114744605A (en) IO sends ware, chip and electronic equipment
CN115149941A (en) Fail-safe I/O interface circuit and system on chip

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination