CN115149941A - Fail-safe I/O interface circuit and system on chip - Google Patents

Fail-safe I/O interface circuit and system on chip Download PDF

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Publication number
CN115149941A
CN115149941A CN202110350450.3A CN202110350450A CN115149941A CN 115149941 A CN115149941 A CN 115149941A CN 202110350450 A CN202110350450 A CN 202110350450A CN 115149941 A CN115149941 A CN 115149941A
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China
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terminal
coupled
transistor
output
control
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王瑞丽
雷玮
许道海
陈先敏
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Shenzhen Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Shenzhen Corp
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Priority to CN202110350450.3A priority Critical patent/CN115149941A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
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  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

Fail safe I/O interface circuit and system on a chip, fail safe I/O interface circuit includes: enable signal terminal, control unit and output unit, wherein: the enable signal end is coupled with the output unit and is suitable for controlling the on-off of an input node and an output node of the output unit based on an input enable signal; the control unit is coupled with a power supply end and the output unit, and is suitable for generating a control signal based on the voltage of the power supply end and the voltage of an output node of the output unit and outputting the control signal to the output unit, so that the output node outputs a corresponding signal when the signal of the enable signal end changes; the output unit is respectively coupled with a power supply end, an enable signal end and the control unit, and is suitable for outputting the corresponding signals through the output node based on the enable signal and the control signal. By adopting the scheme, the reliability of the output signal of the fail-safe I/O interface circuit can be improved.

Description

Fail-safe I/O interface circuit and system on chip
Technical Field
The embodiment of the invention relates to the field of integrated circuits, in particular to a fault-safe I/O interface circuit and a system on a chip.
Background
With the rapid development of Integrated Circuits (ICs), the IC is applied more widely in the field of electronic products, and the requirement for reliability is higher and higher.
In a specific application scenario, for example, in a System On Chip (SOC), when an input terminal of the SOC is powered off, and a device connected to an external node of the SOC circuit normally operates and is at a high level, a current generated by the device flows back into the SOC through the external node of the circuit, so that a transistor inside the SOC is burned or even burnt.
However, when the signal of the enable terminal of the fail-safe I/O interface circuit changes, the fail-safe I/O interface circuit is liable to output an error signal, which affects the normal operation of the system.
Disclosure of Invention
In view of this, embodiments of the present invention provide a fail-safe I/O interface circuit and a system on a chip, which can improve the reliability of an output signal of the fail-safe I/O interface circuit, and further improve the safety and the service life of a system circuit.
First, an embodiment of the present invention provides a fail-safe I/O interface circuit, where the fail-safe I/O interface circuit includes: enable signal terminal, control unit and output unit, wherein:
the enable signal terminal is coupled with the output unit and is suitable for controlling the on-off of an input node and an output node of the output unit based on an input enable signal;
the control unit is coupled with a power supply end and the output unit, and is suitable for generating a control signal based on the voltage of the power supply end and the voltage of an output node of the output unit and outputting the control signal to the output unit, so that the output node outputs a corresponding signal when the signal of the enable signal end changes;
the output unit is respectively coupled to the power source terminal, the enable signal terminal and the control unit, and is adapted to output the corresponding signal through the output node based on the enable signal and the control signal.
Correspondingly, an embodiment of the present invention further provides a system on a chip, where the system on a chip includes: the fail-safe I/O interface circuit described in the foregoing embodiment includes an enable signal terminal, a control unit, and an output unit;
a processor coupled to a power source terminal, an enable signal terminal of the fail-safe I/O interface circuit, and an input node of the output unit, and adapted to input an enable signal to the fail-safe I/O interface circuit through the enable signal terminal, and to input a clock signal or a level signal to the input node of the output unit.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
by adopting the fail-safe I/O interface circuit in the embodiment of the present invention, the fail-safe I/O interface includes an enable signal terminal, a control unit, an output unit and a pull-down protection unit, wherein, since the control unit is coupled to a power terminal and the control unit, a control signal can be generated based on a voltage of the power terminal and a voltage of an output node of the output unit, and the control signal is output to the output unit, and the output unit can output a corresponding signal, rather than an erroneous signal, when a signal of the enable signal terminal changes based on the enable signal of the enable signal terminal and the control signal, thereby improving reliability of an output signal of the fail-safe I/O interface circuit, and further improving safety and service life of a system circuit.
In an alternative, the control signal generation module is capable of outputting a control signal that is not affected by an enable signal terminal based on the voltage at the power supply terminal and the voltage at the output node of the output unit, so that the fail-safe I/O interface circuit can still normally operate in a fault state, by coupling a control terminal of the control signal generation module with the power supply terminal, coupling a first terminal with the output node of the output unit, and coupling a second terminal with the first control terminal of the output unit; and the first control end of the well potential module is coupled with the power supply end, the first end of the well potential module is coupled with the output node of the output unit, the second control end of the well potential module is coupled with the output node of the output unit, the second end of the well potential module is coupled with the power supply end, and the third end of the well potential module is coupled with the first output end of the output unit and the third end of the control signal generation module respectively.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention or in the description of the prior art will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 shows a schematic circuit diagram of a fail-safe I/O interface circuit.
Fig. 2 illustrates a waveform diagram of voltage changes at a critical node of the fail-safe I/O interface circuit of fig. 1.
Fig. 3 shows a schematic structural diagram of a fail-safe I/O interface circuit in an embodiment of the present invention.
Fig. 4 shows a specific structural diagram of a fail-safe I/O interface circuit in an embodiment of the present invention.
Fig. 5 shows a waveform diagram of voltage changes at a critical node of a fail-safe I/O interface circuit in a third example of an embodiment of the present invention.
Fig. 6 shows a schematic structural diagram of a system on chip in an embodiment of the present invention.
Detailed Description
As described in the background art, the current fail-safe I/O interface circuit is susceptible to the enable end, and when the signal of the enable end changes, the fail-safe I/O interface circuit is prone to output an error signal, thereby affecting the normal operation of the system.
To more clearly illustrate the vulnerability of the fail-safe I/O interface circuit to the enable terminal in the prior art, the following detailed description is provided with accompanying drawings and specific examples.
Referring to fig. 1, a schematic structural diagram of a failsafe I/O interface circuit is shown, the failsafe I/O interface circuit is powered by a power supply terminal VDD, wherein the failsafe I/O interface circuit includes an enable signal terminal OEN, a control module 11, an output module 12, and a pull-down protection module PD, where:
the control module 11 may include a first inverter P11, an input node I, a NAND gate NAND, a second inverter P12, a third inverter P13, a transmission gate TG, P-type transistors PM1, PM2, and an output node PAD, which are connected in sequence, wherein a first end of the NAND gate NAND is coupled to an enable signal terminal OEN through the first inverter P11, a second end of the NAND gate NAND is coupled to the input node I, and an output of the third inverter P13 is coupled to an input terminal of the transmission gate TG; a second control end of the transmission gate TG is respectively coupled with a power supply end VDD and a grid electrode of the P-type transistor PM2, and an output end of the transmission gate TG is coupled with a grid electrode of the P-type transistor PM 1; the source electrode of the P-type transistor PM2 is coupled to the output end of the transmission gate TG and is connected with the grid electrode of the P-type transistor PM1, and the drain electrode of the P-type transistor PM2 is coupled with the pull-down protection module PD; the source of the P-type transistor PM1 is coupled to the power supply terminal VDD, and the drain thereof is coupled to the output node PAD.
The control block 12 may include P-type transistors PM3, PM4 and PM5 and N-type transistors NM1, NM2, wherein the gate of the N-type transistor NM1 is directly coupled to the enable signal terminal OEN, the source thereof is coupled to the output node PAD of the output block 11, the drain thereof is coupled to the source of the N-type transistor NM2 and to the first control terminal of the transmission gate TG in the output block 11, and the substrate thereof is coupled to the substrate of the N-type transistor NM 2; the N transistor NM2 is coupled to the enable signal terminal OEN through a fourth inverter P14, and a drain thereof is coupled to ground; the gate of the P-type transistor PM3 is coupled to the power supply terminal VDD, the source thereof is coupled to the output node PAD, and the drain thereof is coupled to the gate of the P-type transistor PM 4; the source electrode of the P-type transistor PM4 is coupled with the power supply end VDD, and the drain electrode and the substrate of the P-type transistor PM4 are respectively coupled with the drain electrode and the substrate of the P-type transistor PM5 and are coupled with the substrate of the P-type transistor PM 1; the gate of the P-type transistor PM5 is coupled to the power supply terminal VDD, and its source is coupled to the output node PAD.
The pull-down protection module PD is coupled between an output node PAD of the output module 11 and ground.
In a specific implementation, when the level of the enable signal terminal OEN is switched from 0 (corresponding to a low level) to 1 (corresponding to a high level), if the level of the output node PAD is at a high level 1, the gate of NM1 is coupled to the enable signal terminal OEN, such that the gate voltage of NM1 is greater than the source voltage thereof, NM1 is turned on, and V is greater than the source voltage thereof P_PASS ＝V PAD -V thn Wherein V is thn The threshold voltage is the NMI threshold voltage.
Voltage V of control signal P _ PASS output via NM1 P_PASS The voltage of the grid electrode of the P-type transistor PM1 cannot be changed into 1 quickly due to the fact that the potential output by the transmission gate TG is from low level 0 to high level 1, and the P-type transistor PM1 is conducted weakly; when the grid potential of the P-type transistor PM1 changes to high level 1, the resistor PD is enabled, a path between the output node PAD and the ground is conducted, and the potential of the output node PAD is pulled down to a low potential.
Since the potential of the PM1 needs a period of time from 0 to 1, the potential of the output node PAD cannot be quickly pulled down to a low level, which causes the fail-safe I/O interface circuit to transmit an error signal, and affects the normal operation of the system.
Referring to fig. 2, a voltage variation waveform diagram of a critical node of the fail-safe I/O interface circuit of fig. 1 is shown, wherein the critical node includes: the circuit comprises an input node I, an enable signal terminal OEN, a resistor PD and an output node PAD.
As shown in fig. 2, when the enable signal terminal OEN is at low level 0, the output node PAD follows the input node I; when t =50 μ s, the enable signal terminal OEN is switched from low level 0 to high level 1, and the voltage of the input node PAD is decreased to 0V when t =120 μ s.
However, in the time period of t =50 μ s to 120 μ s, the voltage of the output node PAD is not 0V, which may cause the fail-safe I/O interface circuit to transmit an error signal, and affect the normal operation of the system.
As can be seen from fig. 2, the level of the resistor PD is always high, but the pull-down capability of the resistor PD is weak, so that the resistor PD does not function when the enable signal terminal OEN is low 0, and the potential of the output node PAD does not decrease to low 0.
In order to solve the above problem, the fail-safe I/O interface circuit in the embodiment of the present invention is adopted, where the fail-safe I/O interface includes an enable signal terminal, a control unit, and an output unit, where the control unit is coupled to a power terminal and the control unit, and may generate a control signal based on a voltage at the power terminal and a voltage at an output node of the output unit, and output the control signal to the output unit, and the output unit may output a corresponding signal, instead of an error signal, when a signal at the enable signal terminal changes based on an enable signal at the enable signal terminal and the control signal, so that reliability of an output signal of the fail-safe I/O interface circuit may be improved, and thus safety and service life of a system circuit may be improved.
For a better understanding and appreciation of the embodiments of the invention by those skilled in the art, reference will now be made to the accompanying drawings, in which the principles of the invention are illustrated in detail, in conjunction with specific application circuits.
Referring to fig. 3, which is a schematic structural diagram of a fail-safe I/O interface circuit in the embodiment of the present invention, the fail-safe I/O interface circuit 30 includes: enable signal terminal 31, output unit 32, and control unit 33, wherein:
the enable signal terminal 31 is coupled to the output unit 32 and adapted to control the on/off of an input node and an output node of the output unit 32 based on an input enable signal;
specifically, when the level of the enable signal terminal 31 is low level 0, a path from the input node to the output node of the output unit 32 is turned on; when the level of the enable signal terminal 31 is high level 1, the path from the input node to the output node of the output unit 32 is disconnected, and thus, the connection and disconnection between the input node and the output node of the output unit 32 can be controlled by controlling the level of the input enable signal.
The output unit 32, respectively coupled to the power source terminal VDD, the enable signal terminal 31 and the control unit 33, and adapted to output the corresponding signals through the output node based on the enable signal and the control signal;
the control unit 33, coupled to a power supply terminal VDD and the output unit 32, is adapted to generate a control signal based on a voltage of the power supply terminal VDD and a voltage of an output node of the output unit 32, and output the control signal to the output unit 32, so that the output node outputs a corresponding signal when the signal of the enable signal terminal 31 changes;
in a specific implementation, when the level of the enable signal terminal 31 is at a high level 1, in order to make the voltage of the output node of the output unit 32 be 0V, a pull-down protection unit 34 may be coupled between the output unit 32 and ground, and the pull-down protection unit 34 is adapted to pull down the voltage of the output node of the output unit 32 to zero volts when the level of the enable signal terminal 31 is at a high level 1.
With the above-mentioned fail-safe I/O interface circuit, the power supply terminal VDD supplies power to the fail-safe I/O interface circuit 30, and the enable signal terminal 31 may receive an enable signal from the system on chip and disconnect a path between the input node and the output node of the output unit 32 when the enable signal is 1 (corresponding to a high level); when the enable signal is 0 (corresponding to a low level), a path between the input node and the output node of the output unit 32 is conducted, and the output unit 32 is coupled to the control unit 33 through the output node, the control unit 33 may generate a control signal according to the output node voltage and the voltage of the power supply terminal VDD coupled thereto, and output the control signal to the output unit 32, and the output unit may output a corresponding signal, instead of an error signal, under the action of the pull-down protection unit 34 when a signal of the enable signal terminal 31 changes, for example, when the level of the enable signal terminal 31 is switched from a low level to a high level, based on the enable signal of the enable signal terminal 31 and the control signal, so that the reliability of the output signal of the fail-safe I/O interface circuit may be improved, and the safety and the service life of the system circuit may be further improved.
For a better understanding and appreciation of the embodiments of the invention by those skilled in the art, reference will now be made to the accompanying drawings, in which the principles of the invention are illustrated in detail, in conjunction with specific application circuits.
In a specific implementation, the control unit may include: a control signal generating module and a well potential module, wherein the control module has a control terminal coupled to the power supply terminal, a first terminal coupled to the output node of the output unit, and a second terminal coupled to the first control terminal of the output unit;
the first control terminal of the well potential module is coupled to the power supply terminal, the first terminal thereof is coupled to the output node of the output unit, the second control terminal thereof is coupled to the output node of the output unit, the second terminal thereof is coupled to the power supply terminal, and the third terminal thereof is coupled to the first output terminal of the output unit and the third terminal of the control signal generating module, respectively.
By coupling a control terminal of a control signal generation module with the power supply terminal, a first terminal with an output node of the output unit, and a second terminal with a first control terminal of the output unit, the control signal generation module can output a control signal that is not affected by an enable signal terminal based on a voltage at the power supply terminal and a voltage at the output node of the output unit, so that the fail-safe I/O interface circuit can still normally operate in a failure state; and, by coupling the first control terminal of the well potential module with the power supply terminal, the first terminal with the output node of the output unit, the second control terminal with the output node of the output unit, the second terminal with the power supply terminal, and the third terminal with the first output terminal of the output unit and the third terminal of the control signal generation module, respectively, when the power supply terminal of the fail-safe I/O interface circuit is powered down, the paths of the well potential module and the output node of the output unit can be conducted, so that the voltage of the well potential module is the same as the voltage of the output node, and the current can be prevented from flowing backwards, thereby further improving the reliability and prolonging the service life of the fail-safe I/O interface circuit
In a specific example of the present invention, the control signal generating module includes: a first transistor and a second transistor, wherein: the gate of the first transistor is connected with the gate of the second transistor and serves as the control end of the control signal generation module, the source of the first transistor serves as the first end of the control signal generation module, the drain of the first transistor is connected with the drain of the second transistor and serves as the second end of the control signal generation module, and the substrate of the first transistor serves as the third end of the control signal generation module; the substrate and the source of the second transistor are connected and grounded.
The well potential module includes: a third transistor and a fourth transistor, wherein: a gate of the third transistor is used as a first control end of the well potential module, a source of the third transistor is used as a first end of the well potential module, and a drain and a substrate of the third transistor are connected with a drain and a substrate of the fourth transistor and are used as a third end of the well potential module; the grid electrode of the fourth transistor is used as the second control end of the well potential module, and the source electrode of the fourth transistor is used as the second end of the well potential module.
It should be noted that, in the embodiment of the present invention, the third transistor and the fourth transistor are both PMOS transistors, and the well potential module is an N-type well potential module.
In a specific implementation, the output unit may include: a first logic circuit module, a first switch module, a fifth transistor, a sixth transistor, and a first inverter, wherein: the first inverter is coupled between the enable signal terminal and the first logic circuit module;
the first logic circuit module has a first input terminal coupled to the input node of the output unit, a second input terminal coupled to the enable signal terminal through the first inverter, and an output terminal coupled to the input terminal of the first switch module;
a first control terminal of the first switch module is used as a first control terminal of the control unit, a second control terminal of the first switch module is coupled to the control terminal of the fifth transistor and the power supply terminal, and an output terminal of the first switch module is coupled to the control terminal of the sixth transistor;
a first terminal of the fifth transistor is coupled to the power supply terminal, a second terminal of the fifth transistor is coupled to the output node of the output unit, and a third terminal of the fifth transistor is used as a first output terminal of the output unit;
the sixth transistor has a control terminal coupled to the power terminal and the second control terminal of the first switch module, a first terminal coupled between the output terminal of the first switch module and the control terminal of the fifth transistor, and a second terminal coupled to ground.
In an embodiment of the present invention, the first control terminal of the control unit is adapted to input the control signal; and the first output end of the control unit is suitable for conducting the output node when the power supply end is powered off, so that the potential of the first output end is equal to the potential of the output node.
In a specific example of the present invention, the first logic circuit block includes: the first input end of the NAND gate is used as the first input end of the first logic circuit module, and the second input end of the NAND gate is used as the second input end of the first logic circuit module; the second inverter is positioned between the NAND gate and the third inverter; and the output end of the third inverter is used as the output end of the first logic circuit module.
The first switch module comprises a transmission gate, the transmission gate comprises a P-type transistor and an N-type transistor, the P-type transistor and the N-type transistor are connected in parallel, and the grid electrode of the P-type transistor in the transmission gate is used as a first control end of the first switch module and is suitable for transmitting a high-level signal; and the grid electrode of the N-type transistor in the transmission gate is used as a second control end of the first switch module and is suitable for transmitting a low-level signal.
The fifth transistor is a PMOS transistor, a gate of the fifth PMOS is coupled to the output terminal of the second switch module, a source of the fifth PMOS is coupled to the power supply terminal, a drain of the fifth PMOS is coupled to the output node, and a substrate of the fifth PMOS serves as the first output terminal of the output unit.
The sixth transistor is a PMOS transistor, a gate of the sixth PMOS transistor is coupled to the power supply terminal and the second control terminal of the first switch module, a source of the sixth PMOS transistor is coupled between the output terminal of the first switch module and the gate of the fifth transistor, and a drain of the sixth PMOS transistor is coupled to the pull-down protection unit.
In some embodiments of the present invention, the output unit may further include a second logic circuit block, a second switch block, and a seventh transistor, wherein: a first input terminal of the second logic circuit module is coupled to the enable signal terminal, a second input terminal of the second logic circuit module is coupled to the input node, and an output terminal of the second logic circuit module is coupled to an input terminal of the second switch module; a first control terminal of the second switch module is coupled to ground, a second control terminal of the second switch module is coupled to the power supply terminal, and an output terminal of the second switch module is coupled to a control terminal of the seventh transistor; a first terminal of the seventh transistor is coupled to a drain of the fifth transistor, and a second terminal of the seventh transistor is coupled to the ground.
In an embodiment of the present invention, the first logic circuit, the first switch module, the fifth transistor, the sixth transistor, and the first inverter are adapted to transmit an input signal to an output node PAD of the output unit when a level of the input signal at an input node I of the output unit is a high level 1; the second logic circuit module, the second switch module and the seventh transistor are adapted to transmit an input signal to an output node PAD of the output unit when a level of the input signal at an input node I of the output unit is a low level 0.
In a specific implementation, when the level of the enable signal terminal of the fail-safe I/O interface circuit is at a high level, to make the voltage of the output node of the output unit zero, a pull-down protection unit may be coupled between the output node of the output unit and ground, and therefore, the fail-safe I/O interface circuit may further include a pull-down protection unit coupled between the output node of the output unit and ground and adapted to pull down the voltage of the output node of the output unit to zero volts when the level of the enable signal terminal of the fail-safe I/O interface circuit is at a high level.
Specifically, referring to a schematic circuit structure diagram of a fail-safe I/O interface circuit in the embodiment of the present invention shown in fig. 4, the fail-safe I/O interface circuit 40 includes an enable signal terminal OEN, a control unit 41, an output unit 42, and a pull-down protection unit 43, where:
the control unit 41 is respectively coupled to the power source terminal VDD and the output unit 42, and may include a control signal generating module 411 and a well potential module 412;
the output unit 42 is coupled to the power source terminal VDD, the enable signal terminal OEN and the control unit 41, respectively, and the output unit 42 may include a first logic circuit module 421, a first switch module TG41, a fifth PMOS transistor PM45 and a sixth PMOS transistor PM46;
the pull-down protection unit 43 is coupled between an output node PAD of the output unit 42 and ground.
In the embodiment of the present invention, the control terminal of the control signal generating module 411 is coupled to the power terminal VDD, a first terminal thereof is coupled to the output node PAD of the output unit 42, and a second terminal thereof is coupled to the first control terminal of the output unit 42;
the well potential module 412 has a first control terminal coupled to the power source terminal VDD, a first terminal coupled to the output node PAD of the output unit 42, a second control terminal coupled to the output node PAD of the output unit 42, a second terminal coupled to the power source terminal VDD, and a third terminal coupled to the first output terminal of the output unit 42 and the third terminal of the control signal generating module 411, respectively.
As a specific example, the control signal generating module 411 may specifically include a first PMOS transistor PM41 and a second NMOS transistor NM42, and the well potential generating module 412 may specifically include a third PMOS transistor PM43 and a fourth PMOS transistor PM44, where:
the gate of the first PMOS transistor PM41 is connected to the gate of the second NMOS transistor NM42 and coupled to the power supply terminal VDD, the source of the first PMOS transistor PM41 is coupled to the power supply terminal VDD, the drain of the first PMOS transistor PM41 is connected to the drain of the second NMOS transistor NM42 and coupled to the first control terminal of the first switch module TG41 of the output unit 42, the substrate of the first PMOS transistor PM41 is coupled to the drains of the third PMOS transistor PM43 and the fourth PMOS transistor PM44, respectively, and the substrate of the second NMOS transistor NM42 is connected to the source and grounded.
The gate of the third PMOS transistor PM43 is coupled to the power supply terminal VDD, the source of the third PMOS transistor PM43 is coupled to the output node PAD of the output unit 42, the drain and the substrate of the third PMOS transistor PM43 are connected to the drain and the substrate of the fourth PMOS transistor PM44 and are coupled to the first output terminal of the output unit 42, the gate of the fourth PMOS transistor PM44 is coupled to the output node PAD of the output unit 42, and the source of the fourth PMOS transistor PM44 is coupled to the power supply terminal VDD.
In the embodiment of the present invention, a first input terminal of the first logic circuit module 421 is coupled to the input node I of the output unit 42, a second input terminal of the first logic circuit module 421 is coupled to the enable signal terminal OEN through the first inverter P1, and an output terminal of the first logic circuit module 421 is coupled to an input terminal of the first switch module TG 41; a first control terminal of the first switch module TG41 serves as a first control terminal of the control unit 42, a second control terminal of the first switch module TG41 is coupled to the gate of the sixth PMOS transistor PM46 and the power supply terminal VDD, and an output terminal of the first switch module TG41 is coupled to the gate of the fifth PMOS transistor PM 45; a source of the fifth PMOS transistor PM45 is coupled to the power supply terminal VDD, a drain of the fifth PMOS transistor PM45 is coupled to the output node PAD of the unit 42 and the source of the seventh NMOS transistor NM47, respectively, and a substrate of the fifth PMOS transistor PM45 serves as a first output terminal of the output unit 42; a gate of the sixth PMOS transistor PM46 is coupled to the power supply terminal VDD and the second control terminal of the first switch module TG41, a source of the sixth PMOS transistor PM46 is coupled between the output terminal of the first switch module TG41 and the gate of the fifth PMOS transistor PM45, and a drain of the sixth PMOS transistor PM46 is coupled to the pull-down protection unit 43, wherein the first control terminal of the control unit 42 is adapted to input the control signal P _ PASS; the first output terminal of the control unit 42 is adapted to turn on the output node PAD when the power source terminal VDD is powered down, so that the potential of the first output terminal is equal to the potential of the output node PAD.
As a specific example, the first logic circuit module 421 includes: a NAND gate NAND, a second inverter P2 and a third inverter P3 connected in sequence, wherein a first input end of the NAND gate NAND is used as a first input end of the first logic circuit module 421, and a second input end of the NAND gate NAND is used as a second input end of the first logic circuit module 421; the second inverter P2 is located between the NAND gate NAND and the third inverter P3; the output terminal of the third inverter P3 is used as the output terminal of the first logic circuit module 421.
The first switch module TG41 may specifically be a transmission gate, where the transmission gate includes a P-type transistor and an N-type transistor, and the P-type transistor and the N-type transistor are connected in parallel, where a gate of the P-type transistor in the transmission gate is used as a first control terminal of the first switch module TG41, and a gate of the N-type transistor in the transmission gate is used as a second control terminal of the first switch module TG 41.
In a specific implementation, the output unit 42 may further include a second logic circuit module 422, a second switch module TG42 and a seventh NMOS transistor NM47, wherein a first input terminal of the second logic circuit module 422 is coupled to the enable signal terminal OEN, a second input terminal of the second logic circuit module 422 is coupled to the input node I, and an output terminal of the second logic circuit module 422 is coupled to an input terminal of the fourth switch module TG 42; a first control terminal of the second switch module TG42 is coupled to ground, a second control terminal of the second switch module TG42 is coupled to the power supply terminal VDD, and an output terminal of the second switch module TG42 is coupled to a gate of the seventh NMOS transistor NM 47; the source of the seventh NMOS transistor NM47 is coupled to the second end of the fifth PMOS transistor PM45, and the drain of the seventh NMOS transistor NM47 is coupled to the ground.
As a specific example, the second logic circuit block may specifically include a nor gate XNOR, a fourth inverter P4 and a fifth inverter P5 connected in sequence, wherein a first input terminal of the nor gate XNOR is coupled to the enable signal terminal OEN, and a second input terminal thereof is coupled to the input node I; the fourth inverter P4 is located between the nor gate XNOR and a fifth inverter P5, and an output terminal of the fifth inverter P5 is coupled to an input terminal of the second switch module TG 42.
The second switch module TG42 may be a transmission gate, and the transmission gate includes a P-type transistor and an N-type transistor, and the P-type transistor and the N-type transistor are connected in parallel, wherein a gate of the P-type transistor is used as a first control terminal of the fourth switch module TG42 and is coupled to ground, and a gate of the N-type transistor is used as a second control terminal of the fourth switch module TG42 and is coupled to the power supply terminal VDD.
In the embodiment of the present invention, the voltage of the power supply terminal VDD has the power supply voltage VDDIO when the fail-safe I/O interface circuit 40 is in the normal operation mode, and is configured to be 0V when the interface circuit is in the fail-safe mode.
The first example is: when the fail-safe I/O interface circuit 40 is in the normal operating mode, the voltage of the power supply terminal VDD is VDDIO.
Specifically, when the fail-safe I/O interface circuit 40 is in the normal operation mode, the voltage of the power supply terminal VDD is VDDIO, since the gate of the second NMOS transistor NM42 is coupled to the power supply terminal VDD, the second NMOS transistor NM42 is turned on, and the voltage V of the control signal P _ PASS output by the second terminal of the control signal generating module 411 is V P_PASS ＝0V。
The control signal P _ PASS generated by the control generation module 41 is input to a first control end (gate of a PMOS transistor) of the first switch module TG41, a second control end (gate of an NMOS transistor) of the first switch module TG41 is coupled to the power supply end VDD, so that a level of the first control end of the first switch module TG41 is a low level, a level of the second control end thereof is a high level, the first switch module TG41 is completely turned on, at this time, a voltage level of the fifth PMOS transistor PM45 is controlled by the signal PG output by the first switch module TG41, the power supply end VDD is directly added to the gate of the sixth PMOS transistor PM46, and the sixth PMOS transistor PM46 is turned off.
Since the source of the fourth PMOS transistor PM44 is coupled to the power source terminal and the gate thereof is coupled to the output node PAD of the output unit 42, the source voltage of the fourth PMOS transistor PM44 is greater than the gate voltage thereof, and the fourth PMOS transistor PM44 makes the N _ WELL of the output unit 42 be a high level 1.
The second example is: when the fail-safe I/O interface circuit 40 is in the fail-safe mode, the voltage of the power supply terminal VDD is 0V.
Specifically, when the fail-safe I/O interface circuit 40 is in fail-safe mode, the voltage of the power terminal VDD is 0V, the output node PAD is coupled to the external circuit, and the potential of the output node PAD is high level 1. The output node PAD is coupled to the source of the first PMOS transistor PM41 due to the first PMOS transistor PM41 and the power supply terminal VDD, and the source of the first PMOS transistor PM41 is electrically connectedThe voltage is greater than the gate voltage thereof, the first PMOS transistor PM41 is turned on, and the voltage V of the control signal P _ PASS output by the second end of the control signal generating module 411 P_PASS ＝V PAD 。
The control signal P _ PASS generated by the control generation module 41 is input to a first control end (gate of a PMOS transistor) of the first switch module TG41, a second control end (gate of an NMOS transistor) of the first switch module TG41 is coupled to the power supply end VDD, so that the level of the first control end of the first switch module TG41 is high, the level of the second control end is low, the first switch module TG41 is completely turned off, the source of the fifth PMOS transistor PM45 is coupled to the power supply end VDD, the fifth PMOS transistor PM45 is turned off, the power supply end VDD is directly added to the gate of the sixth PMOS transistor PM46, the source voltage of the sixth PMOS transistor PM46 is greater than the gate voltage thereof, the sixth PMOS transistor PM46 is turned on, and the PG point potential is V PAD 。
Since the gate of the third PMOS transistor PM43 is coupled to the power source terminal VDD and the output node PAD is coupled to the source of the third PMOS transistor PM43, the source voltage of the third PMOS transistor PM43 is greater than the gate voltage thereof, and the third PMOS transistor PM43 is turned on, so that V is N_WELL ＝V PAD Thereby blocking external circuitry from leaking internally to the failsafe I/O interface circuit 40 through the output node PAD.
The third example: when the failsafe I/O interface circuit 40 is in a normal operating mode and the level of the enable signal terminal is switched from a low level to a high level (0 to 1), the voltage of the power supply terminal VDD is VDDIO.
Specifically, when the failsafe I/O interface circuit 40 is in the normal operation mode and the level of the enable signal terminal is switched from the low level 0 to the high level 1, the voltage of the power terminal VDD is VDDIO, since the gate of the second NMOS transistor NM42 is coupled thereto, the second NMOS transistor NM42 is turned on, and the voltage V of the control signal P _ PASS output by the second terminal of the control signal generating module 411 is V P_PASS =0V. The control signal P _ PASS generated by the control generation module 41 is input to a first control end (of a PMOS transistor) of the first switch module TG41A gate), the second control terminal (gate of an NMOS transistor) of the first switch module TG41 is coupled to the power supply terminal VDD, so that the level of the first control terminal of the first switch module TG is a low level, the level of the second control terminal of the first switch module TG is a high level, the first switch module TG41 is completely turned on, at this time, the voltage level of the fifth PMOS transistor PM45 is controlled by the signal PG output by the first switch module TG41, the power supply terminal VDD is directly applied to the gate of the sixth PMOS transistor PM46, and the sixth PMOS transistor PM46 is turned off.
Since the level of the enable signal terminal OEN is switched from 0 to 1, the level is changed to low level 0 through the first inverter P1, the level output to the first switch module TG41 is changed to high level 1 through the input node I and the first logic circuit module 421, the level output to the first switch module TG41 is completely turned on, and the first switch module TG41 does not change the polarity of the signal, the level output by the first switch module TG41 is high level 1, and is added to the gate of the fifth PMOS transistor PM45, so that the level of the gate of the fifth PMOS transistor PM45 is high level, the fifth PMOS transistor PM45 is turned off, the pull-down protection unit 43 forms a conductive path with the output node PAD of the output unit 42, and the output node PAD of the output unit 42 is coupled to ground, so that the potential of the output node PAD can be quickly lowered to low level 0.
Since the fourth PMOS transistor PM44 is coupled to the output node PAD, and the source thereof is coupled to the power source terminal VDD, the gate voltage of the fourth PMOS transistor PM44 is smaller than the source voltage thereof, and the fourth PMOS transistor PM44 is turned on, so that the voltage of N _ WELL of the output unit 42 is the power source voltage VDDIO.
Referring to fig. 5, a waveform diagram of voltage variation of a critical node of a fail-safe I/O interface circuit in a third example of the embodiment of the present invention is shown, wherein the critical node of the fail-safe I/O interface circuit includes: the protection circuit comprises an enabling signal terminal OEN, an input node I, a pull-down protection unit PD and an output node PAD.
As can be seen from fig. 5, when the level of the enable signal terminal OEN is low level 0, the voltage of the output node PAD follows the voltage of the input node I, that is, when the level of the input node I is low level 0, the level of the output node PAD is also low level 0; when the level of the enable signal terminal OEN is switched from low level 0 to high level 1 at t =50 μ s, the level of the input node I still maintains the original level state, and the level of the output node PAD no longer follows the level of the input node I, and at t =52 μ s, the voltage level thereof drops to zero volt.
It should be noted that, as can be seen from fig. 5, the level of the pull-down protection unit PD is always at a high level, but the pull-down protection unit PD has a weak pull-down capability, so that when the enable signal terminal OEN is at a low level 0, the pull-down protection unit PD does not function, and the potential of the output node PAD does not drop to the low level 0.
As can be seen from fig. 5 and fig. 2, when the level of the enable signal terminal is switched from low level to high level, the time for the output node voltage of the output unit to drop to zero volt is shortened by using the fail-safe I/O interface circuit in the embodiment of the present invention, so as to avoid transmitting an error signal when the level of the enable signal terminal of the fail-safe I/O interface circuit is high level.
An embodiment of the present invention further provides a system on chip, as shown in fig. 6, where the system on chip 60 may include: a processor 61 and a fail-safe I/O interface circuit 62, wherein:
the processor 61, coupled to a power supply terminal VDD, an enable signal terminal 621 of the fail-safe I/O interface circuit 62 and an input node of the output unit 622, is adapted to input an enable signal ENB to the fail-safe I/O interface circuit 62 through the enable signal terminal 621 and to input a clock signal or a level signal to the input node I of the output unit 622.
The fail-safe I/O interface circuit 62 may include an enable signal terminal 621, an output unit 622, and a control unit 623, where each circuit unit of the fail-safe I/O interface circuit 62 may adopt the circuit structure shown in the foregoing embodiment, and specifically, refer to the fail-safe I/O interface circuit shown in the foregoing embodiment, which is not described herein again.
Specifically, the processor 61 in the system-on-chip 60 may input the enable signal ENB to the fail-safe I/O interface circuit 62 through an enable signal terminal 621, the output unit 622 of the fail-safe I/O interface circuit 62 may turn on or off a path between the input node I and the output node PAD of the output unit 622 according to the input enable signal ENB, and input the state information of the output node PAD to the control unit 623, the control unit 623 may output a corresponding control signal according to the voltage of the power terminal VDD and the voltage of the output node PAD, and output the control signal to the output unit 622, and the output unit 622 may output a corresponding signal according to the level of the input enable signal ENB and the control signal. For example, when the level of the input enable signal is a high level, the path between the input node I and the output node PAD is disconnected, the control unit outputs a control signal with a voltage value of 0V to the output unit 622, and the output unit 622 outputs a corresponding signal according to the control signal; when the level of the input enable signal is a low level, the paths of the input node I and the output node PAD are turned on, the system-on-chip 60 may input a clock signal or a level signal to the fail-safe I/O interface circuit 62 through the output node I of the output unit 622, and the fail-safe I/O interface circuit 62 may perform corresponding processing according to the input clock signal or level signal.
Although the embodiments of the present invention have been disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (12)

1. A fail-safe I/O interface circuit, comprising: enable signal terminal, control unit and output unit, wherein:
the enable signal terminal is coupled with the output unit and is suitable for controlling the on-off of an input node and an output node of the output unit based on an input enable signal;
the control unit is coupled with a power supply end and the output unit, and is suitable for generating a control signal based on the voltage of the power supply end and the voltage of an output node of the output unit and outputting the control signal to the output unit, so that the output node outputs a corresponding signal when the signal of the enable signal end changes;
the output unit is respectively coupled with the power end, the enable signal end and the control unit, and is adapted to output the corresponding signal through the output node based on the enable signal and the control signal.
2. The fail-safe I/O interface circuit of claim 1, wherein the output unit comprises: the first control end is suitable for inputting the control signal; and the first output end is suitable for conducting the output node when the power supply end is powered down, so that the potential of the first output end is equal to the potential of the output node.
3. The fail-safe I/O interface circuit of claim 2, wherein the control unit comprises:
a control signal generating module having a control terminal coupled to the power terminal, a first terminal coupled to the output node of the output unit, and a second terminal coupled to the first control terminal of the output unit;
a first control terminal of the well potential module is coupled to the power supply terminal, a first terminal of the well potential module is coupled to the output node of the output unit, a second control terminal of the well potential module is coupled to the output node of the output unit, a second terminal of the well potential module is coupled to the power supply terminal, and a third terminal of the well potential module is coupled to the first output terminal of the output unit and the third terminal of the control signal generating module, respectively.
4. The fail-safe I/O interface circuit of claim 3, wherein the control signal generation module comprises a first transistor and a second transistor, wherein:
the gate of the first transistor is connected to the gate of the second transistor and serves as a control terminal of the control signal generation module, the source of the first transistor serves as a first terminal of the control signal generation module, the drain of the first transistor is connected to the drain of the second transistor and serves as a second terminal of the control signal generation module, and the substrate of the first transistor serves as a third terminal of the control signal generation module;
and the substrate of the second transistor is connected with the source electrode and grounded.
5. The fail-safe I/O interface circuit of claim 3, wherein the well potential module comprises a third transistor and a fourth transistor, wherein:
the grid electrode of the third transistor is used as a first control end of the well potential module, the source electrode of the third transistor is used as a first end of the well potential module, and the drain electrode and the substrate of the third transistor are connected with the drain electrode and the substrate of the fourth transistor and are used as a third end of the well potential module;
the gate of the fourth transistor is used as the second control end of the well potential module, and the source of the fourth transistor is used as the second end of the well potential module.
6. The fail-safe I/O interface circuit of claim 5, wherein the third transistor and the fourth transistor are both PMOS transistors and the well potential module is an N-type well potential module.
7. The fail-safe I/O interface circuit of claim 2, wherein the output unit further comprises: the first logic circuit module, the first switch module, the fifth transistor, the sixth transistor and the first inverter, wherein:
the first inverter is coupled between the enable signal end and the first logic circuit module;
the first logic circuit module has a first input terminal coupled to the input node of the output unit, a second input terminal coupled to the enable signal terminal through the first inverter, and an output terminal coupled to the input terminal of the first switch module;
a first control terminal of the first switch module is used as a first control terminal of the control unit, a second control terminal of the first switch module is coupled to the control terminal of the fifth transistor and the power supply terminal, and an output terminal of the first switch module is coupled to the control terminal of the sixth transistor;
a first terminal of the fifth transistor is coupled to the power supply terminal, a second terminal of the fifth transistor is coupled to the output node of the output unit, and a third terminal of the fifth transistor is used as a first output terminal of the output unit;
the sixth transistor has a control terminal coupled to the power terminal and the second control terminal of the first switch module, a first terminal coupled between the output terminal of the first switch module and the control terminal of the fifth transistor, and a second terminal coupled to ground.
8. The fail-safe I/O interface circuit of claim 7, wherein the first logic circuit block comprises a nand gate, a second inverter, and a third inverter connected in series, wherein:
the first input end of the nand gate is used as the first input end of the first logic circuit module, and the second input end of the nand gate is used as the second input end of the first logic circuit module;
the second inverter is positioned between the NAND gate and the third inverter;
and the output end of the third phase inverter is used as the output end of the first logic circuit module.
9. The fail-safe I/O interface circuit of claim 7, wherein the first switch module comprises a transmission gate comprising a P-type transistor and an N-type transistor connected in parallel, wherein:
the grid electrode of the P-type transistor in the transmission gate is used as a first control end of the first switch module and is suitable for transmitting a high-level signal;
and the grid electrode of the N-type transistor in the transmission gate is used as a second control end of the first switch module and is suitable for transmitting a low-level signal.
10. The fail-safe I/O interface circuit of claim 7, wherein the output unit further comprises: a second logic circuit module, a second switch module, and a seventh transistor, wherein:
a first input terminal of the second logic circuit module is coupled to the enable signal terminal, a second input terminal thereof is coupled to the input node, and an output terminal thereof is coupled to an input terminal of the second switch module;
the first control terminal of the second switch module is coupled to ground, the second control terminal of the second switch module is coupled to the power supply terminal, and the output terminal of the second switch module is coupled to the control terminal of the seventh transistor;
the first terminal of the seventh transistor is coupled to the second terminal of the second switch module, and the second terminal of the seventh transistor is coupled to the ground.
11. The fail-safe I/O interface circuit of any one of claims 1 to 10, further comprising: and the pull-down protection unit is coupled between the output node of the output unit and the ground and is suitable for pulling down the voltage of the output node of the output unit to zero volt when the level of the enable signal end is high level.
12. A system on a chip, comprising:
the fail safe I/O interface circuit of any of claims 1 to 11, the fault safety I/O interface circuit comprises an enabling signal end, a control unit and an output unit;
a processor coupled to a power source terminal, an enable signal terminal of the fail-safe I/O interface circuit, and an input node of the output unit, and adapted to input an enable signal to the fail-safe I/O interface circuit through the enable signal terminal, and to input a clock signal or a level signal to the input node of the output unit.
CN202110350450.3A 2021-03-31 2021-03-31 Fail-safe I/O interface circuit and system on chip Pending CN115149941A (en)

Priority Applications (1)

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CN202110350450.3A CN115149941A (en) 2021-03-31 2021-03-31 Fail-safe I/O interface circuit and system on chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110350450.3A CN115149941A (en) 2021-03-31 2021-03-31 Fail-safe I/O interface circuit and system on chip

Publications (1)

Publication Number Publication Date
CN115149941A true CN115149941A (en) 2022-10-04

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Country Link
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