CN206547080U - A kind of clock generation module - Google Patents
A kind of clock generation module Download PDFInfo
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- CN206547080U CN206547080U CN201720091856.3U CN201720091856U CN206547080U CN 206547080 U CN206547080 U CN 206547080U CN 201720091856 U CN201720091856 U CN 201720091856U CN 206547080 U CN206547080 U CN 206547080U
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Abstract
The utility model discloses a kind of clock generation module, including：Energy Saving Control sub-circuit (101), bias current generation sub-circuit (102), ring oscillator (20), Energy Saving Control signal generation sub-circuit (301), duty cycle adjustment sub-circuit (302) and clock signal shaping sub-circuit (303)；Bias current generation sub-circuit (102) is used to produce bias current based on bias voltage；Ring oscillator (20) is used for the sinusoidal signal (S1) that frequency-adjustable is produced based on bias current；Duty cycle adjustment sub-circuit (302) is used for the dutycycle for adjusting sinusoidal signal (S1), to obtain sinusoidal signal (S2)；Clock signal shaping sub-circuit (303) is used to carry out shaping to sinusoidal signal (S2), to obtain clock signal (CLK_OUT)；Energy Saving Control signal generation sub-circuit (301) is used to produce Energy Saving Control signal (UN_CLK)；Energy Saving Control sub-circuit (101) is used to carry out Energy Saving Control management to biasing circuit (10) based on Energy Saving Control signal (UN_CLK).
Description
Technical field
The utility model is related to simulation clock circuit field, more particularly to a kind of clock generation module.
Background technology
With the fast development of integrated circuit, also more and more extensively, clock is this kind of chip for the application of digital-analog mix-mode chip
Essential part.Simultaneously as the variation of handled signal, the difference of process demand, also have not to arithmetic speed
Same requirement.This needs clock circuit to possess the function of exporting multiple clock signal, but clock generation circuit exists at present
When multiple clock signal output is realized in circuit design, complex circuit designs, and its circuit power consumption had not been considered.
Utility model content
The utility model is for present in prior art, clock generation circuit realizes that multiple clock is believed in circuit design
Number output when, the big technical problem of complex circuit designs, circuit power consumption, can be in not shadow there is provided a kind of clock generation module
While ringing normal work, realize multiple clock signal output, the energy expenditure of circuit is reduced.
The utility model provides a kind of clock generation module, including：The biasing circuit that is sequentially connected, ring oscillator and
Enable control circuit；The biasing circuit includes：Energy Saving Control sub-circuit and bias current generation sub-circuit；It is described to enable control
Circuit includes：Energy Saving Control signal generation sub-circuit, duty cycle adjustment sub-circuit and clock signal shaping sub-circuit；
The bias current generation sub-circuit is used in the case where enabling the control of signal produce bias current based on bias voltage；
The ring oscillator is used for the first sinusoidal signal that frequency-adjustable is produced based on the bias current；
The duty cycle adjustment sub-circuit is used for the duty that first sinusoidal signal is adjusted in the case where enabling the control of signal
Than to obtain the second sinusoidal signal；
The clock signal shaping sub-circuit is used to carry out shaping to second sinusoidal signal, to obtain clock signal；
The Energy Saving Control signal generation sub-circuit is used to produce Energy Saving Control signal based on the enable signal；
The Energy Saving Control sub-circuit is used to carry out Energy Saving Control to the biasing circuit based on the Energy Saving Control signal
Management.
Optionally, the Energy Saving Control sub-circuit includes：First PMOS, the second PMOS, the 3rd PMOS, the 4th
PMOS and the 5th PMOS；
The Energy Saving Control signal output part of the grid of first PMOS and the Energy Saving Control signal generation sub-circuit
Connection, for inputting Energy Saving Control signal；The source electrode of first PMOS is connected with power voltage terminal, for input power electricity
Pressure；The drain electrode of first PMOS is connected with the grid of the 4th PMOS, drain electrode；
The grid of second PMOS is connected and is grounded with the grid of the 3rd PMOS；Second PMOS
Source electrode and the source electrode of the 3rd PMOS are connected with power voltage terminal, for input supply voltage；Second PMOS
Drain electrode and the 3rd PMOS the source electrode and the source electrode of the 5th PMOS respectively with the 4th PMOS of draining
It is connected；
The grid of 4th PMOS is connected with the grid of the 5th PMOS；The drain electrode of 4th PMOS with
The drain electrode of 5th PMOS is connected with the bias current generation sub-circuit.
Optionally, the bias current generation sub-circuit includes：First NMOS tube, the second NMOS tube, the 3rd NMOS tube and
4th NMOS tube；
The grid of the grid of first NMOS tube, drain electrode with second NMOS tube is connected, and with biased electrical pressure side
It is connected, for input offset voltage；The drain electrode of second NMOS tube is connected with the Energy Saving Control sub-circuit；Described first
The source electrode of NMOS tube is connected and is grounded with the source electrode of second NMOS tube；
The grid of 3rd NMOS tube is connected with the grid of the 4th NMOS tube, and is connected with enabling signal end, uses
Signal is enabled in input；The drain electrode of 3rd NMOS tube is connected with biased electrical pressure side, for input offset voltage；Described 4th
The drain electrode of NMOS tube is connected with the Energy Saving Control sub-circuit；The source electrode of 3rd NMOS tube and the source of the 4th NMOS tube
Extremely it is connected and is grounded.
Optionally, the ring oscillator includes：The multiple CMOS inverters being connected with the biasing circuit, and be used for
Connect multiple nodes of the multiple CMOS inverter.
Optionally, the ring oscillator includes：
First CMOS inverter, the second CMOS inverter, the 3rd CMOS inverter, the 4th CMOS inverter, the 5th CMOS
Phase inverter, the 6th CMOS inverter, the 7th CMOS inverter, the 8th CMOS inverter；And for connecting described first to
First node, Section Point, the 3rd node and the fourth node of eight CMOS inverters；
Wherein, first CMOS inverter and the second CMOS inverter reverse parallel connection, and the first CMOS is anti-
The input and output end of phase device are connected with the first node and the Section Point respectively；6th CMOS inverter and
The 7th CMOS inverter reverse parallel connection, and the 6th CMOS inverter input and output end respectively with the described 4th
Node and the 3rd node connection；
The input and output end of 3rd CMOS inverter connect with the first node and the 3rd node respectively
Connect；The input and output end of 4th CMOS inverter are connected with the 3rd node and the Section Point respectively；Institute
The input and output end for stating the 5th CMOS inverter are connected with the Section Point and the fourth node respectively；Described 8th
The input and output end of CMOS inverter are connected with the fourth node and the first node respectively.
Optionally, the first node is by the first capacity earth, and the Section Point is described by the second capacity earth
3rd node is by the 3rd capacity earth, and the fourth node passes through the 4th capacity earth.
Optionally, the first CMOS inverter is made up of the 6th PMOS and the 5th NMOS tube；Second CMOS inverter is by
Seven PMOSs and the 6th NMOS tube are constituted；3rd CMOS inverter is made up of the 8th PMOS and the 7th NMOS tube；4th CMOS
Phase inverter is made up of the 9th PMOS and the 8th NMOS tube；5th CMOS inverter is by the tenth PMOS and the 9th NMOS tube structure
Into；6th CMOS inverter is made up of the 11st PMOS and the tenth NMOS tube；7th CMOS inverter is by the 12nd PMOS
Constituted with the 11st NMOS tube；8th CMOS inverter is made up of the 13rd PMOS and the 12nd NMOS tube.
Optionally, the Energy Saving Control signal generation sub-circuit includes：14th PMOS and the 13rd NMOS tube；
The grid of 14th PMOS is connected with the grid of the 13rd NMOS tube, and with enabling signal end phase
Even, signal is enabled for inputting；The source electrode of 14th PMOS is connected with power voltage terminal, for input supply voltage；
The source ground of 13rd NMOS tube；The drain electrode of 14th PMOS and the drain electrode phase of the 13rd NMOS tube
Connect, and be connected to Energy Saving Control signal output part, for exporting Energy Saving Control signal.
Optionally, the duty cycle adjustment sub-circuit includes：15th PMOS, the 16th PMOS, the 14th NMOS
Pipe and the 15th NMOS tube；
The grid of 15th PMOS is connected with the grid of the 15th NMOS tube, and is connected to Energy Saving Control letter
Number output end, for inputting Energy Saving Control signal；The source electrode of 15th PMOS is connected with power voltage terminal, for inputting
Supply voltage；The drain electrode and the 14th NMOS tube that drain respectively with the 16th PMOS of 15th PMOS
Drain electrode be connected；The drain electrode of 15th NMOS tube is connected with the source electrode of 14 NMOS tube；15th NMOS tube
Source ground；
The grid of 14th NMOS tube is connected with the grid of the 16th PMOS, and is connected to the annular and shakes
Swing the output end of device.
Optionally, the clock signal shaping sub-circuit includes：9th CMOS inverter and the tenth CMOS inverter；
9th CMOS inverter is made up of the 17th PMOS and the 16th NMOS tube, the tenth CMOS inverter
It is made up of the 18th PMOS and the 17th NMOS tube；
The grid of 17th PMOS is connected with the grid of the 16th NMOS tube, and is connected to the dutycycle
Adjust the output end of sub-circuit；The source electrode of 17th PMOS is connected with power voltage terminal, for input supply voltage；Institute
The drain electrode for stating the 17th PMOS is connected with the drain electrode of the 16th NMOS tube, and is connected to the tenth CMOS inverter；
The source ground of 16th NMOS tube；
The grid of 18th PMOS is connected with the grid of the 17th NMOS tube, and is connected to the described 9th
CMOS inverter；The source electrode of 18th PMOS is connected with power voltage terminal, for input supply voltage；Described 17th
The source ground of NMOS tube；The drain electrode of 18th PMOS is connected with the drain electrode of the 17th NMOS tube, and is connected to
Clock signal output terminal, for exporting clock signal.
The one or more technical schemes provided in the utility model, have at least the following technical effects or advantages：
Due in the utility model, clock generation module, including：The biasing circuit that is sequentially connected, ring oscillator and
Enable control circuit；Wherein, the biasing circuit includes：Energy Saving Control sub-circuit and bias current generation sub-circuit；It is described to make
Circuit can be controlled to include：Energy Saving Control signal generation sub-circuit, duty cycle adjustment sub-circuit and clock signal shaping sub-circuit.Enter
One step, the bias current generation sub-circuit is used in the case where enabling the control of signal produce bias current based on bias voltage；Institute
State the first sinusoidal signal that ring oscillator is used to produce frequency-adjustable based on the bias current；The duty cycle adjustment electricity
Road is used for the dutycycle that first sinusoidal signal is adjusted in the case where enabling the control of signal, to obtain the second sinusoidal signal；It is described
Clock signal shaping sub-circuit is used to carry out shaping to second sinusoidal signal, to obtain clock signal.It is pointed out that
The Energy Saving Control signal generation sub-circuit is used to produce Energy Saving Control signal based on the enable signal；Energy Saving Control
Circuit is used to carry out Energy Saving Control management to the biasing circuit based on the Energy Saving Control signal.Efficiently solve existing skill
When clock generation circuit realizes multiple clock signal output in circuit design in art, complex circuit designs, circuit power consumption are big
Technical problem.The energy expenditure of circuit can be reduced while not influenceing normal work, realizing multiple clock signal output.
Brief description of the drawings
, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art
Or the accompanying drawing used required in description of the prior art is briefly described, it should be apparent that, drawings in the following description are only
It is embodiment of the present utility model, for those of ordinary skill in the art, on the premise of not paying creative work, also
Other accompanying drawings can be obtained according to the accompanying drawing of offer.
A kind of structural representation for clock generation module that Fig. 1 provides for the utility model embodiment；
The circuit theory diagrams of biasing circuit in the clock generation module that Fig. 2 provides for the utility model embodiment；
A kind of circuit theory of annular oscillation circuit in the clock generation module that Fig. 3 A provide for the utility model embodiment
Figure；
The circuit of another annular oscillation circuit is former in the clock generation module that Fig. 3 B provide for the utility model embodiment
Reason figure；
The circuit theory diagrams of control circuit are enabled in the clock generation module that Fig. 4 provides for the utility model embodiment.
Embodiment
The utility model embodiment is solved present in prior art, clock by providing a kind of clock generation module
When generation circuit realizes multiple clock signal output in circuit design, the big technical problem of complex circuit designs, circuit power consumption,
The energy expenditure of circuit can be reduced while not influenceing normal work, realizing multiple clock signal output.
The technical scheme of the utility model embodiment is in order to solve the above technical problems, general thought is as follows：
The utility model embodiment provides a kind of clock generation module, including：The biasing circuit that is sequentially connected, annular are shaken
Swing device and enable control circuit；The biasing circuit includes：Energy Saving Control sub-circuit and bias current generation sub-circuit；It is described to make
Circuit can be controlled to include：Energy Saving Control signal generation sub-circuit, duty cycle adjustment sub-circuit and clock signal shaping sub-circuit；Institute
Stating bias current generation sub-circuit is used in the case where enabling the control of signal produce bias current based on bias voltage；The annular is shaken
Swing the first sinusoidal signal that device is used to produce frequency-adjustable based on the bias current；The duty cycle adjustment sub-circuit is used for
The dutycycle of first sinusoidal signal is adjusted under the control for enabling signal, to obtain the second sinusoidal signal；The clock signal
Shaping sub-circuit is used to carry out shaping to second sinusoidal signal, to obtain clock signal；The Energy Saving Control signal is produced
Sub-circuit is used to produce Energy Saving Control signal based on the enable signal；The Energy Saving Control sub-circuit is used to be based on the energy-conservation
Control signal carries out Energy Saving Control management to the biasing circuit.
It can be seen that, in the utility model embodiment, by setting Energy Saving Control signal to produce son in control circuit is enabled
Circuit, and the setting Energy Saving Control sub-circuit in biasing circuit；Further, under the outside control for enabling signal, section is passed through
Energy control signal generation sub-circuit produces Energy Saving Control signal so that Energy Saving Control sub-circuit is based on the Energy Saving Control signal to institute
State biasing circuit and carry out Energy Saving Control management.Meanwhile, in the case where enabling the control of signal, the biased electrical miscarriage in the biasing circuit
Raw sub-circuit produces bias current, and ring oscillator produces the first sinusoidal signal of frequency-adjustable, institute based on the bias current
The duty cycle adjustment sub-circuit and clock signal shaping sub-circuit enabled in control circuit is stated, the first sinusoidal signal is carried out successively
Duty cycle adjustment and Shape correction, to obtain final clock signal.Normal work can not influenceed, realizing that multiple clock is believed
Number output while, reduce circuit energy expenditure.
In order to be better understood from above-mentioned technical proposal, below in conjunction with Figure of description and specific embodiment to upper
State technical scheme to be described in detail, it should be understood that the specific features in the utility model embodiment and embodiment are to this
Apply for the detailed description of technical scheme, rather than the restriction to technical scheme, in the case where not conflicting, this practicality
Technical characteristic in new embodiment and embodiment can be mutually combined.
Fig. 1 is refer to, the utility model embodiment provides a kind of clock generation module, including：The biasing being sequentially connected
Circuit 10, ring oscillator 20 and enable control circuit 30；Biasing circuit 10 includes：Energy Saving Control sub-circuit 101 and biased electrical
Flow generation sub-circuit 102；Enabling control circuit 30 includes：Energy Saving Control signal generation sub-circuit 301, duty cycle adjustment sub-circuit
302 and clock signal shaping sub-circuit 303；
Bias current generation sub-circuit 102 is used in the case where enabling signal EN_CLK control based on bias voltage Vbiasn productions
Raw bias current Ibiasn；
Ring oscillator 20 is used for the first sinusoidal signal S1 that frequency-adjustable is produced based on the bias current Ibiasn；
Duty cycle adjustment sub-circuit 302 is used to adjust accounting for for the first sinusoidal signal S1 in the case where enabling signal EN_CLK control
Sky ratio, to obtain the second sinusoidal signal S2；
Clock signal shaping sub-circuit 303 be used for the second sinusoidal signal S2 carry out shaping, with obtain clock signal clk _
OUT；
Energy Saving Control signal generation sub-circuit 301 is used to produce Energy Saving Control signal UN_ based on enable signal EN_CLK
CLK；
Energy Saving Control sub-circuit 101 is used to carry out energy-conservation control to the biasing circuit 10 based on Energy Saving Control signal UN_CLK
Tubulation is managed.
In specific implementation process, Fig. 2 is refer to, Energy Saving Control sub-circuit 101 includes：First PMOS MP1, second
PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4 and the 5th PMOS MP5；
First PMOS MP1 grid and the Energy Saving Control signal output part of Energy Saving Control signal generation sub-circuit 301
PUN_CLKConnection, for inputting Energy Saving Control signal UN_CLK；First PMOS MP1 source electrode and power voltage terminal PVDDIt is connected,
For input supply voltage VDD；First PMOS MP1 drain electrode is connected with the 4th PMOS MP4 grid, drain electrode；
Second PMOS MP2 grid is connected and is grounded with the 3rd PMOS MP3 grid；Second PMOS MP2 source
Pole and the 3rd PMOS MP3 source electrode with power voltage terminal PVDDIt is connected, for input supply voltage VDD；Second PMOS
The source electrode and the 5th PMOS MP5 source electrode of MP2 drain electrode and the 3rd PMOS MP3 drain electrode respectively with the 4th PMOS MP4
It is connected.
4th PMOS MP4 grid is connected with the 5th PMOS MP5 grid；4th PMOS MP4 drain electrode and the
Five PMOS MP5 drain electrode is connected with bias current generation sub-circuit 102.
Referring still to Fig. 2, bias current generation sub-circuit 102 includes：First NMOS tube MN1, the second NMOS tube MN2,
Three NMOS tube MN3 and the 4th NMOS tube MN4；
The grid of first NMOS tube MN1 grid, drain electrode with the second NMOS tube MN2 is connected, and with biased electrical pressure side PV
It is connected, for input offset voltage Vbiasn；Second NMOS tube MN2 drain electrode is connected with Energy Saving Control sub-circuit 101；First
NMOS tube MN1 source electrode is connected and is grounded with the second NMOS tube MN2 source electrode；Wherein, the second NMOS tube MN2 drain electrode specifically with
4th PMOS MP4 drain electrode is connected.
3rd NMOS tube MN3 grid is connected with the 4th NMOS tube MN4 grid, and with enabling signal end PEN_CLKIt is connected,
Signal EN_CLK is enabled for inputting；3rd NMOS tube MN3 drain electrode and biased electrical pressure side PVIt is connected, for input offset voltage
Vbiasn；4th NMOS tube MN4 drain electrode is connected with Energy Saving Control sub-circuit 101；3rd NMOS tube MN3 source electrode and the 4th
NMOS tube MN4 source electrode is connected and is grounded；Wherein, the drain electrode phase of the 4th NMOS tube MN4 drain electrode specifically with the 5th PMOS MP5
Even.
In specific implementation process, ring oscillator 20 includes：The multiple CMOS inverters being connected with biasing circuit 10, with
And for connecting multiple nodes of multiple CMOS inverters.Fig. 3 is refer to, ring oscillator 20 includes：
First CMOS inverter 201, the second CMOS inverter 202, the 3rd CMOS inverter 203, the 4th CMOS inverter
204th, the 5th CMOS inverter 205, the 6th CMOS inverter 206, the 7th CMOS inverter 207, the 8th CMOS inverter 208；
And for connecting first node K1, Section Point K2, the 3rd node K3 of the first to the 8th CMOS inverter (201~208)
With fourth node K4；
Wherein, the first CMOS inverter 201 and the reverse parallel connection of the second CMOS inverter 202, and the first CMOS inverter 201
Input and output end be connected respectively with first node K1 and Section Point K2；6th CMOS inverter 206 and the 7th CMOS
The reverse parallel connection of phase inverter 207, and the 6th CMOS inverter 206 input and output end respectively with fourth node K4 and the 3rd section
Point K3 connections；
The input and output end of 3rd CMOS inverter 203 are connected with first node K1 and the 3rd node K3 respectively；The
The input and output end of four CMOS inverters 204 are connected with the 3rd node K3 and Section Point K2 respectively；5th CMOS is anti-phase
The input and output end of device 205 are connected with Section Point K2 and fourth node K4 respectively；The input of 8th CMOS inverter 208
End and output end are connected with fourth node K4 and first node K1 respectively.
Further, incorporated by reference to Fig. 3 A and Fig. 3 B, the first CMOS inverter 201 is by the 6th PMOS MP6 and the 5th NMOS tube
MN5 is constituted.Specifically, the bias current output end P of the 6th PMOS MP6 source electrode and biasing circuit 10IConnection, for accessing
Bias current Ibiasn；6th PMOS MP6 grid and the 5th NMOS tube MN5 grid are connected with first node K1, and
It is grounded by the first electric capacity C1；5th NMOS tube MN5 source ground；6th PMOS MP6 drain electrode and the 5th NMOS tube MN5
Drain electrode be connected, and export to the second CMOS inverter 202.
Second CMOS inverter 202 is made up of the 7th PMOS MP7 and the 6th NMOS tube MN6；3rd CMOS inverter 203
It is made up of the 8th PMOS MP8 and the 7th NMOS tube MN7；4th CMOS inverter 204 is by the 9th PMOS MP9 and the 8th NMOS
Pipe MN8 is constituted；5th CMOS inverter 205 is made up of the tenth PMOS MP10 and the 9th NMOS tube MN9；6th CMOS inverter
206 are made up of the 11st PMOS MP11 and the tenth NMOS tube MN10；7th CMOS inverter 207 is by the 12nd PMOS MP12
Constituted with the 11st NMOS tube MN11；8th CMOS inverter 208 is by the 13rd PMOS MP13 and the 12nd NMOS tube MN12
Constitute.Section Point K2 is grounded by the second electric capacity C2, and the 3rd node K3 is grounded by the 3rd electric capacity C3, and fourth node K4 passes through
4th electric capacity C4 is grounded.
The structure of the CMOS inverter 208 of second CMOS inverter 202 to the 8th and the structure class of the first CMOS inverter 201
Seemingly, no longer repeat one by one here.In addition, the structure model of the 6th to the 13rd PMOS (MP6~MP13) can be with the first PMOS
Pipe MP1.
Fig. 4 is refer to, Energy Saving Control signal generation sub-circuit 301 includes：14th PMOS MP14 and the 13rd NMOS
Pipe MN13；
14th PMOS MP14 grid and the 13rd NMOS tube MN13 grid are connected, and with enabling signal end
PEN_CLKIt is connected, signal EN_CLK is enabled for inputting；14th PMOS MP14 source electrode and power voltage terminal PVDDIt is connected, uses
In input supply voltage VDD；13rd NMOS tube MN13 source ground；14th PMOS MP14 drain electrode and the 13rd
NMOS tube MN13 drain electrode is connected, and is connected to Energy Saving Control signal output part PUN_CLK, for exporting Energy Saving Control signal UN_
CLK。
Referring still to Fig. 4, duty cycle adjustment sub-circuit 302 includes：15th PMOS MP15, the 16th PMOS
MP16, the 14th NMOS tube MN14 and the 15th NMOS tube MN15；
15th PMOS MP15 grid and the 15th NMOS tube MN15 grid are connected, and are connected to Energy Saving Control letter
Number output end PUN_CLK, for inputting Energy Saving Control signal UN_CLK；15th PMOS MP15 source electrode and power voltage terminal
PVDDIt is connected, for input supply voltage VDD；The leakage of 15th PMOS MP15 drain electrode respectively with the 16th PMOS MP16
The drain electrode of pole and the 14th NMOS tube MN14 is connected；15th NMOS tube MN15 drain electrode and 14 NMOS tube MN14 source electrode phase
Even；15th NMOS tube MN15 source ground；
14th NMOS tube MN14 grid is connected with the 16th PMOS MP16 grid, and is connected to ring oscillator
20 output end PS1_OUT。
Fig. 4 is refer to, the clock signal shaping sub-circuit 303 includes：9th CMOS inverter 3031 and the tenth CMOS
Phase inverter 3032；
9th CMOS inverter 3031 is made up of the 17th PMOS MP17 and the 16th NMOS tube MN16, and the tenth CMOS is anti-
Phase device 3032 is made up of the 18th PMOS MP18 and the 17th NMOS tube MN17；9th CMOS inverter 3031 and the tenth CMOS
The structure of phase inverter 3032 is similar to the first CMOS inverter 201, no longer repeats one by one here.
17th PMOS MP17 grid and the 16th NMOS tube MN16 grid are connected, and are connected to the dutycycle
The output end of sub-circuit 302 is adjusted, for inputting the second sinusoidal signal S2；17th PMOS MP17 source electrode and supply voltage
Hold PVDDIt is connected, for input supply voltage VDD；17th PMOS MP17 drain electrode and the 16th NMOS tube MN16 drain electrode
It is connected, and is connected to the tenth CMOS inverter 3032；16th NMOS tube MN16 source ground；
18th PMOS MP18 grid and the 17th NMOS tube MN17 grid are connected, and it is anti-to be connected to the 9th CMOS
Phase device 3031；18th PMOS MP18 source electrode and power voltage terminal PVDDIt is connected, for input supply voltage VDD；17th
NMOS tube MN17 source ground；18th PMOS MP18 drain electrode is connected with the 17th NMOS tube MN17 drain electrode, and even
It is connected to clock signal output terminal PCLK_OUT, for exporting clock signal clk _ OUT.
The operation principle of the application clock generation module is described below：
1) for biasing circuit 10：
It refer to Fig. 2, the second PMOS MP2 and the 3rd PMOS MP3 and constitute current-mirror structure, their sizes are identical, stream
The electric current for crossing two metal-oxide-semiconductors is equal.For PMOS, as gate source voltage VGSDuring ＜ 0, gate source voltage is worked as in PMOS conducting
VGSDuring ＞ 0, PMOS shut-off.Second PMOS MP2 and the 3rd PMOS MP3 source electrodes access supply voltage VDD, grid and connect
Ground, therefore, when the voltage supply vdd is on, the second PMOS MP2 and the 3rd PMOS MP3 are in conducting state.4th
The same second PMOS MP2 and the 3rd PMOS MP3 of PMOS MP4 and the 5th PMOS MP5 structure structure, it is not another here
One repeats.When the second PMOS MP2 and the 3rd PMOS MP3 is turned on, the 4th PMOS MP4 and the 5th PMOS MP5 source
Pole is height.By controlling the first PMOS MP1 turn-on and turn-off, the 4th PMOS MP4 and the 5th PMOS MP5 can control
Constitute current-mirror structure work or do not work.
When clock generation module works, it obtains outside enable signal EN_CLK, Energy Saving Control signal generation sub-circuit
301 inputs enable signal EN_CLK, and carry out reverse process to enabling signal EN_CLK, have inverse state with it to obtain
Energy Saving Control signal UN_CLK.For NPMOS pipes, as gate source voltage VGSDuring ＞ 0, NMOS tube conducting, as gate source voltage VGS
During ＜ 0, NMOS tube shut-off.When EN_CLK is low, the current-mirror structure that the 3rd NMOS tube MN3 and the 4th NMOS tube MN4 are constituted
Do not work, UN_CLK is height, the first PMOS MP1 shut-offs, the 4th PMOS MP4 and the 5th PMOS MP5 constitute current mirror knot
Structure works, and to the output current of ring oscillator 20, the normal work of ring oscillator 20.When EN_CLK is high, UN_CLK is
Low, the first PMOS MP1 conductings, the 4th PMOS MP4 and the 5th PMOS MP5 constitute current-mirror structure and not worked, and VDD is direct
Image current is provided to the first NMOS tube MN1 and the second NMOS tube MN2 current-mirror structures constituted by the first PMOS MP1,
So as to be mirrored to ring oscillator 20 again by the 3rd NMOS tube MN3 and the 4th NMOS tube MN4.It can be seen that, by enabling signal
EN_CLK and Energy Saving Control signal UN_CLK is controlled to Energy Saving Control sub-circuit 101 and bias current generation sub-circuit 102,
Energy expenditure when it does not work can be reduced in the control normal work of biasing circuit 10 simultaneously.
2) for ring oscillator 20
As shown in Figure 3A, in using quadrangle as the topological structure of the ring oscillator of major loop, comprising 4 nodes (K1~
K4), node is connected with node by phase inverter (201~208).Oscillator agent structure is that 3 stable loops and 4 are vibrated back
Road.There are 1 major loop and 2 cross coupling inverter circuits among stable loop, major loop is K4 → K1 → K3 → K2 → K4,
Cross coupling inverter circuit is K4 → K3 → K4 and K1 → K2 → K1.Oscillation circuit is that 3 phase inverter cascades constitute loop, 4
Individual oscillation circuit is respectively K4 → K1 → K3 → K4, K1 → K3 → K2 → K1, K3 → K2 → K4 → K3, K2 → K4 → K1 → K2.
By controlling the series of phase inverter in ring oscillator, the frequency-adjustable of output sinusoidal signal is realized.For example, for
Simple three-level annular oscillator, the metal-oxide-semiconductor for being operated in sub-threshold region carries out discharge and recharge in a cycle to parasitic capacitance, makes
Obtain each phase inverter and produce a time delay TD.Under the interference of noise, it is assumed that when first phase inverter input is high, by posting
The delay of raw electric capacity and resistance, after time TD, the input of second phase inverter is low, is also passed through the 3rd after delay TD
The input of individual phase inverter is height, by that analogy, and the input of first phase inverter is returned to after the 3rd phase inverter delay TD
To be low, then by 3TD, the input of first phase inverter is height.Therefore the cycle that clock can be obtained is T=6TD.Other situations
By that analogy, no longer repeat one by one here.
3) for enabling control circuit 30
The input of Energy Saving Control signal generation sub-circuit 301 enables signal EN_CLK, and is carried out instead to enabling signal EN_CLK
To processing, to obtain the Energy Saving Control signal UN_CLK with it with inverse state.
15th PMOS MP15, the 16th PMOS MP16, the 14th NMOS tube in duty cycle adjustment sub-circuit 302
MN14 and the 15th NMOS tube MN15, has collectively constituted a NAND gate, and when UN_CLK is high, input and output are identical, with regard to phase
When a then phase inverter.Voltage transfer curve can be obtained by the DC characteristic of phase inverter.In order to obtain desired dutycycle,
It can adjust the size of pipe to realize according to transfer point voltage equation.
Two phase inverters are used for the duty exported to duty cycle adjustment sub-circuit 302 in clock signal shaping sub-circuit 303
The the second sinusoidal signal S2 obtained after being handled than regulation carries out Shape correction, to obtain square-like clock signal CLK_OUT.
In specific implementation process, supply voltage and capacitance determine output clock frequency and dutycycle, meanwhile, technique
Output clock frequency and dutycycle can be also influenceed with the size and drain voltage of temperature and metal-oxide-semiconductor.
Sum it up, in the utility model embodiment, by setting Energy Saving Control signal to produce in control circuit is enabled
Raw sub-circuit, and the setting Energy Saving Control sub-circuit in biasing circuit；Further, under the outside control for enabling signal, lead to
Cross energy-conservation control signal generation sub-circuit and produce Energy Saving Control signal so that Energy Saving Control sub-circuit is based on the Energy Saving Control signal
Energy Saving Control management is carried out to the biasing circuit.Meanwhile, in the case where enabling the control of signal, the biased electrical in the biasing circuit
Flow generation sub-circuit and produce bias current, ring oscillator produces the first sinusoidal letter of frequency-adjustable based on the bias current
Number, the duty cycle adjustment sub-circuit and clock signal shaping sub-circuit enabled in control circuit is sinusoidal to first successively to believe
Number duty cycle adjustment and Shape correction are carried out, to obtain final clock signal.Can do not influence normal work, realize it is a variety of
While clock signal is exported, the energy expenditure of circuit is reduced.
Although having been described for preferred embodiment of the present utility model, those skilled in the art once know substantially
Creative concept, then can make other change and modification to these embodiments.So, appended claims are intended to be construed to bag
Include preferred embodiment and fall into having altered and changing for the utility model scope.
Obviously, those skilled in the art can carry out various changes and modification without departing from this practicality to the utility model
New spirit and scope.So, if these modifications and variations of the present utility model belong to the utility model claim and
Within the scope of its equivalent technologies, then the utility model is also intended to comprising including these changes and modification.
Claims (10)
1. a kind of clock generation module, it is characterised in that including：Biasing circuit (10), the ring oscillator (20) being sequentially connected
Circuit (30) is controlled with enabling；The biasing circuit (10) includes：Energy Saving Control sub-circuit (101) and bias current produce son electricity
Road (102)；The control circuit (30) that enables includes：Energy Saving Control signal generation sub-circuit (301), duty cycle adjustment sub-circuit
And clock signal shaping sub-circuit (303) (302)；
The bias current generation sub-circuit (102) is used in the case where enabling the control of signal (EN_CLK) be based on bias voltage
(Vbiasn) bias current (Ibiasn) is produced；
The ring oscillator (20) is used for the first sinusoidal signal that frequency-adjustable is produced based on the bias current (Ibiasn)
(S1)；
The duty cycle adjustment sub-circuit (302) is used to adjust the described first sinusoidal letter in the case where enabling the control of signal (EN_CLK)
The dutycycle of number (S1), to obtain the second sinusoidal signal (S2)；
The clock signal shaping sub-circuit (303) is used to carry out shaping to second sinusoidal signal (S2), to obtain clock
Signal (CLK_OUT)；
The Energy Saving Control signal generation sub-circuit (301) is used to produce Energy Saving Control letter based on the enable signal (EN_CLK)
Number (UN_CLK)；
The Energy Saving Control sub-circuit (101) is used for based on the Energy Saving Control signal (UN_CLK) to the biasing circuit (10)
Carry out Energy Saving Control management.
2. clock generation module as claimed in claim 1, it is characterised in that the Energy Saving Control sub-circuit (101) includes：The
One PMOS (MP1), the second PMOS (MP2), the 3rd PMOS (MP3), the 4th PMOS (MP4) and the 5th PMOS
(MP5)；
The grid of first PMOS (MP1) and the Energy Saving Control signal of the Energy Saving Control signal generation sub-circuit (301)
Output end (PUN_CLK) connection, for inputting Energy Saving Control signal (UN_CLK)；The source electrode of first PMOS (MP1) and electricity
Source voltage end (PVDD) be connected, for input supply voltage (VDD)；The drain electrode and the described 4th of first PMOS (MP1)
The grid of PMOS (MP4), drain electrode are connected；
The grid of second PMOS (MP2) is connected and is grounded with the grid of the 3rd PMOS (MP3)；Described second
The source electrode of PMOS (MP2) and the source electrode of the 3rd PMOS (MP3) with power voltage terminal (PVDD) be connected, for inputting
Supply voltage (VDD)；The drain electrode of second PMOS (MP2) and the drain electrode of the 3rd PMOS (MP3) respectively with it is described
The source electrode of 4th PMOS (MP4) is connected with the source electrode of the 5th PMOS (MP5)；
The grid of 4th PMOS (MP4) is connected with the grid of the 5th PMOS (MP5)；4th PMOS
(MP4) drain electrode is connected with the drain electrode of the 5th PMOS (MP5) with the bias current generation sub-circuit (102).
3. clock generation module as claimed in claim 1, it is characterised in that bias current generation sub-circuit (102) bag
Include：First NMOS tube (MN1), the second NMOS tube (MN2), the 3rd NMOS tube (MN3) and the 4th NMOS tube (MN4)；
The grid of the grid of first NMOS tube (MN1), drain electrode with second NMOS tube (MN2) is connected, and with biasing
Voltage end (PV) be connected, for input offset voltage (Vbiasn)；The drain electrode of second NMOS tube (MN2) is controlled with the energy-conservation
System circuit (101) is connected；The source electrode of first NMOS tube (MN1) is connected simultaneously with the source electrode of second NMOS tube (MN2)
Ground connection；
The grid of 3rd NMOS tube (MN3) is connected with the grid of the 4th NMOS tube (MN4), and with enabling signal end
(PEN_CLK) be connected, enable signal (EN_CLK) for inputting；The drain electrode of 3rd NMOS tube (MN3) and biased electrical pressure side
(PV) be connected, for input offset voltage (Vbiasn)；The drain electrode of 4th NMOS tube (MN4) and Energy Saving Control electricity
Road (101) is connected；The source electrode of 3rd NMOS tube (MN3) is connected and is grounded with the source electrode of the 4th NMOS tube (MN4).
4. clock generation module as claimed in claim 1, it is characterised in that the ring oscillator (20) includes：With it is described
The connected multiple CMOS inverters of biasing circuit (10), and for connecting multiple nodes of the multiple CMOS inverter.
5. clock generation module as claimed in claim 1, it is characterised in that the ring oscillator (20) includes：
First CMOS inverter (201), the second CMOS inverter (202), the 3rd CMOS inverter (203), the 4th CMOS are anti-phase
Device (204), the 5th CMOS inverter (205), the 6th CMOS inverter (206), the 7th CMOS inverter (207), the 8th CMOS
Phase inverter (208)；And for connect the described first to the 8th CMOS inverter (201~208) first node (K1), second
Node (K2), the 3rd node (K3) and fourth node (K4)；
Wherein, first CMOS inverter (201) and second CMOS inverter (202) reverse parallel connection, and described first
The input and output end of CMOS inverter (201) are connected with the first node (K1) and the Section Point (K2) respectively；
6th CMOS inverter (206) and the 7th CMOS inverter (207) reverse parallel connection, and the 6th CMOS inverter
(206) input and output end is connected with the fourth node (K4) and the 3rd node (K3) respectively；
The input and output end of 3rd CMOS inverter (203) respectively with the first node (K1) and described Section three
Point (K3) is connected；The input and output end of 4th CMOS inverter (204) respectively with the 3rd node (K3) and institute
State Section Point (K2) connection；The input and output end of 5th CMOS inverter (205) respectively with the Section Point
(K2) connected with the fourth node (K4)；The input and output end of 8th CMOS inverter (208) respectively with it is described
Fourth node (K4) and the first node (K1) connection.
6. clock generation module as claimed in claim 5, it is characterised in that the first node (K1) passes through the first electric capacity
(C1) it is grounded, the Section Point (K2) is grounded by the second electric capacity (C2), the 3rd node (K3) passes through the 3rd electric capacity
(C3) it is grounded, the fourth node (K4) is grounded by the 4th electric capacity (C4).
7. clock generation module as claimed in claim 5, it is characterised in that the first CMOS inverter (201) is by the 6th PMOS
Manage (MP6) and the 5th NMOS tube (MN5) is constituted；Second CMOS inverter (202) is by the 7th PMOS (MP7) and the 6th NMOS tube
(MN6) constitute；3rd CMOS inverter (203) is made up of the 8th PMOS (MP8) and the 7th NMOS tube (MN7)；4th CMOS
Phase inverter (204) is made up of the 9th PMOS (MP9) and the 8th NMOS tube (MN8)；5th CMOS inverter (205) is by the tenth
PMOS (MP10) and the 9th NMOS tube (MN9) are constituted；6th CMOS inverter (206) is by the 11st PMOS (MP11) and
Ten NMOS tubes (MN10) are constituted；7th CMOS inverter (207) is by the 12nd PMOS (MP12) and the 11st NMOS tube
(MN11) constitute；8th CMOS inverter (208) is made up of the 13rd PMOS (MP13) and the 12nd NMOS tube (MN12).
8. clock generation module as claimed in claim 1, it is characterised in that the Energy Saving Control signal generation sub-circuit
(301) include：14th PMOS (MP14) and the 13rd NMOS tube (MN13)；
The grid of 14th PMOS (MP14) is connected with the grid of the 13rd NMOS tube (MN13), and believes with enabling
Number end (PEN_CLK) be connected, enable signal (EN_CLK) for inputting；The source electrode of 14th PMOS (MP14) and power supply electricity
Pressure side (PVDD) be connected, for input supply voltage (VDD)；The source ground of 13rd NMOS tube (MN13)；Described tenth
The drain electrode of four PMOSs (MP14) is connected with the drain electrode of the 13rd NMOS tube (MN13), and it is defeated to be connected to Energy Saving Control signal
Go out end (PUN_CLK), for exporting Energy Saving Control signal (UN_CLK).
9. clock generation module as claimed in claim 1, it is characterised in that the duty cycle adjustment sub-circuit (302) includes：
15th PMOS (MP15), the 16th PMOS (MP16), the 14th NMOS tube (MN14) and the 15th NMOS tube (MN15)；
The grid of 15th PMOS (MP15) is connected with the grid of the 15th NMOS tube (MN15), and is connected to section
Can control signal output (PUN_CLK), for inputting Energy Saving Control signal (UN_CLK)；15th PMOS (MP15)
Source electrode and power voltage terminal (PVDD) be connected, for input supply voltage (VDD)；The drain electrode of 15th PMOS (MP15)
It is connected respectively with the drain electrode of the 16th PMOS (MP16) and the drain electrode of the 14th NMOS tube (MN14)；Described tenth
The drain electrode of five NMOS tubes (MN15) is connected with the source electrode of 14 NMOS tube；The source electrode of 15th NMOS tube (MN15) connects
Ground；
The grid of 14th NMOS tube (MN14) is connected with the grid of the 16th PMOS (MP16), and is connected to institute
State the output end (P of ring oscillator (20)S1_OUT)。
10. clock generation module as claimed in claim 1, it is characterised in that clock signal shaping sub-circuit (303) bag
Include：9th CMOS inverter (3031) and the tenth CMOS inverter (3032)；
9th CMOS inverter (3031) is made up of the 17th PMOS (MP17) and the 16th NMOS tube (MN16), described
Tenth CMOS inverter (3032) is made up of the 18th PMOS (MP18) and the 17th NMOS tube (MN17)；
The grid of 17th PMOS (MP17) is connected with the grid of the 16th NMOS tube (MN16), and is connected to institute
State the output end of duty cycle adjustment sub-circuit (302)；The source electrode of 17th PMOS (MP17) and power voltage terminal (PVDD)
It is connected, for input supply voltage (VDD)；The drain electrode of 17th PMOS (MP17) and the 16th NMOS tube
(MN16) drain electrode is connected, and is connected to the tenth CMOS inverter (3032)；The source of 16th NMOS tube (MN16)
Pole is grounded；
The grid of 18th PMOS (MP18) is connected with the grid of the 17th NMOS tube (MN17), and is connected to institute
State the 9th CMOS inverter (3031)；The source electrode of 18th PMOS (MP18) and power voltage terminal (PVDD) be connected, it is used for
Input supply voltage (VDD)；The source ground of 17th NMOS tube (MN17)；The leakage of 18th PMOS (MP18)
The drain electrode of pole and the 17th NMOS tube (MN17) is connected, and is connected to clock signal output terminal (PCLK_OUT), for exporting
Clock signal (CLK_OUT).
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|---|---|---|---|
| CN201720091856.3U CN206547080U (en) | 2017-01-22 | 2017-01-22 | A kind of clock generation module |
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| CN201720091856.3U CN206547080U (en) | 2017-01-22 | 2017-01-22 | A kind of clock generation module |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111294017A (en) * | 2020-03-20 | 2020-06-16 | 内蒙古显鸿科技股份有限公司 | Low-power consumption clock generation circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111294017A (en) * | 2020-03-20 | 2020-06-16 | 内蒙古显鸿科技股份有限公司 | Low-power consumption clock generation circuit |
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Address after: 511458 Nansha District, Guangzhou, Guangdong Province, No. 2 Huanshi Avenue South, Software South Building 3003, Guangzhou Nansha Information Technology Park Patentee after: Guangzhou Xinshiwu Technology Co., Ltd. Address before: 511458 Nansha District, Guangzhou, Guangdong Province, No. 2 Huanshi Avenue South, Software South Building 3003, Guangzhou Nansha Information Technology Park Patentee before: Guangzhou World Heritage Mdt InfoTech Ltd |