CN104579245B - RC oscillator - Google Patents
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- CN104579245B CN104579245B CN201410151448.3A CN201410151448A CN104579245B CN 104579245 B CN104579245 B CN 104579245B CN 201410151448 A CN201410151448 A CN 201410151448A CN 104579245 B CN104579245 B CN 104579245B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
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- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
- Oscillators With Electromechanical Resonators (AREA)
Abstract
The invention discloses a kind of RC oscillators, including offset generating circuit and oscillation generating circuit.For generating bias current, the size of bias current is determined offset generating circuit by the size of two resistance and the threshold voltage of a NMOS tube.Oscillation generating circuit is respectively used to the capacitor charging to two charge-discharge circuits using two mirror image circuits, and the capacitor of two charge-discharge circuits discharges over the ground.Two control signal generating circuits generate two control signals according to the voltage of the capacitor of charge-discharge circuit, control signal is input in output circuit and outputting oscillation signal and the feedback signal for controlling capacitor charge and discharge, the threshold voltage for controlling the NMOS tube of signal generating circuit is identical with the threshold voltage of the NMOS tube of offset generating circuit, so that the frequency of oscillator signal is only related with capacitor with two resistance.Circuit structure of the present invention is simple, and the frequency precision with higher of the oscillator signal exported.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of RC oscillator.
Background technique
In many System on Chip/SoC (system on chip, SOC) application, oscillator is a very important module.
Oscillator is divided into resistance-capacitance oscillator i.e. RC oscillator, LC oscillator, crystal oscillator, tuning fork oscillator etc..RC oscillation
Device is the output that oscillator signal is realized by charging and discharging to capacitor, and the value by adjusting resistance or capacitor can be adjusted
The frequency of oscillator signal.Relative in the oscillator of various other types, RC oscillator has structure simple, and precision is higher excellent
Point, so in some SOC chips, such as in single-chip microcontroller (Micro Control Unit, MCU), RC oscillator is very common.
In SOC chip, the circuit of device is simpler, then the cost of chip is lower；Meanwhile the oscillation of RC oscillator output
Signal accuracy is higher, and the performance of chip is better.The circuit structure of existing RC oscillator or oscillation letter that is complex, and exporting
Number frequency be easy by supply voltage, temperature etc. influence, this can all reduce the frequency accuracy of oscillator signal, so how to obtain
Circuit structure is simple and to export the RC oscillator of the oscillation signal frequency of degree of precision be a significantly research class
Topic.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of RC oscillators, and circuit structure is simple, and the oscillation exported
The frequency of signal precision with higher.
In order to solve the above technical problems, RC oscillator provided by the invention includes that offset generating circuit and oscillation generate electricity
Road.
The offset generating circuit is for generating bias current；The offset generating circuit includes the first current path, the
Two current paths and an operational amplifier, first current path include the first PMOS tube and first resistor, second electricity
Flow path includes the second PMOS tube, second resistance and the first NMOS tube, the source of first PMOS tube and second PMOS tube
Pole all connects the output end that supply voltage, grid all connect the operational amplifier；The first end connection described the of the first resistor
The drain electrode of one PMOS tube and the first input end of the operational amplifier, the second end ground connection of first resistor；2nd PMOS
The first end of the drain electrode of pipe, the grid of first NMOS tube and the second resistance links together, the second resistance
Second end connects drain electrode and the second input terminal of the operational amplifier of first NMOS tube, the source of first NMOS tube
Pole ground connection, the first input end of the operational amplifier and the second input terminal are two input terminals of reverse phase each other.
The size of second bias current of the first bias current of first current path and second current path
Ratio is determined by the breadth length ratio of channel and the ratio of breadth length ratio of channel of second PMOS tube of first PMOS tube；Institute
It states the first NMOS tube and works in saturation region, the size of first bias current and second bias current is by described first
The value of the grid voltage of NMOS tube, the first resistor and the second resistance is determining, the width of the channel of first NMOS tube
It is long than meet make first NMOS tube grid voltage be in first NMOS tube threshold voltage positive and negative 2% range
It is interior.
The oscillation generating circuit includes two mirror image circuits and two charge-discharge circuits, the first charge-discharge circuit and first
Mirror image circuit is connected, the second charge-discharge circuit and the second mirror image circuit are connected, and first mirror image circuit generates and described first
The first proportional image current of bias current, second mirror image circuit generates and first bias current is proportional the
Two image currents.
First charge-discharge circuit includes first capacitor, the 7th PMOS tube and the 4th NMOS tube, the 7th PMOS tube
The second feedback signal is all connect with the grid of the 4th NMOS tube, the source electrode of the 7th PMOS tube connects the first mirror image electricity
The first image current output end on road, the drain electrode of the 7th PMOS tube and the 4th NMOS tube all connect the first capacitor
First end, the 4th NMOS tube source electrode ground connection, the first capacitor second end ground connection.
Second charge-discharge circuit includes the second capacitor, the 8th PMOS tube and the 5th NMOS tube, the 8th PMOS tube
The first feedback signal is all connect with the grid of the 5th NMOS tube, the source electrode of the 8th PMOS tube connects the second mirror image electricity
The second image current output end on road, the drain electrode of the 8th PMOS tube and the 5th NMOS tube all connect second capacitor
First end, the 5th NMOS tube source electrode ground connection, second capacitor second end ground connection.
The oscillation generating circuit further includes two control signal generating circuits, the first control signal generation circuit packet
Third PMOS tube and the second NMOS tube are included, the source electrode of the third PMOS tube connects supply voltage, the grid of the third PMOS tube
Pole connects the grid of first PMOS tube, and the third PMOS tube is connected and with the drain electrode of second NMOS tube as first
The output end of signal is controlled, the grid of second NMOS tube connects the first end of the first capacitor, second NMOS tube
Source electrode ground connection, the threshold voltage of second NMOS tube is equal to the threshold voltage of first NMOS tube, in first electricity
It is low level that the voltage of the first end of appearance, which is greater than the first control signal when threshold voltage of second NMOS tube, described
It is high level that the voltage of the first end of first capacitor, which is less than the first control signal when threshold voltage of second NMOS tube,.
The second control signal generation circuit includes the 4th PMOS tube and third NMOS tube, the source of the 4th PMOS tube
Pole connects supply voltage, and the grid of the 4th PMOS tube connects the grid of first PMOS tube, the 4th PMOS tube and
The drain electrode of the third NMOS tube is connected and the output end as second control signal, and the grid of the third NMOS tube connects institute
The first end of the second capacitor is stated, the source electrode ground connection of the third NMOS tube, the threshold voltage of the third NMOS tube is equal to described
The threshold voltage of first NMOS tube is greater than the threshold voltage of the third NMOS tube in the voltage of the first end of second capacitor
Shi Suoshu second control signal is low level, is less than the threshold of the third NMOS tube in the voltage of the first end of second capacitor
The second control signal is high level when threshold voltage.
The oscillation generating circuit further includes an output circuit, the output circuit include 8 phase inverters and two with
NOT gate, the output end of the first NAND gate connect the first input end of the second NAND gate, the output end connection of second NAND gate
The first input end of first NAND gate；It is gone here and there between the first control signal and the second input terminal of first NAND gate
There are two phase inverters for connection, and there are two reverse phases for series connection between the second control signal and the second input terminal of second NAND gate
Device；The output end of first NAND gate passes through outputting oscillation signal after connecting with two concatenated phase inverters；Described second with
The output end of NOT gate is passed through and one by output first feedback signal that is connected with a phase inverter, first feedback signal
Phase inverter, which is connected, exports second feedback signal.
A further improvement is that first PMOS tube is identical with the breadth length ratio of the channel of second PMOS tube, it is described
First bias current and second bias current it is equal in magnitude.
A further improvement is that first image current and first bias current is equal in magnitude, described second
Image current and first bias current it is equal in magnitude.
A further improvement is that first mirror image circuit is made of the 5th PMOS tube, the grid of the 5th PMOS tube
The grid of first PMOS tube is connected, the source electrode of the 5th PMOS tube connects supply voltage, the leakage of the 5th PMOS tube
Pole exports first image current.
A further improvement is that first PMOS tube is identical with the breadth length ratio of the channel of the 5th PMOS tube, it is described
First bias current and first image current it is equal in magnitude.
A further improvement is that second mirror image circuit is made of the 6th PMOS tube, the grid of the 6th PMOS tube
The grid of first PMOS tube is connected, the source electrode of the 6th PMOS tube connects supply voltage, the leakage of the 6th PMOS tube
Pole exports second image current.
A further improvement is that first PMOS tube is identical with the breadth length ratio of the channel of the 6th PMOS tube, it is described
First bias current and second image current it is equal in magnitude.
A further improvement is that the first capacitor and second capacitor is equal in magnitude.
A further improvement is that by adjusting the first resistor, the second resistance, the first capacitor and described the
The frequency of oscillator signal described in the big minor adjustment of two capacitors.
A further improvement is that the RC oscillator is integrated in same SOC chip.
RC oscillator of the present invention has the following beneficial effects:
1, circuit of the present invention uses 2 resistance and 2 capacitors, other parts are all made of NMOS tube or PMOS tube, all
It can be realized using CMOS technology, so the configuration of the present invention is simple and being easily integrated on the same chip, be can be good in SOC core
On piece is applied.
2, the breadth length ratio that the present invention passes through the channel of the first NMOS tube in the second current path to offset generating circuit
Setting, the size of the first bias current and the second bias current that enable to offset generating circuit only with the first NMOS tube
Threshold voltage is related with two resistance of offset generating circuit；The present invention is by producing two control signals of oscillation generating circuit
The threshold voltage of NMOS tube and the threshold voltage of the first NMOS tube of raw circuit are set as identical, enable to entire circuit output
Oscillator signal frequency it is only related with two resistance and two capacitors, eliminate supply voltage and each NMOS tube or PMOS tube
Influence to the frequency of oscillator signal, so the frequency precision with higher of the oscillator signal of output, and by adjusting two
Resistance or two capacitors can be achieved with the adjusting of the frequency of oscillator signal, and the frequency of oscillator signal is easy to adjust.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is circuit diagram of the embodiment of the present invention.
Specific embodiment
As shown in Figure 1, being circuit diagram of the embodiment of the present invention.RC oscillator of the embodiment of the present invention includes offset generating circuit 1
With oscillation generating circuit 2.Preferably, the RC oscillator is integrated in same SOC chip.
The offset generating circuit 1 is for generating bias current；The offset generating circuit 1 include the first current path,
Second current path and an operational amplifier 3, first current path include the first PMOS tube mp1 and first resistor R1, institute
State the second current path include the second PMOS tube mp2, second resistance R2 and the first NMOS tube mn1, the first PMOS tube mp1 and
The source electrode of the second PMOS tube mp2 all connects the output end that supply voltage VDD, grid all connect the operational amplifier 3；Described
The first end of one resistance R1 connect the first PMOS tube mp1 drain electrode and the operational amplifier 3 first input end, first
The second end of resistance R1 is grounded；The drain electrode of the second PMOS tube mp2, the first NMOS tube mn1 grid and described second
The first end of resistance R2 links together, the second end of the second resistance R2 connect the first NMOS tube mn1 drain electrode and
Second input terminal of the operational amplifier 3, the source electrode ground connection of the first NMOS tube mn1, the first of the operational amplifier 3
Input terminal and the second input terminal are two input terminals of reverse phase each other.
The second bias current I2's of the first bias current I1 and second current path of first current path
Size ratio by the first PMOS tube mp1 channel breadth length ratio and the second PMOS tube mp2 channel breadth length ratio
Ratio determines；Preferably, the first PMOS tube mp1 is identical with the breadth length ratio of the channel of the second PMOS tube mp2, and described
One bias current I1's and the second bias current I2 is equal in magnitude.
The first NMOS tube mn1 works in saturation region, the first bias current I1 and the second bias current I2
Size determined by the value of the grid voltage of the first NMOS tube mn1, the first resistor R1 and the second resistance R2, institute
The grid voltage for stating the first NMOS tube mn1 is approximately equal to the threshold voltage of the first NMOS tube mn1, specially described first NMOS
The breadth length ratio of the channel of pipe mn1 meets the threshold for making the grid voltage of the first NMOS tube mn1 be in the first NMOS tube mn1
In the range of positive and negative the 2% of threshold voltage.The principle that the size of the first bias current I1 and second biasing circuit determines
It is described as follows:
V1 is enabled to indicate that the voltage of first end of the first resistor R1, V2 are the electricity of the second end of the second resistance R2
Pressure, V3 are the voltage of the first end of the second resistance R2.
Have in the offset generating circuit 1 work: I1=I2, V1=V2, I1=V1/R1, I2=(V3-V2)/R2, warp
It crosses and derives available following formula (1):
I=I1=I2=V3/ (R1+R2) --- --- --- --- --- --- --- --- (1)
I indicates bias current, by formula (1) it is found that the size of bias current is electric by the grid of the first NMOS tube mn1
The value of pressure, the first resistor R1 and the second resistance R2 determines.Formula (1) is with the first PMOS tube mp1 and described
What the breadth length ratio of the channel of the second PMOS tube mp2 obtained when identical, as the first PMOS tube mp1 and second PMOS tube
When the breadth length ratio difference of the channel of mp2 is to make to have certain ratio between the I1 and I2, phase need to be only added in formula (1)
The ratio answered, specific derive no longer are introduced, and the size of the bias current finally obtained in this way is still by the first NMOS
The value of the grid voltage of pipe mn1, the first resistor R1 and the second resistance R2 determines.
The grid of the first NMOS tube mn1 as described in the embodiment of the present invention is connected with drain electrode by the second resistance R2
Together, the first NMOS tube mn1 can work in saturation region, by giving the first NMOS tube mn1 channel appropriate
Breadth length ratio, then grid voltage, that is, V3 of the first NMOS tube mn1 can be approximately equal to the threshold voltage of the first NMOS tube mn1
Vthn, it may be assumed that
V3=Vthn-------------------------------- (2)
Situation when formula (2) gives V3 equal to Vthn, in practical situation, V3 can change in a certain range,
The frequency for the oscillator signal Osc_out that V3 is exported when changing can also change.Preferably, the grid electricity of the first NMOS tube mn1
In the range of positive and negative the 2% of threshold voltage of the pressure in the first NMOS tube mn1；Further improvement is the first NMOS
The grid voltage of pipe mn1 is in the range of positive and negative the 1% of the threshold voltage of the first NMOS tube mn1.
The oscillation generating circuit 2 includes two mirror image circuits and two charge-discharge circuits, the first charge-discharge circuit and the
One mirror image circuit is connected, the second charge-discharge circuit and the second mirror image circuit are connected.
First mirror image circuit generates and the first bias current I1 is proportional the first image current I3, described the
Two mirror image circuits generate and the second the first bias current I1 proportional image current I4.Preferably, first mirror image
Circuit is made of the 5th PMOS tube mp5, and the grid of the 5th PMOS tube mp5 connects the grid of the first PMOS tube mp1, institute
The drain electrode for stating source electrode connection the supply voltage VDD, the 5th PMOS tube mp5 of the 5th PMOS tube mp5 exports first mirror image
Electric current I3；The first PMOS tube mp1 is identical with the breadth length ratio of the channel of the 5th PMOS tube mp5, first biased electrical
Flow the equal in magnitude of I1 and the first image current I3.Second mirror image circuit is made of the 6th PMOS tube mp6, and described
The grid of six PMOS tube mp6 connects the grid of the first PMOS tube mp1, and the source electrode of the 6th PMOS tube mp6 connects power supply
The drain electrode of voltage VDD, the 6th PMOS tube mp6 export the second image current I4；The first PMOS tube mp1 and described
The breadth length ratio of the channel of 6th PMOS tube mp6 is identical, the size of the first bias current I1 and the second image current I4
It is equal.
First charge-discharge circuit includes first capacitor C1, the 7th PMOS tube mp7 and the 4th NMOS tube mn4, and described
The grid of seven PMOS tube mp7 and the 4th NMOS tube mn4 all meet the second feedback signal fb_b, the 7th PMOS tube mp7's
Source electrode connects the first image current I3 output end of first mirror image circuit, the 7th PMOS tube mp7 and the described 4th
The drain electrode of NMOS tube mn4 all connects the first end of the first capacitor C1, and the source electrode ground connection of the 4th NMOS tube mn4 is described
The second end of first capacitor C1 is grounded.
Second charge-discharge circuit includes the second capacitor C2, the 8th PMOS tube mp8 and the 5th NMOS tube mn5, and described the
The grid of eight PMOS tube mp8 and the 5th NMOS tube mn5 all meet the first feedback signal fb_a, the 8th PMOS tube mp8's
Source electrode connects the second image current I4 output end of second mirror image circuit, the 8th PMOS tube mp8 and the described 5th
The drain electrode of NMOS tube mn5 all connects the first end of the second capacitor C2, and the source electrode ground connection of the 5th NMOS tube mn5 is described
The second end of second capacitor C2 is grounded.Preferably, the first capacitor C1's and the second capacitor C2 is equal in magnitude.
The oscillation generating circuit 2 further includes two control signal generating circuits, the first control signal generation circuit
Supply voltage VDD is connected including the source electrode of third PMOS tube mp3 and the second NMOS tube mn2, the third PMOS tube mp3, it is described
The grid of third PMOS tube mp3 connects the grid of the first PMOS tube mp1, the third PMOS tube mp3 and described second
The drain electrode of NMOS tube mn2 is connected and the output end as first control signal in1, the grid connection of the second NMOS tube mn2
The first end of the first capacitor C1, the source electrode ground connection of the second NMOS tube mn2, the threshold value electricity of the second NMOS tube mn2
Threshold voltage of the pressure equal to the first NMOS tube mn1 is all Vthn, big in the voltage of the first end of the first capacitor C1
The first control signal in1 is low level when the threshold voltage of the second NMOS tube mn2, the first capacitor C1's
It is high level that the voltage of first end, which is less than the first control signal in1 when threshold voltage of the second NMOS tube mn2,.
The second control signal generation circuit includes the 4th PMOS tube mp4 and third NMOS tube mn3, the 4th PMOS
The source electrode of pipe mp4 connects supply voltage VDD, and the grid of the 4th PMOS tube mp4 connects the grid of the first PMOS tube mp1
Pole, the 4th PMOS tube mp4 is connected with the drain electrode of the third NMOS tube mn3 and the output as second control signal in2
End, the grid of the third NMOS tube mn3 connect the first end of the second capacitor C2, the source electrode of the third NMOS tube mn3
Ground connection, the threshold voltage of the third NMOS tube mn3 are equal to the threshold voltage of the first NMOS tube mn1, in second electricity
It is low electricity that the voltage for holding the first end of C2, which is greater than the second control signal in2 when threshold voltage of the third NMOS tube mn3,
It is flat, when the voltage of the first end of the second capacitor C2 is less than the threshold voltage of the third NMOS tube mn3 described in the second control
Signal in2 processed is high level.
The oscillation generating circuit 2 further includes an output circuit 4, and the output circuit 4 includes 8 phase inverters 5 and two
A NAND gate, the output end of the first NAND gate 6a connect the first input end of the second NAND gate 6b, the second NAND gate 6b's
Output end connects the first input end of the first NAND gate 6a；The first control signal in1 and the first NAND gate 6a
The second input terminal between series connection there are two phase inverter 5, the second of the second control signal in2 and the second NAND gate 6b
There are two phase inverters 5 for series connection between input terminal；The output end of the first NAND gate 6a passes through and two concatenated phase inverters 5 connect
Meet rear outputting oscillation signal Osc_out；The output end of the second NAND gate 6b exports described the by being connected with a phase inverter 5
Two feedback signal fb_b, the second feedback signal fb_b pass through output first feedback signal that is connected with a phase inverter 5
fb_a.In the embodiment of the present invention, by adjusting the first resistor R1, the second resistance R2, the first capacitor C1 and institute
State the frequency of oscillator signal Osc_out described in the big minor adjustment of the second capacitor C2.
Illustrate that the working principle of the embodiment of the present invention is as follows for when now in a preferred embodiment thereof:
As can be seen above, in better embodiment, the first PMOS tube mp1, the second PMOS tube mp2, institute
The breadth length ratio for stating the channel of the 5th PMOS tube mp5 and the 6th PMOS tube mp6 is all identical, there is first bias current in this way
I1, the second bias current I2, the size of the first image current I3 and the second image current I4 are all equal, it may be assumed that
I=I3=I4=I1=I2--------------------------------- (3)
In better embodiment, the size of the first capacitor C1 and the second capacitor C2 are also identical, and described first
The voltage of the first end of capacitor C1 is Vn1, and the voltage of the first end of the second capacitor C2 is Vn2.
If the electric current of the second NMOS tube mn2 is far longer than third PMOS tube mp3's when Vn1 reaches Vthn from 0
Electric current.In this way when Vn1 reaches Vthn from 0, in1 just rapidly changes to 0 from VDD；Similarly, when vn2 reaches Vthn from 0,
In2 just rapidly changes to 0 from VDD.So vn1 and vn2 are converted between 0 and vthn when the RC oscillator operation.
As seen from Figure 1, the first NAND gate 6a connects to form a rest-set flip-flop with the second NAND gate 6b
Structure；If in2 is 0, fb_b is also that 0, fb_a is equal to VDD, this meeting is so that I3 gives vn1 charging, the second capacitor C2
It is discharged by the 5th NMOS tube mn5 to vn2.When vn1 reaches Vthn from 0, in1 is equal to 0, in2 and is equal to VDD, at this point,
Fb_a is equal to 0, fb_b and is equal to VDD, and then, vn1 starts to discharge, and vn2 is started to charge.When vn2 reaches Vthn, in2 is equal to 0,
In1 is equal to VDD, so that fb_a is got higher, fb_b is lower for this meeting, in this way, vn1 is started to charge, and vn2 starts to discharge；So follow
Ring, oscillation just produce, and eventually form the oscillator signal Osc_out.
Vn1 and Vn2 constantly changes to VDD from 0, or changes to 0. within the half period of oscillation from VDD:
I*t=Vthn*C--------------------------------- (4)
In conjunction with formula (1)~(4), obtain:
T=(R1+R2) * C
Then, the period of the oscillator signal Osc_out of the RC oscillator are as follows:
T=2t=2 (R1+R2) × C-------------------------------- (5)
Frequency of oscillation:
F=1/2 п × T=1/ [4 п × (R1+R2) × C] --- --- --- --- --- --- --- -- (6)
From formula (6) as can be seen that the frequency and passive device of the oscillator signal Osc_out of the RC oscillator
R is related with C.If we will obtain accurate frequency of oscillation, it is only necessary to which the value for adjusting resistance or capacitor can be obtained by.
Equally, the embodiment of the present invention can also obtain the oscillator signal of the RC oscillator in other embodiment
The frequency of Osc_out only and the related conclusion of passive device R and C, each electric current I1, I2, I3 and I4 are no longer equal, but at than
Example, as long as adding corresponding ratio value in corresponding formula.When the first capacitor C1 and the second capacitor C2 not
Whens equal, the C in the t of two half periods of oscillation is replaced respectively with C1 and C2.
Circuit of the embodiment of the present invention uses 2 resistance and 2 capacitors, and other parts are all by NMOS tube or PMOS tube group
At, it can be realized using CMOS technology, such as:
Each phase inverter 5 can use CMOS inverter, connected and formed with a NMOS tube by a PMOS tube.
Each NAND gate can connect to be formed with two NMOS tubes using two PMOS tube, and two PMOS tube are using in parallel
Connection type, two NMOS tubes use series connection mode, and two PMOS tube are connected in parallel on the cascaded structure of two NMOS tubes
Between drain electrode and supply voltage, two NMOS tubes are connected between the drain electrode and ground of the parallel-connection structure of two PMOS tube.
The operational amplifier 3 also can connect to be formed with PMOS tube using multiple NMOS tubes.
From the foregoing, it will be observed that circuit structure of the embodiment of the present invention simply and readily integrates on the same chip, can be good at
It is applied in SOC chip.
The channel that the embodiment of the present invention passes through the first NMOS tube mn1 in the second current path to offset generating circuit 1
Breadth length ratio setting, enable to the size of the first bias current I1 and the second bias current I2 of offset generating circuit 1 only
It is related with two resistance R1 and R2 of offset generating circuit 1 with the threshold voltage vt hn of the first NMOS tube mn1；The present invention pass through by
The threshold voltage and the first NMOS tube mn1 of the NMOS tube mn2 and mn3 of two control signal generating circuits of oscillation generating circuit 2
Threshold voltage be set as identical, enable to the frequency of the oscillator signal Osc_out of entire circuit output only with two resistance
R1 is related with R2 and two capacitor C1 and C2, eliminates supply voltage VDD and each NMOS tube or PMOS tube to oscillator signal
The influence of the frequency of Osc_out, so the frequency precision with higher of the oscillator signal Osc_out of output, and pass through adjusting
Two resistance R1 and R2 and two capacitor C1 and C2 can be achieved with the adjusting of the frequency of oscillator signal, and the frequency of oscillator signal is adjusted
It is convenient.
It is able to verify that the embodiment of the present invention can actually obtain the good oscillator signal of frequency performance by emulation experiment
Osc_out。
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of RC oscillator, which is characterized in that including offset generating circuit and oscillation generating circuit；
The offset generating circuit is for generating bias current；The offset generating circuit includes the first current path, the second electricity
Flow path and an operational amplifier, first current path include the first PMOS tube and first resistor, second electric current road
Diameter includes the second PMOS tube, second resistance and the first NMOS tube, and the source electrode of first PMOS tube and second PMOS tube is all
Connect the output end that supply voltage, grid all connect the operational amplifier；The first end connection described first of the first resistor
The drain electrode of PMOS tube and the first input end of the operational amplifier, the second end ground connection of first resistor；Second PMOS tube
Drain electrode, the grid of first NMOS tube and the first end of the second resistance link together, the of the second resistance
Two ends connect drain electrode and the second input terminal of the operational amplifier of first NMOS tube, the source electrode of first NMOS tube
Ground connection, the first input end of the operational amplifier and the second input terminal are two input terminals of reverse phase each other；
The size ratio of second bias current of the first bias current of first current path and second current path
It is determined by the ratio of the breadth length ratio of the channel of the breadth length ratio and second PMOS tube of the channel of first PMOS tube；Described
One NMOS tube works in saturation region, and the size of first bias current and second bias current is by first NMOS tube
Grid voltage, the first resistor and the second resistance value determine that the breadth length ratio of the channel of first NMOS tube is full
It is in the grid voltage of first NMOS tube in the range of positive and negative the 2% of the threshold voltage of first NMOS tube；
The oscillation generating circuit includes two mirror image circuits and two charge-discharge circuits, the first charge-discharge circuit and the first mirror image
Circuit is connected, the second charge-discharge circuit and the second mirror image circuit are connected, and first mirror image circuit generates and first biasing
The first proportional image current of electric current, second mirror image circuit generates and the second proportional mirror of first bias current
Image current；
First charge-discharge circuit includes first capacitor, the 7th PMOS tube and the 4th NMOS tube, the 7th PMOS tube and institute
The grid for stating the 4th NMOS tube all connects the second feedback signal, and the source electrode of the 7th PMOS tube connects first mirror image circuit
First image current output end, the drain electrode of the 7th PMOS tube and the 4th NMOS tube all connect the of the first capacitor
One end, the source electrode ground connection of the 4th NMOS tube, the second end ground connection of the first capacitor；
Second charge-discharge circuit includes the second capacitor, the 8th PMOS tube and the 5th NMOS tube, the 8th PMOS tube and institute
The grid for stating the 5th NMOS tube all connects the first feedback signal, and the source electrode of the 8th PMOS tube connects second mirror image circuit
Second image current output end, the drain electrode of the 8th PMOS tube and the 5th NMOS tube all connect the of second capacitor
One end, the source electrode ground connection of the 5th NMOS tube, the second end ground connection of second capacitor；
The oscillation generating circuit further includes two control signal generating circuits, and first control signal generation circuit includes third
PMOS tube and the second NMOS tube, the source electrode of the third PMOS tube connect supply voltage, the grid connection of the third PMOS tube
The grid of first PMOS tube, the third PMOS tube are connected with the drain electrode of second NMOS tube and as the first control letters
Number output end, the grid of second NMOS tube connects the first end of the first capacitor, the source electrode of second NMOS tube
Ground connection, the threshold voltage of second NMOS tube are equal to the threshold voltage of first NMOS tube, the of the first capacitor
It is low level that the voltage of one end, which is greater than the first control signal when threshold voltage of second NMOS tube, in first electricity
It is high level that the voltage of the first end of appearance, which is less than the first control signal when threshold voltage of second NMOS tube,；
Second control signal generation circuit includes the 4th PMOS tube and third NMOS tube, and the source electrode of the 4th PMOS tube connects electricity
The grid of source voltage, the 4th PMOS tube connects the grid of first PMOS tube, the 4th PMOS tube and the third
The drain electrode of NMOS tube is connected and the output end as second control signal, the grid connection of the third NMOS tube second electricity
The first end of appearance, the source electrode ground connection of the third NMOS tube, the threshold voltage of the third NMOS tube are equal to the first NMOS
The threshold voltage of pipe, when the voltage of the first end of second capacitor is greater than the threshold voltage of the third NMOS tube described in the
Two control signals are low level, when the voltage of the first end of second capacitor is less than the threshold voltage of the third NMOS tube
The second control signal is high level；
The oscillation generating circuit further includes an output circuit, and the output circuit includes 8 phase inverters and two NAND gates,
The output end of first NAND gate connects the first input end of the second NAND gate, the output end connection of second NAND gate described the
The first input end of one NAND gate；Two are in series between the first control signal and the second input terminal of first NAND gate
A phase inverter, there are two phase inverters for series connection between the second control signal and the second input terminal of second NAND gate；Institute
The output end for stating the first NAND gate passes through outputting oscillation signal after connecting with two concatenated phase inverters；Second NAND gate
Output end is by output second feedback signal that is connected with a phase inverter, and second feedback signal passes through and a phase inverter
Be connected output first feedback signal.
2. RC oscillator as described in claim 1, it is characterised in that: the channel of first PMOS tube and second PMOS tube
Breadth length ratio it is identical, first bias current and second bias current it is equal in magnitude.
3. RC oscillator as claimed in claim 2, it is characterised in that: first image current and first bias current
It is equal in magnitude, second image current and first bias current it is equal in magnitude.
4. RC oscillator as claimed in claim 1 or 2, it is characterised in that: first mirror image circuit is made of the 5th PMOS tube,
The grid of 5th PMOS tube connects the grid of first PMOS tube, the source electrode connection power supply electricity of the 5th PMOS tube
The drain electrode of pressure, the 5th PMOS tube exports first image current.
5. RC oscillator as claimed in claim 4, it is characterised in that: the channel of first PMOS tube and the 5th PMOS tube
Breadth length ratio it is identical, first bias current and first image current it is equal in magnitude.
6. RC oscillator as claimed in claim 1 or 2, it is characterised in that: second mirror image circuit is made of the 6th PMOS tube,
The grid of 6th PMOS tube connects the grid of first PMOS tube, the source electrode connection power supply electricity of the 6th PMOS tube
The drain electrode of pressure, the 6th PMOS tube exports second image current.
7. RC oscillator as claimed in claim 6, it is characterised in that: the channel of first PMOS tube and the 6th PMOS tube
Breadth length ratio it is identical, first bias current and second image current it is equal in magnitude.
8. RC oscillator as described in claim 1, it is characterised in that: the size phase of the first capacitor and second capacitor
Deng.
9. the RC oscillator as described in claim 1 or 8, it is characterised in that: by adjusting the first resistor, second electricity
The frequency of oscillator signal described in the big minor adjustment of resistance, the first capacitor and second capacitor.
10. RC oscillator as described in claim 1, it is characterised in that: the RC oscillator is integrated in same SOC chip.
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| CN107241083B (en) * | 2017-06-05 | 2020-08-04 | 上海爱信诺航芯电子科技有限公司 | High-precision self-biasing clock circuit and corresponding self-biasing circuit |
| CN109286369B (en) * | 2017-07-21 | 2020-10-09 | 珠海格力电器股份有限公司 | Voltage-controlled oscillator, integrated chip and electronic equipment |
| CN109525197B (en) * | 2018-11-28 | 2022-09-13 | 中国电子科技集团公司第四十七研究所 | High-precision RC oscillator capable of being modified and adjusted |
| CN116317951B (en) * | 2023-04-17 | 2023-08-01 | 江苏润石科技有限公司 | RC relaxation oscillator circuit |
Citations (4)
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|---|---|---|---|---|
| US5594388A (en) * | 1995-06-07 | 1997-01-14 | American Microsystems, Inc. | Self-calibrating RC oscillator |
| CN102790601A (en) * | 2012-08-08 | 2012-11-21 | 电子科技大学 | RC (resistance-capacitance) oscillator |
| CN103076830A (en) * | 2012-12-20 | 2013-05-01 | 上海宏力半导体制造有限公司 | Bandgap reference circuit |
| CN203071869U (en) * | 2013-02-21 | 2013-07-17 | 浙江商业职业技术学院 | Oscillator circuit |
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2014
- 2014-04-16 CN CN201410151448.3A patent/CN104579245B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5594388A (en) * | 1995-06-07 | 1997-01-14 | American Microsystems, Inc. | Self-calibrating RC oscillator |
| CN102790601A (en) * | 2012-08-08 | 2012-11-21 | 电子科技大学 | RC (resistance-capacitance) oscillator |
| CN103076830A (en) * | 2012-12-20 | 2013-05-01 | 上海宏力半导体制造有限公司 | Bandgap reference circuit |
| CN203071869U (en) * | 2013-02-21 | 2013-07-17 | 浙江商业职业技术学院 | Oscillator circuit |
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