CN105978560A - Programmable voltage-controlled oscillator - Google Patents
Programmable voltage-controlled oscillator Download PDFInfo
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- CN105978560A CN105978560A CN201610352340.XA CN201610352340A CN105978560A CN 105978560 A CN105978560 A CN 105978560A CN 201610352340 A CN201610352340 A CN 201610352340A CN 105978560 A CN105978560 A CN 105978560A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
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Abstract
The invention relates to a programmable voltage-controlled oscillator. The frequency adjusting range of the oscillator can be controlled and a clock signal with the 50% of duty ratio can be outputted. The oscillator comprises a voltage-current conversion circuit, a current matching circuit, a current mirror image circuit, a ring oscillator circuit, a programmable resistor array, a programmable capacitor array and an output buffer unit circuit.
Description
Technical field
The present invention relates to a kind of integrated circuit controller, be specifically related to a kind of voltage controlled oscillator able to programme.
Background technology
Voltage controlled oscillator (VCO, Voltage-controlled Oscillator) is phaselocked loop (PLL, Phase-locked Loop) and data
The important module such as clock recovery (CDR, Clock and Data Recovery) circuit.Its effect is that outside input controls voltage-regulation agitator
Frequency of oscillation, makes oscillator output frequencies present the periodic signal of increasing or decreasing with the change controlling voltage.
Agitator has two kinds of conventional structures, LC oscillator (LC Oscillator) and ring oscillator (Ring Oscillator).LC shakes
Swinging device and mainly produced the clock signal of fixed frequency by LC resonance, frequency of oscillation is by electric capacity, inductance value discharge and recharge impact.But by technique skill
Art is limited, and electric capacity, inductance area occupied are big, is unfavorable for Integrated design, and integrated capacitance, inductance value adjustable extent are smaller, and the electric capacity of off-chip,
Inductance is easily by such environmental effects.
Ring oscillator is then the clock signal being produced fixed frequency by the Time-delayed Feedback of delay cell.Ring oscillator is by several identical delays
Unit composition feedback control loop, determines the frequency of oscillation of agitator the time delay of each delay cell, the most permissible by controlling the time delay of delay cell
The frequency of oscillation of regulation agitator.
Ring oscillator delay unit has two types, and a kind of delay unit being amplifier and forming, as proposed in patent CN 102723912 A
The delay cell of the differential amplifier arrangements that a kind of broadband annular oscillator is used；The delay cell that another kind is made up of phase inverter, such as patent CN
The ring oscillator of a kind of frequency stable proposed in 104300971 A, the delay cell being made up of phase inverter exactly used.Time delay is subject to
The discharge and recharge time of circuit load electric capacity determines, changing time delay can be by changing the discharge and recharge time constant of circuit or by changing discharge and recharge
Electric current realizes, and discharge and recharge time constant is obtained by the regulation load capacitance of delay unit, resistance value, and charging and discharging currents can be by controlling tail electricity
Stream source overdrive voltage obtains.
The present invention provides a kind of loop configuration voltage controlled oscillator able to programme, and circuit structure easily realizes and wideband frequency range of accommodation and PLC technology,
It is applicable to medium-high frequency clock circuit.
The delay cell of the present invention is used a kind of fully differential delay cell structure being different from amplifier and phase inverter, the time delay of this delay cell
Mechanism is the discharge and recharge time of load capacitance.The frequency regulation of the agitator of the present invention is by controlling the realization of delay cell size of current.The present invention's
Achieve the effective control to frequency-tuning range, the different frequency area requirement of different clock circuits can be met.The control mode of the present invention has two
Kind, a kind of load capacitance being to control delay cell；Another kind is to control the resistance in current/charge-voltage convertor (V-I), and then controls voltage
Proportionate relationship corresponding with electric current.
Summary of the invention
Present invention aim at providing a kind of voltage controlled oscillator able to programme, frequency-tuning range is able to programme and output duty cycle is the clock signal of 50%.
The voltage controlled oscillator able to programme that the present invention provides includes current/charge-voltage convertor, current matching circuit, current mirror circuit, ring oscillation
Device circuit and output buffer cell circuit.
The control signal of input is converted into the first current source by described current/charge-voltage convertor, then produces the by described current matching circuit
Two current sources；First current source and the second current source mirror image are supplied to described ring oscillator circuit by described current mirror circuit；Described annular
Pierce circuit produces time delay by delay cell load capacitance discharge and recharge, and feedback is produced from Induced Oscillation, and output differential clock signal is supplied to described
Output buffer cell circuit；Differential vibrating signal is compared by described output buffer cell circuit, shaping, and output duty cycle is the cycle of 50%
Clock signal.
Described current/charge-voltage convertor includes two PMOS, a resistance and an operational amplifier A 1, the source of the first PMOS MP1
Pole meets power vd D；The grid of the first PMOS MP1 connects with the outfan of operational amplifier A 1, the drain electrode of the first PMOS MP1 and second
The source electrode of PMOS MP2 connects, and the grid of the second PMOS MP2 connects offset signal Vb1 of outside reference source input；Second PMOS MP2 leakage
Pole, one end of zero resistance device R0 are connected with the normal phase input end Vp of operational amplifier A 1, the other end ground connection of zero resistance device R0；Computing is put
Control signal Vctrl of the outside input of anti-phase input termination of big device A1.
Described current matching circuit includes two PMOS and two NMOS tube, the grid of the 4th PMOS MP4 and current/charge-voltage convertor
In the grid of the first PMOS MP1 connect, form image current source circuit；The source electrode of the 3rd PMOS meets power vd D, the 3rd PMOS
Drain electrode connects with the source electrode of the 3rd PMOS MP3, and the grid of the second PMOS connects offset signal Vb1 of outside reference source input；3rd PMOS
The drain electrode of the drain electrode of MP3, the grid of the second NMOS tube MN2 and the first NMOS tube MN1 connects；The grid of the first NMOS tube MN1 and outside reference
Offset signal Vb2 of source input connects, and the source electrode of the first NMOS tube MN1 connects the drain electrode of the second NMOS tube MN2, the source of the second NMOS tube MN2
Pole ground connection.
Described current mirror circuit I3 includes three PMOS and three NMOS tube, the source electrode of the 5th PMOS MP5, the 6th PMOS MP6
Source electrode and the source electrode of the 7th PMOS MP7 meet power vd D, the grid of the 5th PMOS MP5, the grid and the 7th of the 6th PMOS MP6
The grid of PMOS MP7 connects with the grid of the first PMOS MP1 in current/charge-voltage convertor；The drain electrode and first of the 4th PMOS P4
The input Ip of delay cell TD1 connects, and the drain electrode of the 5th PMOS P5 is connected with the input Ip of the second delay cell TD2, the 6th PMOS
The drain electrode of pipe is connected with the input Ip of the 3rd delay cell TD2；The source electrode of the 3rd NMOS tube MN3, the source electrode of the 4th NMOS tube MN4 and
The source ground of five NMOS tube MN5, the grid of the 3rd NMOS tube MN3, the grid of the 4th NMOS tube MN4 and the grid of the 5th NMOS tube MN5
It is connected with the grid of the second NMOS tube MN2 in current matching circuit；The drain electrode of the 3rd NMOS tube MN3 and the input of the first delay cell TD1
In connects, and the drain electrode of the 4th NMOS tube MN4 is connected with the input In of the second delay cell TD2, the drain electrode and the 3rd of the 5th NMOS tube MN5
The input In of delay cell TD3 connects.
Described ring oscillator circuit I4 includes three identical delay cells, and each delay cell includes two PMOS, two NMOS tube
With an electric capacity, the source electrode of the 8th PMOS MP8 source electrode and the 9th PMOS MP9 is as the charging current input port Ip of this delay cell；The
The grid of eight PMOS MP8 as the in-phase input end V+ of this delay cell, anti-phase defeated as this delay cell of the grid of the 9th PMOS MP9
Enter to hold V-；The drain electrode of the 8th PMOS MP8, the drain electrode of the 7th NMOS tube MN7, the grid of the 6th NMOS tube MN6 and one end of capacitor C
Connect, the drain electrode of the 9th PMOS MP9, the drain electrode of the 6th NMOS tube MN6, the grid of the 7th NMOS tube MN7 and the other end of capacitor C
Connect；The source electrode of the 7th NMOS tube MN7 and the source electrode of the 6th NMOS tube MN6 are used as the discharge current output port In of this delay cell.
Described output buffer cell circuit I 5 includes an amplifier and two phase inverters, and the second amplifier A2 is used as comparator, the second amplifier
The in-phase input end Vp of A2 meets the In-phase output signal Vout+ of ring oscillator, the inverting input Vp of the second amplifier A2 connects ring oscillator
Reversed-phase output signal Vout-；The outfan O of the second amplifier A2 connects the input of the first phase inverter INV1, the output of the first phase inverter INV1
Terminating the input of the second phase inverter INV2, the outfan of the second phase inverter is as final clock signal output terminal mouth CLk.
Further, the adjustable frequency scope of voltage controlled oscillator is controlled by the present invention, it is achieved mode is to control in current/charge-voltage convertor
Electric resistance array and the capacitor array controlled in agitator delay cell.Specific practice is as follows:
1. the zero resistance device R0 in current/charge-voltage convertor is replaced with PLC technology electric resistance array, electric resistance array by several resistance R1,
R2, R3 ..., Rn series connection, respectively programmable switch U1, U2, U3 ..., a Un in parallel on the resistance nodes of series connection, as at resistance R1
Upper paralleling switch U1, paralleling switch U2 on resistance R2, the rest may be inferred, paralleling switch Un on resistance Rn；Then former with data selector
Reason controls switch conduction and disconnection, and when the selected conducting of Un, the resistance accessing circuit is maximum；And when the selected conducting of U1, access circuit
Resistance is minimum.
2. the capacitor C in agitator delay cell is replaced with PLC technology capacitor array, capacitor array by several electric capacity C1, C2 ...,
Cn is in parallel, and connect on shunt capacitance programmable switch D1, D2 ..., a Dn respectively, such as tandem tap D1 on the capacitor cl, at electricity
Tandem tap D2 on container C2, the rest may be inferred, tandem tap Dn on capacitor Cn；Then programming Control switch D1, D2 ..., Dn
Conducting and disconnection, switch conduction is i.e. that corresponding capacitor accesses circuit, switches off the capacitor being i.e. corresponding and does not accesses circuit.
The voltage controlled oscillator able to programme of the present invention has the advantage that
1. circuit structure is simple, and CMOS technology can be used to realize, easy of integration, low cost；
2. Control of Voltage frequency tuning linearity is good, applied range；
3. delay cell uses fully differential structure, utilizes the poor sub-signal of comparator, produces single-ended clock signal, and dutycycle is 50%；
4. frequency-tuning range PLC technology, can be applicable to medium-high frequency clock circuit module.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the voltage controlled oscillator able to programme of the present invention；
Fig. 2 is the electrical block diagram of the voltage controlled oscillator of the present invention；
Fig. 3 is the delay unit circuit figure in Fig. 2；
Fig. 4 is the voltage controlled oscillator groundwork sequential chart of the present invention；
Fig. 5 is the schematic diagram of the programmable resistor array of the present invention；
Fig. 6 is the programmable capacitor array schematic diagram of delay cell of the present invention；
Fig. 7 is the example operation result schematic diagram of voltage controlled oscillator able to programme.
Detailed description of the invention
Fig. 1 is the structured flowchart of the voltage controlled oscillator able to programme of embodiments of the invention.As it is shown in figure 1, voltage controlled oscillator able to programme include voltage-
Current converter circuit I1, current matching circuit I2, current mirror circuit I3, ring oscillator circuit I4 and output buffer cell circuit I 5.
Fig. 2 is the circuit structure diagram of the voltage controlled oscillator able to programme of the embodiment of the present invention, and described current/charge-voltage convertor I1 includes two PMOS
Pipe, a resistance and an operational amplifier A 1, the source electrode of the first PMOS MP1 meets power vd D；The grid of the first PMOS MP1 and computing
The outfan of amplifier A1 connects, and the drain electrode of the first PMOS MP1 is connected with the source electrode of the second PMOS MP2, the grid of the second PMOS MP2
Pole connects offset signal Vb1 of outside reference source input；Second PMOS MP2 drain electrode, one end of zero resistance device R0 and operational amplifier A 1 are just
Phase input Vp connects, the other end ground connection of zero resistance device R0；Control signal Vctrl of the outside input of anti-phase input termination of operational amplifier A 1.
Described current matching circuit I2 includes two PMOS and two NMOS tube, the grid of the 4th PMOS MP4 and Voltage-current conversion
The grid of the first PMOS MP1 in circuit connects, and forms image current source circuit；The source electrode of the 4th PMOS MP4 meets power vd D, and the 4th
The drain electrode of PMOS MP4 connects with the source electrode of the 3rd PMOS MP3, and the grid of the 3rd PMOS MP3 connects the offset signal of outside reference source input
Vb1；The drain electrode of the drain electrode of the 3rd PMOS MP3, the grid of the second NMOS tube MN2 and the first NMOS tube MN1 connects；First NMOS tube MN1
Offset signal Vb2 that inputs with outside reference source of grid connect, the source electrode of the first NMOS tube MN1 connects the drain electrode of the second NMOS tube MN2, second
The source ground of NMOS tube MN2.
Described current mirror circuit I3 includes three PMOS and three NMOS tube, the source electrode of the 5th PMOS MP5, the 6th PMOS MP6
Source electrode and the source electrode of the 7th PMOS MP7 meet power vd D, the grid of the 5th PMOS MP5, the grid and the 7th of the 6th PMOS MP6
The grid of PMOS MP7 connects with the grid of the first PMOS MP1 in current/charge-voltage convertor；The drain electrode and first of the 4th PMOS P4
The input Ip of delay cell TD1 connects, and the drain electrode of the 5th PMOS P5 is connected with the input Ip of the second delay cell TD2, the 6th PMOS
The drain electrode of pipe is connected with the input Ip of the 3rd delay cell TD2；The source electrode of the 3rd NMOS tube MN3, the source electrode of the 4th NMOS tube MN4 and
The source ground of seven NMOS tube MN7, the grid of the 3rd NMOS tube MN3, the grid of the 4th NMOS tube MN4 and the grid of the 7th NMOS tube MN7
It is connected with the grid of the second NMOS tube MN2 in current matching circuit；The drain electrode of the 3rd NMOS tube MN3 and the input of the first delay cell TD1
In connects, and the drain electrode of the 4th NMOS tube MN4 is connected with the input In of the second delay cell TD2, the drain electrode and the 3rd of the 7th NMOS tube MN7
The input In of delay cell TD2 connects.
Described ring oscillator circuit I4 includes three identical delay cells, and Fig. 3 is that the annular voltage controlled oscillator of the embodiment of the present invention postpones single
Unit, as it is shown on figure 3, each delay cell includes two PMOS, two NMOS tube and an electric capacity, the 8th PMOS MP8 source electrode and
The source electrode of nine PMOS MP9 is as the charging current input port Ip of this delay cell；The grid of the 8th PMOS MP8 is as this delay cell
In-phase input end V+, the grid of the 9th PMOS MP9 is as the inverting input V-of this delay cell；The drain electrode of the 8th PMOS MP8,
The drain electrode of seven NMOS tube MN7, the grid of the 6th NMOS tube MN6 are connected with one end of capacitor C, the drain electrode of the 9th PMOS MP9, the 6th
The drain electrode of NMOS tube MN6, the grid of the 7th NMOS tube MN7 are connected with the other end of capacitor C；The source electrode and the 6th of the 7th NMOS tube MN7
The source electrode of NMOS tube MN6 is used as the discharge current output port In of this delay cell.
Described output buffer cell I5 includes an amplifier and two phase inverters, and the second amplifier A2 is used as comparator, the second amplifier A2
In-phase input end Vp meet the In-phase output signal Vout+, the inverting input Vp of the second amplifier A2 of ring oscillator and connect the anti-of ring oscillator
Phase output signal Vout-；The outfan O of the second amplifier A2 connects the input of the first phase inverter INV1, the output termination of the first phase inverter INV1
The input of the second phase inverter INV2, the outfan of the second phase inverter INV2 is used as final clock signal output terminal mouth CLk.
Fig. 4 is the voltage controlled oscillator groundwork sequential chart of the present invention, as shown in Figure 4, and voltage controlled oscillator output differential clock signal Vout+ and Vout-,
Then utilize comparator that differential clock signal changes into single-ended clock signal, with reverser INV1 and INV2, clock signal is carried out shaping,
Whole output duty cycle is the square-like clock signal of 50%.
Further, the adjustable frequency scope of voltage controlled oscillator is controlled by the present invention, it is achieved mode is to control in current/charge-voltage convertor
Electric resistance array and the capacitor array controlled in agitator delay cell.
As it is shown in figure 5, the zero resistance device R0 in current/charge-voltage convertor is replaced with PLC technology electric resistance array I6, if electric resistance array by
Dry resistance R1, R2, R3 ..., Rn series connection, respectively programmable switch U1, U2, U3 ..., a Un in parallel on the resistance nodes of series connection,
Such as paralleling switch U1 on resistance R1, paralleling switch U2 on resistance R2, the rest may be inferred, paralleling switch Un on resistance Rn；Then use
Data selector principle controls switch conduction and disconnection, and when the selected conducting of Un, the resistance accessing circuit is maximum；And when the selected conducting of U1,
The resistance accessing circuit is minimum.
As shown in Figure 6, by agitator delay cell capacitor replace PLC technology capacitor array I7, capacitor array by several electric capacity C1,
C2 ..., Cn are in parallel, and connect on shunt capacitance programmable switch D1, D2 ..., a Dn respectively, such as tandem tap on the capacitor cl
D1, on the capacitor c 2 tandem tap D2, the rest may be inferred, tandem tap Dn on capacitor Cn；Then programming Control switch D1, D2 ...,
The conducting of Dn and disconnection, switch conduction is i.e. that corresponding capacitor accesses circuit, switches off the capacitor being i.e. corresponding and does not accesses circuit.
Fig. 7 is the example operation result schematic diagram of voltage controlled oscillator able to programme, as it is shown in fig. 7, the present embodiment is to postpone voltage controlled oscillator able to programme
The load capacitance array of unit is programmed controlling, and agitator regulating frequency is transformed into linear relationship with control voltage, its oscillator output signal
Mid frequency increases with capacitance and reduces, and reaches to control frequency size and the requirement of scope.
The invention is not restricted to specific embodiment described here, various obvious change can be carried out based on present inventive concept to those skilled in the art
Change, readjust and substitute all without departing from protection scope of the present invention.Therefore, the present invention has simply been carried out the most specifically by above example
Bright, but the present invention is not limited only to above example, without departing from the inventive concept, it is also possible to include other Equivalent embodiments more,
The scope of the present invention is determined by scope of the appended claims.
Claims (8)
1. a voltage controlled oscillator able to programme, it is characterised in that: described pressuring controlling oscillator frequency range of accommodation is controlled and output duty cycle be 50% time
Clock signal；Described voltage controlled oscillator includes current/charge-voltage convertor, current matching circuit, current mirror circuit, ring oscillator circuit and defeated
Go out buffer cell circuit；The control signal of input is converted into the first current source by described current/charge-voltage convertor, then by described electric current
Distribution road produces the second current source；First current source and the second current source mirror image are supplied to described ring oscillator electricity by described current mirror circuit
Road；Described ring oscillator circuit produces time delay by delay cell load capacitance discharge and recharge, and feedback is produced from Induced Oscillation, exports differential clock signal
It is supplied to described output buffer cell circuit；Differential vibrating signal is compared by described output buffer cell circuit, shaping, output duty cycle
It it is the cycle clock signal of 50%.
Voltage controlled oscillator able to programme the most according to claim 1, is characterized in that: described current/charge-voltage convertor include two PMOS,
One resistance and an operational amplifier A 1, the source electrode of the first PMOS MP1 meets power vd D；The grid of the first PMOS MP1 and operation amplifier
The outfan of device A1 connects, and the drain electrode of the first PMOS MP1 is connected with the source electrode of the second PMOS MP2, and the grid of the second PMOS MP2 connects
Offset signal Vb1 of outside reference source input；Second PMOS MP2 drains, one end of zero resistance device R0 is defeated with the positive of operational amplifier A 1
Enter and hold Vp to connect, the other end ground connection of zero resistance device R0；Control signal Vctrl of the outside input of anti-phase input termination of operational amplifier A 1.
Voltage controlled oscillator able to programme the most according to claim 1 and 2, is characterized in that: described current matching circuit includes two PMOS
With two NMOS tube, the grid of the 4th PMOS MP4 connects with the grid of the first PMOS MP1 in current/charge-voltage convertor, forms mirror
Image current source circuit；The source electrode of the 3rd PMOS meets power vd D, and the drain electrode of the 3rd PMOS connects with the source electrode of the 3rd PMOS MP3, and second
The grid of PMOS connects offset signal Vb1 of outside reference source input；The drain electrode of the 3rd PMOS MP3, the grid of the second NMOS tube MN2 and
The drain electrode of one NMOS tube MN1 connects；Offset signal Vb2 that the grid of the first NMOS tube MN1 inputs with outside reference source connects, a NMOS
The source electrode of pipe MN1 connects the drain electrode of the second NMOS tube MN2, the source ground of the second NMOS tube MN2.
4. according to the voltage controlled oscillator able to programme according to any one of claim 1-3, it is characterized in that: described current mirror circuit I3 includes three
Individual PMOS and three NMOS tube, the source electrode of the 5th PMOS MP5, the source electrode of the 6th PMOS MP6 and the source electrode of the 7th PMOS MP7
Meeting power vd D, the grid of the grid of the 5th PMOS MP5, the grid of the 6th PMOS MP6 and the 7th PMOS MP7 turns with voltage-to-current
The grid changing the first PMOS MP1 in circuit connects；The drain electrode of the 4th PMOS P4 is connected with the input Ip of the first delay cell TD1,
The drain electrode of the 5th PMOS P5 is connected with the input Ip of the second delay cell TD2, the drain electrode of the 6th PMOS and the 3rd delay cell TD2
Input Ip connects；The source electrode of the 3rd NMOS tube MN3, the source electrode of the 4th NMOS tube MN4 and the source ground of the 5th NMOS tube MN5, the 3rd
The grid of the grid of NMOS tube MN3, the grid of the 4th NMOS tube MN4 and the 5th NMOS tube MN5 and the second NMOS tube in current matching circuit
The grid of MN2 connects；The drain electrode of the 3rd NMOS tube MN3 is connected with the input In of the first delay cell TD1, the drain electrode of the 4th NMOS tube MN4
Being connected with the input In of the second delay cell TD2, the drain electrode of the 5th NMOS tube MN5 is connected with the input In of the 3rd delay cell TD3.
5. according to the voltage controlled oscillator able to programme according to any one of claim 1-4, it is characterized in that: described ring oscillator circuit I4 includes
Three identical delay cells, each delay cell includes two PMOS, two NMOS tube and an electric capacity, the 8th PMOS MP8 source electrode
With the source electrode of the 9th PMOS MP9 as the charging current input port Ip of this delay cell；The grid of the 8th PMOS MP8 is as this delay list
The in-phase input end V+ of unit, the grid of the 9th PMOS MP9 is as the inverting input V-of this delay cell；The drain electrode of the 8th PMOS MP8,
The drain electrode of the 7th NMOS tube MN7, the grid of the 6th NMOS tube MN6 are connected with one end of capacitor C, the drain electrode of the 9th PMOS MP9,
The drain electrode of six NMOS tube MN6, the grid of the 7th NMOS tube MN7 are connected with the other end of capacitor C；The source electrode of the 7th NMOS tube MN7 and
The source electrode of six NMOS tube MN6 is used as the discharge current output port In of this delay cell.
6. according to the voltage controlled oscillator able to programme according to any one of claim 1-5, it is characterized in that: described output buffer cell circuit I 5 is wrapped
Including an amplifier and two phase inverters, the second amplifier A2 is used as comparator, and the in-phase input end Vp of the second amplifier A2 connects ring oscillator
In-phase output signal Vout+, the inverting input Vp of the second amplifier A2 meets the reversed-phase output signal Vout-of ring oscillator；Second amplifies
The outfan 0 of device A2 connects the input of the first phase inverter INV1, the input of the output termination second phase inverter INV2 of the first phase inverter INV1,
The outfan of the second phase inverter is as final clock signal output terminal mouth CLk.
7. according to the voltage controlled oscillator able to programme according to any one of claim 2-6, it is characterized in that: by the 0th in current/charge-voltage convertor
Resistor R0 replaces with PLC technology electric resistance array, and electric resistance array is by several resistance R1, R2, R3 ..., Rn series connection, respectively in series connection
Resistance nodes in parallel programmable switch U1, U2, U3 ..., a Un, such as paralleling switch U1 on resistance R1, on resistance R2 also
Connection switch U2, the rest may be inferred, paralleling switch Un on resistance Rn；Then control switch conduction and disconnection by data selector principle, work as Un
During selected conducting, the resistance accessing circuit is maximum；And when the selected conducting of U1, the resistance accessing circuit is minimum.
8. according to the voltage controlled oscillator able to programme according to any one of claim 5-7, it is characterized in that: by the capacitor C in agitator delay cell
Replacing with PLC technology capacitor array, capacitor array, by several electric capacity C1, C2 ..., Cn parallel connection, is connected one respectively on shunt capacitance
Programmable switch D1, D2 ..., Dn, such as tandem tap D1, on the capacitor c 2 tandem tap D2 on the capacitor cl, the rest may be inferred,
Tandem tap Dn on capacitor Cn；Then programming Control switch D1, D2 ..., the conducting of Dn and disconnection, switch conduction is i.e. corresponding capacitor
Access circuit, switch off the capacitor being i.e. corresponding and do not access circuit.
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| CN201610352340.XA CN105978560A (en) | 2016-05-25 | 2016-05-25 | Programmable voltage-controlled oscillator |
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| CN107863950A (en) * | 2017-12-11 | 2018-03-30 | 许昌学院 | A kind of doubleway output frequency-adjustable clock-signal generator |
| CN107896092A (en) * | 2017-12-18 | 2018-04-10 | 长沙景嘉微电子股份有限公司 | A kind of circuit of achievable accurate frequency modulation for relaxor |
| CN107979371A (en) * | 2017-12-28 | 2018-05-01 | 上海先基半导体科技有限公司 | A kind of phaselocked loop and its voltage controlled oscillator |
| CN108155891A (en) * | 2017-12-22 | 2018-06-12 | 中国电子科技集团公司第五十四研究所 | A kind of clock generation circuit |
| CN109245724A (en) * | 2018-07-24 | 2019-01-18 | 北京时代民芯科技有限公司 | A kind of adaptive-biased broadband voltage controlled pierce circuit |
| CN109428747A (en) * | 2017-08-25 | 2019-03-05 | 展讯通信（上海）有限公司 | Local oscillator bandwidth adjusting method, receiver, computer media and system |
| CN109639270A (en) * | 2018-12-07 | 2019-04-16 | 上海安路信息科技有限公司 | A kind of voltage-controlled oscillator circuit |
| CN109962696A (en) * | 2017-12-25 | 2019-07-02 | 北京同方微电子有限公司 | A kind of pierce circuit that duty ratio is controllable |
| CN110277992A (en) * | 2019-05-30 | 2019-09-24 | 芯创智（北京）微电子有限公司 | A kind of Semi-digital phaselocked loop of no bias current |
| CN110365294A (en) * | 2019-06-28 | 2019-10-22 | 西安紫光国芯半导体有限公司 | The frequency expansion method of delay cell, voltage controlled oscillator and voltage controlled oscillator |
| CN110460308A (en) * | 2019-08-15 | 2019-11-15 | 电子科技大学 | A kind of ring voltage-controlled oscillator circuit of wide scope |
| CN111181491A (en) * | 2019-12-31 | 2020-05-19 | 成都锐成芯微科技股份有限公司 | Clock generating circuit |
| CN111611535A (en) * | 2019-02-26 | 2020-09-01 | 北京知存科技有限公司 | Anti-process deviation analog vector-matrix multiplication circuit |
| CN111865305A (en) * | 2020-08-08 | 2020-10-30 | 北京百瑞互联技术有限公司 | Frequency-adjustable ring oscillator with level conversion |
| CN111953343A (en) * | 2020-09-07 | 2020-11-17 | 北京中科芯蕊科技有限公司 | Digital control subthreshold ring oscillator |
| CN112420090A (en) * | 2019-08-20 | 2021-02-26 | 美光科技公司 | Apparatus and method for voltage dependent delay |
| CN113054997A (en) * | 2019-12-26 | 2021-06-29 | 吉林大学 | Quick locking delay phase-locked loop |
| CN113472349A (en) * | 2021-07-29 | 2021-10-01 | 上海华力微电子有限公司 | Voltage controlled oscillator and phase locked loop |
| CN115021726A (en) * | 2022-05-10 | 2022-09-06 | 上海韬润半导体有限公司 | Clock buffer circuit and analog-to-digital converter |
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Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109428747A (en) * | 2017-08-25 | 2019-03-05 | 展讯通信（上海）有限公司 | Local oscillator bandwidth adjusting method, receiver, computer media and system |
| CN107863950A (en) * | 2017-12-11 | 2018-03-30 | 许昌学院 | A kind of doubleway output frequency-adjustable clock-signal generator |
| CN107863950B (en) * | 2017-12-11 | 2023-10-27 | 许昌学院 | Dual-output frequency-adjustable clock signal generator |
| CN107896092A (en) * | 2017-12-18 | 2018-04-10 | 长沙景嘉微电子股份有限公司 | A kind of circuit of achievable accurate frequency modulation for relaxor |
| CN108155891A (en) * | 2017-12-22 | 2018-06-12 | 中国电子科技集团公司第五十四研究所 | A kind of clock generation circuit |
| CN109962696A (en) * | 2017-12-25 | 2019-07-02 | 北京同方微电子有限公司 | A kind of pierce circuit that duty ratio is controllable |
| CN107979371A (en) * | 2017-12-28 | 2018-05-01 | 上海先基半导体科技有限公司 | A kind of phaselocked loop and its voltage controlled oscillator |
| CN107979371B (en) * | 2017-12-28 | 2024-03-22 | 上海先基半导体科技有限公司 | Phase-locked loop and voltage-controlled oscillator thereof |
| CN109245724B (en) * | 2018-07-24 | 2022-09-27 | 北京时代民芯科技有限公司 | Self-adaptive bias wide-frequency voltage-controlled oscillator circuit |
| CN109245724A (en) * | 2018-07-24 | 2019-01-18 | 北京时代民芯科技有限公司 | A kind of adaptive-biased broadband voltage controlled pierce circuit |
| CN109639270B (en) * | 2018-12-07 | 2021-07-20 | 上海安路信息科技股份有限公司 | Voltage controlled oscillator circuit |
| CN109639270A (en) * | 2018-12-07 | 2019-04-16 | 上海安路信息科技有限公司 | A kind of voltage-controlled oscillator circuit |
| CN111611535A (en) * | 2019-02-26 | 2020-09-01 | 北京知存科技有限公司 | Anti-process deviation analog vector-matrix multiplication circuit |
| CN110277992A (en) * | 2019-05-30 | 2019-09-24 | 芯创智（北京）微电子有限公司 | A kind of Semi-digital phaselocked loop of no bias current |
| CN110365294A (en) * | 2019-06-28 | 2019-10-22 | 西安紫光国芯半导体有限公司 | The frequency expansion method of delay cell, voltage controlled oscillator and voltage controlled oscillator |
| CN110460308A (en) * | 2019-08-15 | 2019-11-15 | 电子科技大学 | A kind of ring voltage-controlled oscillator circuit of wide scope |
| CN110460308B (en) * | 2019-08-15 | 2023-03-24 | 电子科技大学 | Wide-range annular voltage-controlled oscillator circuit |
| CN112420090A (en) * | 2019-08-20 | 2021-02-26 | 美光科技公司 | Apparatus and method for voltage dependent delay |
| CN113054997A (en) * | 2019-12-26 | 2021-06-29 | 吉林大学 | Quick locking delay phase-locked loop |
| CN113054997B (en) * | 2019-12-26 | 2022-08-19 | 吉林大学 | Quick locking delay phase-locked loop |
| CN111181491B (en) * | 2019-12-31 | 2023-07-28 | 成都锐成芯微科技股份有限公司 | Clock generating circuit |
| CN111181491A (en) * | 2019-12-31 | 2020-05-19 | 成都锐成芯微科技股份有限公司 | Clock generating circuit |
| CN111865305A (en) * | 2020-08-08 | 2020-10-30 | 北京百瑞互联技术有限公司 | Frequency-adjustable ring oscillator with level conversion |
| CN111865305B (en) * | 2020-08-08 | 2023-11-03 | 北京百瑞互联技术股份有限公司 | Frequency-adjustable ring oscillator with power conversion |
| CN111953343A (en) * | 2020-09-07 | 2020-11-17 | 北京中科芯蕊科技有限公司 | Digital control subthreshold ring oscillator |
| CN111953343B (en) * | 2020-09-07 | 2023-05-30 | 北京中科芯蕊科技有限公司 | Digital control subthreshold ring oscillator |
| CN113472349A (en) * | 2021-07-29 | 2021-10-01 | 上海华力微电子有限公司 | Voltage controlled oscillator and phase locked loop |
| CN115021726B (en) * | 2022-05-10 | 2023-02-17 | 上海韬润半导体有限公司 | Clock buffer circuit and analog-to-digital converter |
| CN115021726A (en) * | 2022-05-10 | 2022-09-06 | 上海韬润半导体有限公司 | Clock buffer circuit and analog-to-digital converter |
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