CN107659302A - Level shifting circuit with pre-amplification - Google Patents
Level shifting circuit with pre-amplification Download PDFInfo
- Publication number
- CN107659302A CN107659302A CN201710751152.9A CN201710751152A CN107659302A CN 107659302 A CN107659302 A CN 107659302A CN 201710751152 A CN201710751152 A CN 201710751152A CN 107659302 A CN107659302 A CN 107659302A
- Authority
- CN
- China
- Prior art keywords
- node
- drain electrode
- source electrode
- grid
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
Abstract
The present invention relates to integrated circuit fields, to complete the conversion of the level signal of multi-power system so that very low level signal can be converted into high level signal, the present invention, the level shifting circuit with pre-amplification, and structure is as follows：It is MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8 respectively to have 8 PMOSs, it is MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 and two phase inverters INV1, INV2 respectively to have 8 NMOS tubes, wherein MP1, MP2, MN2, MP3, MP4, MN5, MP5, MP6, MP7, MP8, MN7 and MN8 are the metal-oxide-semiconductors for belonging to thick grating oxide layer, working power is that high power supply voltage VDDH, MN1, MN3, MN4, MN6 are the metal-oxide-semiconductors for belonging to thin gate oxide.Present invention is mainly applied to IC design manufacture.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to the level signal circuit design of multivoltage source system.Tool
Body is said, is related to the level shifting circuit with pre-amplification.
Background technology
Voltage source is not unique in the SOC of complexity, and power supply can be different used in disparate modules circuit, different
The obtained amplitude of level signal of supply voltage be different, the level signal that low supply voltage obtains is very low, and level
Too low signal will have an impact to the propagation of signal, so level shifting circuit is as essential in multi-power system
Interface circuit.Traditional level shifting circuit is the method based on differential cascade voltage switch, although can be by low level signal
High level signal is converted to, but this structure will fail when the level signal of input is in a relatively low level.For
Solve the problems, such as to be converted into high level signal compared with low level signal in multi-power system, the present invention propose it is a kind of have in advance put
Big level shifting circuit, the circuit can complete conversion of the low level signal to high level signal in multi-power system.
The content of the invention
For overcome the deficiencies in the prior art, the present invention is directed to propose a kind of new level shifting circuit, can be completed more electric
The level signal conversion of source system so that very low level signal can be converted into high level signal, in order to level signal
Subsequent propagation and processing.The technical solution adopted by the present invention is that have the level shifting circuit of pre-amplification, and structure is as follows：There are 8
PMOS is MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8 respectively, have 8 NMOS tubes be respectively MN1, MN2, MN3, MN4,
MN5, MN6, MN7, MN8 and two phase inverters INV1, INV2, wherein MP1, MP2, MN2, MP3, MP4, MN5, MP5, MP6,
MP7, MP8, MN7 and MN8 are the metal-oxide-semiconductors for belonging to thick grating oxide layer, working power be high power supply voltage VDDH, MN1, MN3, MN4,
MN6 is the metal-oxide-semiconductor for belonging to thin gate oxide, and working power is low supply voltage VDDL；Phase inverter INV1 input termination input
Signal IN, output termination INB, the power supply of work is VDDL；Phase inverter INV2 input terminated nodes QB, output termination input
OUT, working power VDDH；NMOS tube MN1 grid meets input signal IN, and source electrode connects MN2 drain electrode, and drain electrode meets node A, serves as a contrast
Bottom is grounded；NMOS tube NM2 grid connects node QB, source electrode and Substrate ground, and drain electrode connects NM1 source electrode；NMOS tube MN3 grid
INB, source electrode and Substrate ground are connect, drain electrode meets node B；NMOS tube MN4 grid meets INB, and source electrode connects MN5 drain electrode, and drain electrode connects
Node C, Substrate ground；NMOS tube MN5 grid connects node Q, source electrode and Substrate ground, and drain electrode connects MN4 source electrode；NMOS tube
MN6 grid connects IN, source electrode and Substrate ground, and drain electrode meets node D；NMOS tube MN7 grid meets node D, and source electrode and substrate connect
Ground, drain electrode meet node Q；NMOS tube MN8 grid connects node B, source electrode and Substrate ground, and drain electrode meets node QB；PMOS MP1's
Grid and drain electrode connect node A, source electrode and Substrate ground；PMOS MP2 grid connects node A, source electrode and Substrate ground, and drain electrode connects
Node B；PMOS MP3 grid and drain electrode connect node C, source electrode and Substrate ground；PMOS MP4 grid connects node C, source electrode
And Substrate ground, drain electrode meet node D；PMOS MP5 grid connects node QB, source electrode and Substrate ground, and drain electrode connects MP6 source
Pole；PMOS MP6 grid meets node D, and source electrode connects MP5 drain electrode, and drain electrode connects node Q, Substrate ground；PMOS MP7 grid
Pole connects node Q, source electrode and Substrate ground, and drain electrode connects MP8 drain electrode；PMOS MP8 grid meets node B, and source electrode connects MP7 leakage
Pole, drain electrode connect node QB, Substrate ground.
MN1 and MN2 forms the high level logic error correction circuit of pre-amplification, and MN4 and MN5 form the low level of pre-amplification
Logical error circuit for rectifying, MP1 and MP2 and MP3 and MP4 have respectively constituted the current mirror of two pre-amplifications, and MN3 and MN5 divide
Control metal-oxide-semiconductor not as two pre-amplifications；When it is VDDL to input IN, INB is low level；If it is low now to export OUT
Level is QB when to be VDDH, Q be low level, high level logic error correction circuit work so that node B is VDDH, forces QB
Level be returned to low level, output OUT is changed into VDDH；When it is low level to input IN, INB VDDL, if now defeated
Go out OUT be high level i.e. QB be low level, Q is when being VDDH, then now low level error correction circuit works so that node D
For VDDH, Q level points are forced to return to VDDH, and then so that node QB level is VDDH, most output OUT is adjusted to low electricity at last
It is flat.
Phase inverter INV1 is input inverter, and its effect is that input signal IN is converted into control signal INB；Phase inverter
INV2 is output phase inverter, and it, which is acted on, is isolated by MP5, MP6, MP7, MP8, MN7, MN8 latch formed and load capacitance,
Lift the driving force of circuit.
The features of the present invention and beneficial effect are：
A kind of level shifting circuit with pre-amplification proposed by the present invention can complete the level signal of multi-power system
Conversion, the low in energy consumption, data stability very low level signal being converted into when high level signal and circuit work are good.
Brief description of the drawings：
A kind of Fig. 1 circuit diagrams of the level shifting circuit with pre-amplification proposed by the present invention.
A kind of Fig. 2 working timing figures of the level shifting circuit with level conversion electric capacity proposed by the present invention.
Embodiment
In multi-power system, the amplitude for the level signal that different supply voltages obtains is different, and traditional
Level shifting circuit can not make a very low level signal be converted into a high level signal, and the present invention puts forward a kind of new
Level shifting circuit, the level signal conversion of multi-power system can be completed so that very low level signal can be converted into height
Level signal, subsequent propagation and processing in order to level signal.
The circuit diagram of level shifting circuit proposed by the present invention with pre-amplification is as shown in Figure 1.Electricity proposed by the present invention
It is MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8 respectively that, which there are 8 PMOSs on road, have 8 NMOS tubes be respectively MN1, MN2,
MN3, MN4, MN5, MN6, MN7, MN8 and two phase inverters INV1, INV2, wherein MP1, MP2, MN2, MP3, MP4, MN5,
MP5, MP6, MP7, MP8, MN7 and MN8 are the metal-oxide-semiconductors for belonging to thick grating oxide layer, and working power is VDDH (high power supply voltage),
MN1, MN3, MN4, MN6 are the metal-oxide-semiconductors for belonging to thin gate oxide, and working power is VDDL (low supply voltage).The present invention is each
The annexation of component is as follows：Phase inverter INV1 input termination input signal IN, output termination INB, the power supply of work are
VDDL；Phase inverter INV2 input terminated nodes QB, output termination input OUT, working power VDDH；NMOS tube MN1's
Grid meets input signal IN, and source electrode connects MN2 drain electrode, and drain electrode connects node A, Substrate ground；NMOS tube NM2 grid connects node
QB, source electrode and Substrate ground, drain electrode connect NM1 source electrode；NMOS tube MN3 grid connects INB, source electrode and Substrate ground, and drain electrode connects
Node B；NMOS tube MN4 grid meets INB, and source electrode connects MN5 drain electrode, and drain electrode connects node C, Substrate ground；NMOS tube MN5 grid
Pole connects node Q, source electrode and Substrate ground, and drain electrode connects MN4 source electrode；NMOS tube MN6 grid connects IN, source electrode and Substrate ground,
Drain electrode meets node D；NMOS tube MN7 grid connects node D, source electrode and Substrate ground, and drain electrode meets node Q；NMOS tube MN8 grid
Node B, source electrode and Substrate ground are connect, drain electrode meets node QB；PMOS MP1 grid and drain electrode meet node A, and source electrode and substrate connect
Ground；PMOS MP2 grid connects node A, source electrode and Substrate ground, and drain electrode meets node B；PMOS MP3 grid and drain electrode connect
Node C, source electrode and Substrate ground；PMOS MP4 grid connects node C, source electrode and Substrate ground, and drain electrode meets node D；PMOS
MP5 grid connects node QB, source electrode and Substrate ground, and drain electrode connects MP6 source electrode；PMOS MP6 grid connects node D, source electrode
MP5 drain electrode is connect, drain electrode connects node Q, Substrate ground；PMOS MP7 grid connects node Q, source electrode and Substrate ground, and drain electrode connects
MP8 drain electrode；PMOS MP8 grid meets node B, and source electrode connects MP7 drain electrode, and drain electrode connects node QB, Substrate ground.Wherein
VDDL is low supply voltage, and VDDH is high supply voltage.
MN1 and MN2 forms the high level logic error correction circuit of pre-amplification, and MN4 and MN5 form the low level of pre-amplification
Logical error circuit for rectifying, MP1 and MP2 and MP3 and MP4 have respectively constituted the current mirror of two pre-amplifications, and MN3 and MN5 divide
Control metal-oxide-semiconductor not as two pre-amplifications.The timing diagram of its operation principle is as shown in Fig. 2 general principle is：When input IN is
During VDDL, INB is low level；If now output OUT is that i.e. QB is VDDH, Q to low level when being low level, high level logic misses
Poor circuit for rectifying work so that node B is VDDH, forces QB level to be returned to low level, makes output OUT be changed into VDDH；When
IN is inputted when be low level, INB VDDL, if now export OUT be high level i.e. QB be low level, Q is when being VDDH, then
Now low level error correction circuit works so that node D is VDDH, forces Q level points to return to VDDH, and then cause node QB
Level be VDDH, most at last output OUT be adjusted to low level.
Phase inverter INV1 is input inverter, and its effect is that input signal IN is converted into control signal INB；Phase inverter
INV2 is output phase inverter, and it, which is acted on, is isolated by MP5, MP6, MP7, MP8, MN7, MN8 latch formed and load capacitance,
Lift the driving force of circuit.
The level conversion function that circuit structure proposed by the present invention has multi-power system is divided inside technical scheme
Analysed, in order that to become apparent from the object, technical solutions and advantages of the present invention, next by the low-power consumption to circuit and
Some details and points for attention of data integrity function do some explanations.
It is recognised that the high level error logic pre-amplification being made up of MP1, MP2, MN1, MN2, MN3 from circuit structure
The low level error logic pre-amplification formed with MPP3, MP4, MN4, MN5, MN6, it is therein when input signal is very low
When MN1, MN3, MN4, MN6 work, sub-threshold region is all operated in, operating current all very littles, required power consumption is very low.
Function by MP5, MP6, MP7, MP8, MN7, MN8 latch formed is exactly so that node B and node D voltage swing reach
VDDH is arrived to 0；In addition by MP5, MP6, MP7, MP8 cross-linked connected mode, formd on node Q and QB loop
One negative feedback loop, thus it is ensured that the stability of output level, and then it ensure that the stability of output data.
Claims (3)
1. a kind of level shifting circuit with pre-amplification, it is characterized in that, structure is as follows：Have 8 PMOSs be respectively MP1,
MP2, MP3, MP4, MP5, MP6, MP7, MP8, it is MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 respectively to have 8 NMOS tubes
And two phase inverters INV1, INV2, wherein MP1, MP2, MN2, MP3, MP4, MN5, MP5, MP6, MP7, MP8, MN7 and MN8
It is the metal-oxide-semiconductor for belonging to thick grating oxide layer, working power is that high power supply voltage VDDH, MN1, MN3, MN4, MN6 are to belong to thin grid oxygen
Change the metal-oxide-semiconductor of layer, working power is low supply voltage VDDL；Phase inverter INV1 input termination input signal IN, output termination
INB, the power supply of work is VDDL；Phase inverter INV2 input terminated nodes QB, output termination input OUT, working power are
VDDH；NMOS tube MN1 grid meets input signal IN, and source electrode connects MN2 drain electrode, and drain electrode connects node A, Substrate ground；NMOS tube
NM2 grid connects node QB, source electrode and Substrate ground, and drain electrode connects NM1 source electrode；NMOS tube MN3 grid meets INB, source electrode and
Substrate ground, drain electrode meet node B；NMOS tube MN4 grid meets INB, and source electrode connects MN5 drain electrode, and drain electrode meets node C, and substrate connects
Ground；NMOS tube MN5 grid connects node Q, source electrode and Substrate ground, and drain electrode connects MN4 source electrode；NMOS tube MN6 grid meets IN,
Source electrode and Substrate ground, drain electrode meet node D；NMOS tube MN7 grid connects node D, source electrode and Substrate ground, and drain electrode meets node Q；
NMOS tube MN8 grid connects node B, source electrode and Substrate ground, and drain electrode meets node QB；PMOS MP1 grid and drain electrode connect section
Point A, source electrode and Substrate ground；PMOS MP2 grid connects node A, source electrode and Substrate ground, and drain electrode meets node B；PMOS
MP3 grid and drain electrode connect node C, source electrode and Substrate ground；PMOS MP4 grid connects node C, source electrode and Substrate ground,
Drain electrode meets node D；PMOS MP5 grid connects node QB, source electrode and Substrate ground, and drain electrode connects MP6 source electrode；PMOS MP6
Grid meet node D, source electrode connects MP5 drain electrode, and drain electrode connects node Q, Substrate ground；PMOS MP7 grid connects node Q, source
Pole and Substrate ground, drain electrode connect MP8 drain electrode；PMOS MP8 grid meets node B, and source electrode connects MP7 drain electrode, and drain electrode connects section
Point QB, Substrate ground.
2. there is the level shifting circuit of pre-amplification as claimed in claim 1, it is characterized in that, MN1 and MN2 form pre-amplification
High level logic error correction circuit, MN4 and MN5 form the low-level logic error correction circuit of pre-amplification, MP1 and MP2 with
And MP3 and MP4 have respectively constituted the control metal-oxide-semiconductor of the current mirror of two pre-amplifications, MN3 and MN5 respectively as two pre-amplifications；
When it is VDDL to input IN, INB is low level；If now output OUT is that i.e. QB is VDDH, Q to low level when being low level, high
Level logic error correction circuit works so that node B is VDDH, forces QB level to be returned to low level, becomes output OUT
For VDDH；When input IN be low level when, INB VDDL, if now export OUT be high level i.e. QB be low level, Q be
During VDDH, then now low level error correction circuit works so that node D is VDDH, forces Q level points to return to VDDH, enters
And so that node QB level is VDDH, most output OUT is adjusted to low level at last.
3. there is the level shifting circuit of pre-amplification as claimed in claim 1, it is characterized in that, phase inverter INV1 is input inversion
Device, its effect is that input signal IN is converted into control signal INB；Phase inverter INV2 is output phase inverter, and it is isolation that it, which is acted on,
By MP5, MP6, MP7, MP8, MN7, MN8 latch formed and load capacitance, the driving force of circuit is lifted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710751152.9A CN107659302A (en) | 2017-08-28 | 2017-08-28 | Level shifting circuit with pre-amplification |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710751152.9A CN107659302A (en) | 2017-08-28 | 2017-08-28 | Level shifting circuit with pre-amplification |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107659302A true CN107659302A (en) | 2018-02-02 |
Family
ID=61127845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710751152.9A Pending CN107659302A (en) | 2017-08-28 | 2017-08-28 | Level shifting circuit with pre-amplification |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107659302A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108259034A (en) * | 2018-02-27 | 2018-07-06 | 上海华虹宏力半导体制造有限公司 | Level shift circuit |
| CN108540124A (en) * | 2018-04-16 | 2018-09-14 | 电子科技大学 | A kind of level shifting circuit |
| CN109936359A (en) * | 2019-02-19 | 2019-06-25 | 杭州晶华微电子有限公司 | A kind of low-power consumption bi-directional digital level shifting circuit and chip with automatic angle detecting and strong output driving ability |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106899288A (en) * | 2017-02-21 | 2017-06-27 | 珠海市杰理科技股份有限公司 | Level shifting circuit |
| CN107070446A (en) * | 2015-11-16 | 2017-08-18 | 台湾积体电路制造股份有限公司 | Level conversion device, semiconductor devices and its operating method |
-
2017
- 2017-08-28 CN CN201710751152.9A patent/CN107659302A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107070446A (en) * | 2015-11-16 | 2017-08-18 | 台湾积体电路制造股份有限公司 | Level conversion device, semiconductor devices and its operating method |
| CN106899288A (en) * | 2017-02-21 | 2017-06-27 | 珠海市杰理科技股份有限公司 | Level shifting circuit |
Non-Patent Citations (1)
| Title |
|---|
| RYO MATSUZUKA等: "An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs", 《IEEE》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108259034A (en) * | 2018-02-27 | 2018-07-06 | 上海华虹宏力半导体制造有限公司 | Level shift circuit |
| CN108540124A (en) * | 2018-04-16 | 2018-09-14 | 电子科技大学 | A kind of level shifting circuit |
| CN109936359A (en) * | 2019-02-19 | 2019-06-25 | 杭州晶华微电子有限公司 | A kind of low-power consumption bi-directional digital level shifting circuit and chip with automatic angle detecting and strong output driving ability |
| CN109936359B (en) * | 2019-02-19 | 2021-03-26 | 杭州晶华微电子股份有限公司 | Low-power-consumption bidirectional digital level conversion circuit and chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107659302A (en) | Level shifting circuit with pre-amplification | |
| CN106230416A (en) | A kind of nothing bootstrapping gate driver circuit of band active clamp | |
| CN202750074U (en) | High-speed comparator | |
| CN107944099A (en) | A kind of high-speed, high precision comparator circuit design | |
| CN108155903A (en) | High speed and high pressure level shifting circuit applied to GaN gate drivings | |
| CN102487240B (en) | Control circuit of voltage switching rate and output circuit | |
| CN108233896A (en) | A kind of low-power consumption sense amplifier type d type flip flop | |
| CN102412825A (en) | Level conversion circuit | |
| CN108540124A (en) | A kind of level shifting circuit | |
| Cao et al. | An energy-efficient subthreshold level shifter with a wide input voltage range | |
| CN102983847B (en) | Wide power voltage and low power consumption timer circuit | |
| CN102723930B (en) | Double-edge D trigger | |
| CN104506183A (en) | Single-voltage sub-threshold level shifter | |
| CN113472323B (en) | D trigger circuit with strong latch structure | |
| CN105162468B (en) | A kind of high speed benchmark buffer circuit with voltage bootstrapping | |
| CN112187253B (en) | Low-power-consumption level shifter circuit with strong latch structure | |
| You et al. | An ultra-low leakage energy efficient level shifter with wide conversion range | |
| CN105187045B (en) | A kind of dynamic latch of the band pull-up PMOS of high speed circuit | |
| CN102684647B (en) | Sampling pulse type trigger | |
| CN113162412B (en) | PFM/PWM switching circuit for DC-DC switching power supply circuit | |
| CN108011629A (en) | A kind of high-speed low-power-consumption level displacement circuit | |
| Balaji et al. | A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS | |
| CN206948279U (en) | A kind of Fully-differential low-power-consumptiolow-noise comparator of high tension apparatus work at lower voltages | |
| Chen et al. | An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation | |
| CN106712469A (en) | Gate drive circuit used for charge pump |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180202 |