TWI806169B - Bootstrapped switch - Google Patents

Abstract

A bootstrapped switch is provided. The bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The first switch is coupled between a node and a reference voltage. The second switch is coupled between the control terminal of the first transistor and the node. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the node and the output terminal of the inverter circuit.

Description

bootstrap switch

This case is about bootstrapped switches, especially bootstrapped switches with fast turn-on and fast turn-off.

FIG. 1 is a circuit diagram of a conventional bootstrap switch. The bootstrap switch 10 includes a switch 101 , a switch 102 , a switch 103 , a switch 104 , a switch 105 , and an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) (hereinafter referred to as NMOS transistor) 106 and a bootstrap capacitor 107 . The input terminal VI and the output terminal VO of the bootstrap switch 10 are respectively coupled to the source and drain of the NMOS transistor 106 . The gate of the NMOS transistor 106 is coupled to the voltage source V3 through the switch 105 on the one hand, and is coupled to one end of the boost capacitor 107 and one end of the switch 101 through the switch 104 on the other hand. The other end of the switch 101 is coupled to the voltage source V1. The other end of the boost capacitor 107 is coupled to the voltage source V2 through the switch 102 , and coupled to the source of the NMOS transistor 106 and the input terminal VI of the bootstrap switch 10 through the switch 103 . The voltage source V1 is a high voltage level VDD, and the voltage source V2 and the voltage source V3 are ground level. The operation of the bootstrap switch 10 is well known to those skilled in the art, so details will not be repeated here.

The state of the switch 105 (conducting or not conducting) determines the state of the NMOS transistor 106 (conducting or not conducting). In other words, the shorter the response time of the switch 105 (that is, the faster the gate of the NMOS transistor 106 reaches the target voltage), the more the state of the NMOS transistor 106 can be consistent with the system clock, so that the performance of the bootstrap switch 10 is better. Better (for example, faster, more accurate results for sampling). In other words, the design of the switch 105 plays an important role in the bootstrap switch 10 .

In view of the deficiencies of the prior art, an object of the present invention is to provide a bootstrap switch to improve the deficiencies of the prior art.

One embodiment of the present invention provides a bootstrap switch for receiving an input voltage and outputting an output voltage, comprising: a first transistor, a first capacitor, a second transistor, a first switch, a The second switch, a third switch, a fourth switch, a fifth switch, an inverter circuit and a second capacitor. The first transistor has a first terminal, a second terminal and a first control terminal, wherein the first transistor receives the input voltage from the first terminal and outputs the output voltage from the second terminal. The first capacitor has a third terminal and a fourth terminal; the second transistor has a fifth terminal, a sixth terminal and a second control terminal, wherein the second transistor receives the input from the fifth terminal voltage, the sixth end is electrically connected to the third end of the first capacitor, and the second control end is electrically connected to the first control end of the first transistor. The first switch is coupled between the third terminal of the first capacitor and a first reference voltage. The second switch is coupled between the fourth terminal of the first capacitor and a second reference voltage. The third switch is coupled between the fourth end of the first capacitor and the first control end of the first transistor. The fourth switch is coupled between the first control terminal of the first transistor and a node. The fifth switch has a third control terminal and is coupled between the node and the first reference voltage. The inverter circuit has an input terminal and an output terminal, wherein the input terminal is coupled to the third control terminal of the fifth switch, and the inverter circuit is used for inverting a voltage of the third control terminal. The second capacitor has a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the output terminal of the inverter circuit, and the eighth terminal is coupled to the node.

The bootstrap switch of the present invention is capable of fast turn-on and/or fast turn-off. Compared with the conventional technology, the bootstrap switch of the present invention can operate at a higher speed.

The characteristics, implementation and effects of the present invention are described in detail as follows with reference to the drawings.

The technical terms in the following explanations refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the explanations of these terms shall be based on the descriptions or definitions in this specification.

The present disclosure includes bootstrap switches. Since some of the components included in the bootstrap switch of the present invention may be known components individually, the details of the known components will be described below without affecting the full disclosure and practicability of the invention of the device. Abridged.

FIG. 2 is a circuit diagram of an embodiment of the bootstrap switch of the present invention. The bootstrap switch 100 receives an input voltage Vin from an input terminal IN, and outputs an output voltage Vout from an output terminal OUT. The bootstrap switch 100 includes a switch 110 , a switch 120 , a switch 130 , a switch 140 , a switch 150 , a switch 160 , a switch 170 , a boost capacitor Cb, a capacitor Cq and an inverter circuit 180 . The switch circuit SW1 corresponds to the switch 105 in FIG. 1 . The switch 110, the switch 120, the switch 130, the switch 140, the switch 150, the switch 160 and the switch 170 can respectively use the transistor M1, the transistor M7, the transistor M2, the transistor M3, the transistor M8, the transistor M4 and the transistor M11 practice. Each transistor has a first terminal, a second terminal and a control terminal, the first terminal and the second terminal are the two ends of the switch formed by the transistor. For Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the first end can be one of the source and the drain, and the second end is the other of the source and the drain. , while the control terminal is the gate. For a bipolar junction transistor (BJT), the first end can be one of the collector and the emitter, and the second end is the other of the collector and the emitter. Or, and the control end is the base (base).

As shown in FIG. 2 , the control terminal of the transistor M1 and the control terminal of the transistor M7 are electrically connected to each other. The transistor M1 receives an input voltage Vin at a first terminal, and outputs an output voltage Vout from a second terminal. The first end of the transistor M7 receives the input voltage Vin, and the second end of the transistor M7 is electrically connected to the first end of the boost capacitor Cb. The first end of the transistor M2 is coupled to the first end of the boost capacitor Cb, and the second end of the transistor M2 is coupled to the first reference voltage (the ground level GND in the example of FIG. 2 ). The first terminal of the transistor M3 is coupled to the second reference voltage (in the example of FIG. 2 , the power supply voltage VDD, which is higher than the ground level GND), and the second terminal of the transistor M3 is coupled to the boost capacitor Cb. second end. A first terminal of the transistor M8 is coupled to the control terminal of the transistor M1, and a second terminal of the transistor M8 is coupled to the second terminal of the boost capacitor Cb. The first terminal of the transistor M4 is coupled or electrically connected to the control terminal of the transistor M1 and the control terminal of the transistor M7, the control terminal of the transistor M4 is coupled to or electrically connected to the power supply voltage VDD, and the second terminal of the transistor M4 is coupled to connected or electrically connected to the node Nq. A first end of the transistor M11 is coupled or electrically connected to the node Nq, and a second end of the transistor M11 is coupled or electrically connected to a first reference voltage (ground level GND). The control terminal of the transistor M11 receives the clock pulse Φ1b. A first end of the capacitor Cq is coupled or electrically connected to the node Nq. The input terminal of the inverter circuit 180 receives the clock pulse Φ1b, and the output terminal of the inverter circuit 180 is coupled or electrically connected to the second terminal of the capacitor Cq.

The switch 130 , the switch 140 , the switch 150 and the switch 170 are conducted (the corresponding transistor is turned on) or not conducted (the corresponding transistor is turned off) according to the clock Φ1 and the clock Φ1 b. FIG. 3 shows an example of the clock Φ1 and the clock Φ1b. The clock Φ1 and the clock Φ1b are mutually inverse signals. Controlled by the clock Φ1 and the clock Φ1b, the bootstrap switch 100 alternately operates in the first clock phase Ph1 (the clock Φ1 is at the first level (eg low level) and the clock Φ1b is at the second level (eg High level) and the second clock phase Ph2 (the period when the clock Φ1 is at the second level and the clock Φ1b is at the first level). The details of the operation of the bootstrap switch 100 will be described in detail below.

Refer to Figure 2 and Figure 3. During the first clock phase Ph1 (when the clock Φ1 is low and the clock Φ1b is high), the switch 130 , the switch 140 , the switch 160 and the switch 170 are turned on, and the switch 150 is not turned on. When the switch 160 and the switch 170 are turned on, the voltages on the control terminals of the transistor M1 and the transistor M7 are substantially equal to the first reference voltage (ground level GND), so that the switch 110 and the switch 120 are not conducted; in other words, The switch 110 and the switch 120 are not turned on during the first clock phase Ph1. When the switch 130 and the switch 140 are turned on, the voltages across the lifting capacitor Cb are substantially the first reference voltage (ground level GND) and the second reference voltage (power supply voltage VDD); in other words, the lifting capacitor Cb is at the first clock pulse Charging is performed during the phase Ph1, and the voltage across the boost capacitor Cb Vcb is substantially equal to the voltage difference between the first reference voltage and the second reference voltage after the end of the first clock phase Ph1.

During the second clock phase Ph2 (when the clock Φ1 is high and the clock Φ1b is low), the switch 130 , the switch 140 , the switch 160 and the switch 170 are not turned on, and the switch 150 is turned on. When the switch 150 is turned on, the control terminals of the transistor M1 and the transistor M7 are substantially at the same potential as the second terminal of the boost capacitor Cb, so that the transistor M1 and the transistor M7 are turned on due to the voltage Vcb across the boost capacitor Cb. When the transistor M7 is turned on, the voltage at the second end of the boost capacitor Cb and the control end of the transistor M1 is substantially equal to the sum of the input voltage Vin and the cross voltage Vcb. When the transistor M1 is turned on, the output voltage Vout is substantially equal to the input voltage Vin, that is, the bootstrap switch 100 is turned on.

The voltage of the control terminal of the transistor M1 may be greater than the power supply voltage VDD (even close to 2 times the power supply voltage VDD), and the transistor M11 may be connected to the ground level at the control terminal (gate) and the second terminal (source) The state of GND. In some related technologies, if the first terminal (drain) of the transistor M11 is directly electrically connected to the transistor M1, the high voltage on the control terminal of the transistor M1 (as mentioned above, can be nearly twice as high as The power supply voltage VDD) will greatly reduce the life of the transistor M11. In order to improve the problem disclosed above, one of the purposes of the transistor M4 of the present invention is to isolate the control terminal of the transistor M1 from the transistor M11 to prevent the first terminal of the transistor M11 from bearing the high voltage. Because the control terminal of the transistor M4 is coupled or electrically connected to the power supply voltage VDD, the voltages between the first terminal, the second terminal and the control terminal of the transistor M4 are all lower than the power supply voltage VDD, so the transistor M4 can withstand this high voltage . However, the transistor M4 slows down the switching speed of the control terminal of the transistor M1 from the second level (such as high level) to the first level (such as low level), so that the bootstrap switch 100 cannot Immediately after the first clock phase Ph1, the conduction state becomes non-conduction state; in other words, the transistor M4 may cause the switching speed of the bootstrap switch 100 to slow down.

One of the purposes of the capacitor Cq and the inverter circuit 180 is to quickly pull up or pull down the voltage of the node Nq, thereby accelerating the switching speed of the transistor M4 (that is, increasing the voltage conversion speed of the control terminal of the transistor M1, which is equivalent to speeding up switching speed of the bootstrap switch 100).

When the clock pulse Φ1b is switched from the first level to the second level (transistor M11 starts to conduct but is not completely turned on), the inverter circuit 180 outputs an output signal that is inverse to the clock pulse Φ1b (that is, the signal of the first level ), and then the output signal is coupled to the node Nq through the capacitor Cq, so that the voltage of the node Nq can start to drop before the transistor M11 is fully turned on. Once the voltage on the node Nq begins to drop, the cross-voltage between the first terminal and the second terminal of the transistor M4 will increase, so that the conduction capability of the transistor M4 will increase. In other words, the inverter circuit 180 and the capacitor Cq can greatly help the transistor M4 to be turned on earlier, so that the voltage at the control terminal of the transistor M1 can drop faster (ie, speed up the turn-off speed of the bootstrap switch 100 ).

When the clock pulse Φ1b is switched from the second level to the first level (transistor M11 starts to turn off but not completely turned off), the inverter circuit 180 outputs an output signal that is inverted from the clock Φ1b (that is, the signal of the second level ), and then the output signal is coupled to the node Nq through the capacitor Cq, so that the voltage of the node Nq can start to rise before the transistor M11 is completely turned off. When the voltage on the node Nq starts to rise, the voltage at the control terminal of the transistor M1 will be pulled up through the transistor M4. In other words, the inverter circuit 180 and the capacitor Cq can make the voltage of the control terminal of the transistor M1 rise faster (ie, speed up the conduction speed of the bootstrap switch 100 ).

FIG. 4 is a computer simulation waveform diagram of the voltage of the node Nq and the voltage of the control terminal of the transistor M1. The curve g2 and the curve b2 represent the voltage of the node Nq, and the curve g3 and the curve b3 represent the voltage of the control terminal of the transistor M1. Curve g2 and curve g3 correspond to a bootstrap switch (such as the bootstrap switch 100 of FIG. Bootstrap switch of capacitor Cq (such as the circuit of FIG. 2 but removing inverter circuit 180 and capacitor Cq). It can be seen from Figure 4 that when the time pulse Φ1b is switched from the first level to the second level (such as time point T1), the curve g3 drops faster than the curve b3 (the slope of the curve g3 is greater than the slope of the curve b3), that is, the transistor The voltage of the control terminal of M1 reaches the first level about T3-T2 earlier. When the clock pulse Φ1b is switched from the second level to the first level (such as time point T4), the curve g3 starts to rise earlier than the curve b3, that is, the bootstrap switch 100 is activated more quickly. The voltage on the node Nq also has a similar trend, so it will not be repeated here.

In some embodiments, the inverter circuit 180 includes an odd number of inverters, and the capacitance of the capacitor Cq may be tens to hundreds of femtofarads (fF), preferably between 10 femtofarads and 100 femtofarads , and the capacitance value of capacitor Cq is also a trade-off (trade-off), because if the capacitance value of capacitor Cq is too large, the size of inverter circuit 180 will be increased, resulting in the operation speed of the added inverter circuit 180 and capacitor Cq Slower than transistor M11.

FIG. 5 is a circuit diagram of another embodiment of the bootstrap switch of the present invention. The bootstrap switch 500 is similar to the bootstrap switch 100 , the difference is that the bootstrap switch 500 further includes a switch 185 , a switch 190 and a switch 195 . The switch 185 , the switch 190 and the switch 195 are realized by the transistor M9 , the transistor M5 and the transistor M6 respectively. The switch 185 is coupled between the second reference voltage and the control terminal of the transistor M8, and is controlled by the clock Φ1. The switch 190 is coupled between the first end of the boost capacitor Cb and the control end of the transistor M8, and is controlled by the clock Φ1. The switch 195 is coupled between the first end of the boost capacitor Cb and the control end of the transistor M8, and the control end of the transistor M6 is electrically connected to the control end of the transistor M1 and the control end of the transistor M7. The transistor M5, the transistor M6 and the transistor M9 are used to provide overvoltage protection during the operation of the bootstrap switch 500 to prolong the service life of the components. No longer.

To sum up, the inverter circuit 180 and the capacitor Cq help the voltage on the node Nq and the voltage on the control terminal of the transistor M1 rise or fall early, and/or rise or fall quickly, so that the bootstrap switch has a better performance. Fast response speed (i.e., can operate at higher speeds).

In other embodiments, the PMOS transistors and NMOS transistors in the foregoing embodiments can be replaced by NMOS transistors and PMOS transistors respectively, and those skilled in the art know how to adjust the clock Φ1 and the clock Φ1b accordingly. The phase or level, and adjusting the first reference voltage and the second reference voltage accordingly, realize the implementation content disclosed above.

Please note that the shapes, sizes and proportions of the components in the preceding drawings are only for illustration, and are for those skilled in the art to understand the present invention, and are not intended to limit the present invention.

Although the embodiments of the present invention are as described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make changes to the technical characteristics of the present invention according to the explicit or implicit contents of the present invention. All these changes may belong to the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention must be defined by the scope of patent application in this specification.

10,100,500: bootstrap switch 101,102,103,104,105,110,120,130,140,150,160,170,185,190,195: switch 106: N-type metal oxide half field effect transistor 107, Cb: lifting capacitor VI, IN: input terminal VO, OUT: output terminal V1, V2, V3: voltage source Vin: input voltage Vout: output voltage SW1: switch circuit Cq: Capacitance 180: Inverter circuit M1, M7, M2, M3, M8, M4, M11, M9, M5, M6: Transistor GND: ground level VDD: power supply voltage Nq: node Φ1,Φ1b: Clock Ph1: first clock phase Ph2: second clock phase Vcb: cross voltage g2, b2, g3, b3: curves T1, T2, T3, T4: time points

Fig. 1 is the circuit diagram of known bootstrap switch; Fig. 2 is the circuit diagram of one embodiment of bootstrap switch of the present invention; Fig. 3 shows an example of clock Φ1 and clock Φ1b; Fig. 4 is a computer simulation waveform diagram of the voltage of the node Nq and the voltage of the control terminal of the transistor M1; and FIG. 5 is a circuit diagram of another embodiment of the bootstrap switch of the present invention.

100: Bootstrap switch 110,120,130,140,150,160,170: switch Cb: lift capacitor IN: input terminal OUT: output terminal Vin: input voltage Vout: output voltage SW1: switch circuit Cq: Capacitance 180: Inverter circuit M1, M7, M2, M3, M8, M4, M11: Transistor GND: ground level VDD: power supply voltage Nq: node Φ1,Φ1b: Clock Vcb: cross voltage

Claims (10)

A bootstrap switch for receiving an input voltage and outputting an output voltage, comprising: a first transistor having a first terminal, a second terminal and a first control terminal, wherein the first transistor The first end receives the input voltage, and outputs the output voltage through the second end; a first capacitor has a third end and a fourth end; a second transistor has a fifth end, a The sixth terminal and a second control terminal, wherein the second transistor receives the input voltage from the fifth terminal, the sixth terminal is electrically connected to the third terminal of the first capacitor, and the second control terminal is electrically connected to the first control end of the first transistor; a first switch, coupled between the third end of the first capacitor and a first reference voltage; a second switch, coupled to the first between the fourth end of the capacitor and a second reference voltage; a third switch coupled between the fourth end of the first capacitor and the first control end of the first transistor; a fourth a switch, coupled between the first control terminal of the first transistor and a node; a fifth switch, having a third control terminal and coupled between the node and the first reference voltage; an inverse an inverter circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the third control terminal of the fifth switch, and the inverter circuit is used for inverting a voltage of the third control terminal; as well as A second capacitor has a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the output terminal of the inverter circuit, and the eighth terminal is coupled to the node. The bootstrap switch according to claim 1, wherein, at a first clock phase, the first switch, the second switch, the fourth switch, and the fifth switch are turned on and the third switch is not turned on, so that charging the first capacitor; at a second clock phase, the third switch is turned on and the first switch, the second switch, the fourth switch and the fifth switch are not turned on. The bootstrap switch according to claim 1, wherein the fourth switch has a fourth control terminal, and the fourth control terminal is electrically connected to the second reference voltage. The bootstrap switch according to claim 1, wherein the inverter circuit includes an odd number of inverters. The bootstrap switch according to claim 1, wherein the capacitance of the second capacitor is between 10 femtofarads and 100 femtofarads. A bootstrap switch for receiving an input voltage and outputting an output voltage, comprising: a first transistor having a first terminal, a second terminal and a first control terminal, wherein the first transistor The first end receives the input voltage, and outputs the output voltage through the second end; a first capacitor has a third end and a fourth end; a second transistor has a fifth end, a a sixth terminal and a second control terminal, wherein the second transistor receives the input voltage from the fifth terminal, and the sixth terminal is electrically connected to the first capacitor the third end of the first capacitor, and the second control end is electrically connected to the first control end of the first transistor; a first switch is coupled between the third end of the first capacitor and a first reference voltage Between; a second switch, coupled between the fourth terminal of the first capacitor and a second reference voltage; a third switch, coupled between the fourth terminal of the first capacitor and the first voltage between the first control terminals of the crystal; a fourth switch, coupled between the first control terminal of the first transistor and a node; a fifth switch, having a third control terminal and coupled to between the node and the first reference voltage; an inverter circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the third control terminal of the fifth switch, when the third control terminal When the level is low, the output terminal is high level, and when the third control terminal is high level, the output terminal is low level; and a second capacitor has a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the output terminal of the inverter circuit, and the eighth terminal is coupled to the node. The bootstrap switch of claim 6, wherein, at a first clock phase, the first switch, the second switch, the fourth switch, and the fifth switch are turned on and the third switch is not turned on, so that charging the first capacitor; at a second clock phase, the third switch is turned on and the first switch, the second switch, the fourth switch and the fifth switch are not turned on. The bootstrap switch according to claim 6, wherein the fourth switch has a fourth control terminal, and the fourth control terminal is electrically connected to the second reference voltage. The bootstrap switch according to claim 6, wherein the inverter circuit includes an odd number of inverters. The bootstrap switch according to claim 6, wherein the capacitance of the second capacitor is between 10 femtofarads and 100 femtofarads.

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