TWI593231B - A control device and control method for analog power switch - Google Patents

Description

Control device and control method for analog power switch

The present invention relates to the field of circuits, and more particularly to a control apparatus and control method for analog power switches.

At present, analog power switches are widely used in various circuit systems. When the analog power switch is applied in the circuit system, the conduction and the voltage difference Vgs (Vgate-Vsource) between the gate voltage (Vgate) and the source voltage (Vsource) of the analog power switch can be controlled. cutoff. Specifically, when Vgs<Vth, the analog power switch is turned off; when Vgs At Vth, the analog power switch is turned on, and its on-resistance decreases as Vgs increases, where Vth is the turn-on threshold voltage of the analog power switch.

Figure 1 is a schematic diagram of an exemplary application of an analog power switch, such as an N-channel Metal-Oxide-Semiconductor (NMOS) power transistor. As shown in FIG. 1, an NMOS power transistor is included in the wafer C; the wafer C has three terminals of VIN, VOUT, and GND, and includes three parts of an NMOS power transistor, a gate driving circuit, and a control circuit. The drain of the NMOS power transistor is connected to the VIN terminal, and the input voltage VIN is input to the drain of the NMOS power transistor via the VIN terminal; the source of the NMOS power transistor is connected to the VOUT terminal, and the output voltage VOUT is connected via the VOUT terminal. Provided to the load; the control circuit generates a control signal for controlling the turn-on and turn-off of the NMOS power transistor; the gate driving circuit generates a driving signal for driving the NMOS power transistor to turn on and off based on the control signal generated by the control circuit, and The drive signal is supplied to the gate of the NMOS power transistor.

Before the NMOS power transistor is turned on, the VOUT terminal is grounded; when Vgs At Vth, the NMOS power transistor is turned on. Since the on-resistance of the turned-on NMOS power transistor is small, the VOUT terminal and the VIN terminal can be regarded as a short circuit, so that the output voltage VOUT rises to the input voltage VIN after the NMOS power transistor is turned on. In order to maintain the on state of the NMOS power transistor, the gate driving circuit is configured to control the gate voltage Vgate of the NMOS power transistor to become higher as the output voltage VOUT rises, that is, maintain the gate voltage Vgate VOUT+Vth to ensure that Vgs is met The conduction condition of Vth.

Generally, the gate driving circuit generates a driving signal by any one of a Bootstrap method and a charge pump method. However, the Bootstrap method and the charge pump method generally require an external large capacitor. For cost reasons, the chip C generally cannot integrate such a large capacitor.

The present invention provides a control apparatus and method for an analog power switch.

A control device for an analog power switch according to an embodiment of the present invention includes: a capacitor, an upper plate of the capacitor is connected to a gate of an analog power switch via a diode and connected to an input voltage via a first switch, the capacitor The lower plate is coupled to the source of the analog power switch via a second switch and to the ground via the third switch; and the logic control element is configured to control the closing and closing of the first switch, the second switch, and the third switch The capacitor is controlled to charge and discharge, thereby controlling the analog power switch to be turned on and off, wherein when the first switch and the third switch are closed, the second switch is turned off, the capacitor is charged, when the first switch and the third switch are turned off, and the second The capacitor discharges when the switch is closed.

A control method for an analog power switch according to an embodiment of the present invention includes: connecting an upper plate of a capacitor to a gate of an analog power switch via a diode and connecting to an input voltage via a first switch; The board is connected to the source of the analog power switch via the second switch and to the ground via the third switch; and controlling the charging and discharging of the capacitor by controlling the closing and opening of the first switch, the second switch, and the third switch, Thereby, the analog power switch is controlled to be turned on and off, wherein the capacitor is charged when the first switch and the third switch are closed and the second switch is turned off, and the capacitor is discharged when the first switch and the third switch are turned off and the second switch is closed.

Control device for analog power switch and according to an embodiment of the present invention In the method, the voltage difference between the upper and lower plates of the capacitor is not large, so that it is not necessary to use a large capacitor or a cascode capacitor to realize a high withstand voltage capacitor, so that the analog power switch according to the embodiment of the present invention can be effectively reduced. The cost of the control device and method of the wafer.

Vgate‧‧‧ gate voltage

MOS_EN‧‧‧Switch enable signal

Vsource‧‧‧ source voltage

SST‧‧‧ soft start signal

Vth‧‧‧ conduction threshold voltage

CLK‧‧‧ clock signal

C‧‧‧ wafer

SD, PA, PB, PC‧‧‧ switch control signals

VIN‧‧‧ input voltage

PH1, PH2‧‧‧ voltage selection signal

VOUT‧‧‧ output voltage

AVDD‧‧‧ Constant voltage

GND, VS‧‧‧ terminal

Vramp‧‧‧ ramp voltage

C0, C1, C2, C7‧‧‧ capacitor

VCP‧‧‧ plate voltage

C3-C6‧‧‧ series capacitor

R1, R2, R3, R4‧‧‧ resistance

410‧‧‧Charging pump main circuit

D0‧‧‧ diode

430‧‧‧Logic Control Circuit

D1‧‧‧ voltage clamp diode

Vsel‧‧‧Voltage selection

C1p, C2p, C3p, C4p‧‧‧ capacitance to ground

P1, P3, N1, N2, N3, N4‧‧‧ switch

420‧‧‧Voltage selection (Vsel) circuit

D‧‧‧Power MOS field effect transistor bungee

G‧‧‧Power MOS field effect transistor gate

S‧‧‧Power MOS field effect transistor source

Voltage difference between Vgs‧‧ ‧ gate voltage (Vgate) and source voltage (Vsource)

The invention may be better understood from the following description of the embodiments of the invention, in which <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Schematic diagram of an exemplary application of a semiconductor (NMOS) power transistor; FIG. 2 is an exemplary circuit diagram of a conventional charge pump used in the gate drive circuit shown in FIG. 1; and FIG. 3 is used in FIG. Example circuit diagram of a conventional charge pump using a cascade capacitor in the illustrated gate drive circuit; FIG. 4 is a schematic diagram of a charge pump used in the gate drive circuit shown in FIG. 1 according to an embodiment of the present invention; Figure 5 shows a timing diagram of signals associated with the logic control circuit shown in Figure 4.

Features and exemplary embodiments of various aspects of the invention are described in detail below. In the following detailed description, numerous specific details are set forth However, it will be apparent to those skilled in the art that the present invention may be practiced without some of the details. The following description of the embodiments is merely provided to provide a better understanding of the invention. The present invention is in no way limited to any specific configurations and algorithms presented below, but without departing from the spirit and scope of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessary obscuring the invention.

Fig. 2 is a circuit diagram showing an example of a conventional charge pump used in the gate drive circuit shown in Fig. 1. In the case of the high voltage application of the charge pump shown in Fig. 2, since the voltage difference between the upper and lower plates of the capacitors C1 and C2 is too large, it is necessary to realize a high withstand voltage by means of a cascade capacitor. The capacitance, which causes the cost of the wafer C to increase greatly.

Fig. 3 is a circuit diagram showing an example of a conventional charge pump using a cascade capacitor used in the gate drive circuit shown in Fig. 1. In the charge pump shown in Fig. 3, the withstand voltage of the upper and lower plates of the capacitors C1 and C2 is solved by using a series capacitor. However, as shown in Figure 3, capacitors C1 and C2, and their series capacitors C3-C6, together introduce parasitic capacitance to ground (eg, C1p, C2p, C3p, C4p), which can make the parasitic capacitance to ground The equivalent capacitance of the capacitors C1-C6 in the operating state becomes small. Therefore, to achieve the same effect, it is necessary to cascade more capacitors, which further increases the cost of the wafer C.

In order to solve one or more problems in the charge pump described in connection with FIGS. 2 and 3, a novel charge pump for use in the gate drive circuit shown in FIG. 1 is proposed to effectively reduce the wafer. The cost of C. A charge pump for use in the gate driving circuit shown in Fig. 1 according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 4 is a schematic view of a charge pump used in the gate driving circuit shown in Fig. 1 according to an embodiment of the present invention. As shown in FIG. 4, a charge pump according to an embodiment of the present invention includes a charge pump main circuit 410, a voltage selection (Vsel) circuit 420, and a logic control circuit 430. specifically:

The charge pump main circuit 410 includes switches P1, P3, N1-N4, a capacitor C0, and a diode D0; the VS terminal of the charge pump main circuit 410 is connected to the output of the Vsel circuit 420, and the GATE terminal of the charge pump main circuit 410 is The gates of the NMOS power transistors are connected, and the VOUT terminal of the charge pump main circuit 410 is connected to the source of the NMOS power transistor.

The logic control circuit 430 receives the switch enable signal MOS_EN, the soft start signal SST, and the clock signal CLK, generates a switch control signal SD based on the switch enable signal MOS_EN, and generates a voltage selection signal PH1 based on the switch enable signal MOS_EN and the soft start signal SST. PH2, and generates switch control signals PA, PB, and PC based on the switch enable signal MOS_EN and the clock signal CLK. among them:

That is, when MOS_EN = 1, SD = 0; when MOS_EN = 0, SD = 1.

PH 1= SST . MOS_EN , , that is, when MOS_EN = 1, PH1 = SST, When MOS_EN=0, PH1=PH2=0.

, , that is, when MOS_EN=1, , PA = PC = CLK , and when MOS_EN = 0, PB = 0, PA = PC = 1.

Fig. 5 is a timing chart showing signals related to the logic control circuit shown in Fig. 4. It should be noted that since the logic control circuit has a certain delay, the waveforms of the switch control signals PA, PB, and PC are not strictly aligned with the clock signal CLK.

The function of each of the above-described signals and the operation of the charge pump main circuit 410 will be described in detail below with reference to FIGS. 4 and 5:

The switch enable signal MOS_EN indicates whether the NMOS power transistor is enabled, and the switch control signal SD controls the closing and opening of the switch N4 to control whether the NMOS power transistor is enabled. Specifically, when the switch enable signal MOS_EN is at a high level, the switch control signal SD is at a low level, the switch N4 is turned off, and the NMOS power transistor is enabled; when the switch enable signal MOS_EN is at a low level, the switch control signal SD is at a high level. The switch N4 is closed, the gate of the NMOS power transistor is grounded, and the NMOS power transistor is disabled.

The soft start signal SST indicates whether a soft start process is employed, and the voltage selection signals PH1 and PH2 control the Vsel circuit 420 to select one of the constant voltage AVDD and the ramp voltage Vramp to be supplied to the charge pump main circuit 410 (hereinafter, the selected voltage is convenient for convenience) Called voltage VS). Specifically, when the soft start signal SST is at a high level, the voltage selection signal PH1 is at a high level, the voltage selection signal PH2 is at a low level, and the Vsel circuit 420 selects the ramp voltage Vramp as a voltage VS to be supplied to the charge pump main circuit 410 (ie, using soft Startup process); when the soft start signal SST is low, the voltage selection signal PH1 is low, the voltage selection signal PH2 is high, and the Vsel circuit 420 selects the constant voltage AVDD as the voltage VS to be supplied to the charge pump main circuit 410 (ie, no Adopt soft start process).

The clock signal CLK provides a clock signal of a certain frequency. The switch control signal PA controls the closing and opening of the switch N2; the switch control signal PB controls the closing and opening of the switches N3 and P3 (the switch P3 and the switch N3 are simultaneously closed or opened); the switch control signal PC controls the switches N1 and P1 Closed and open (switches P1 and N1 are closed or open at the same time).

As apparent from the above description, in the case where the NMOS transistor is enabled, the logic control circuit 430 generates the voltage selection signals PH1 and PH2 based on the soft start signal SST, and generates the switch control signals PA, PB, and PC based on the clock signal CLK.

In the case where the NMOS transistor is enabled, when the soft start process is employed, the charge pump main circuit 410 switches between the first state and the second state described below, thereby realizing the gate voltage to the NMOS power transistor. control. specifically:

In the first state, N2 is turned on, P1 is turned on, P1 is turned on, P3 is turned off, N4 is turned off, the lower plate of the capacitor C0 is grounded, and the upper plate of the capacitor C0 is connected to the voltage VS. At this time, the capacitor C0 is charged until the upper and lower plates of the capacitor C0 are charged. The voltage between them reaches the voltage VS.

In the second state, N2 is disconnected, P1 is turned off, P3 is turned on, N4 is turned off, and the lower plate of the capacitor C0 is connected to the output voltage VOUT; since the voltage between the upper and lower plates of the capacitor C0 cannot be abrupt, the capacitor C0 is on The plate voltage VCP is instantaneously raised to VOUT+VS, at which time the upper plate voltage VCP of the capacitor C0 charges the gate voltage of the NMOS power transistor through the diode D0.

After a plurality of switching between the first state and the second state by the charge pump main circuit 410, the voltage difference Vgs between the gate voltage Vgate of the NMOS power transistor and the source voltage Vsource gradually increases to the peak value of the voltage Vramp. (The peak is greater than or equal to Vth) and the NMOS power transistor is turned on.

Here, the internal resistance of the switches N2, P1, P3 determines the switching speed and conduction capability of these switches, and the switching speed and conduction capability of these switches determine the speed of charging or discharging of the capacitor C0, so it can be as needed. The charging or discharging speed of the controlled capacitor C0 sets the appropriate internal resistance for these switches; the internal resistance of the switch N4 determines the switching speed and the conducting capability of the switch N4, and the switching speed and the conducting capability of the switch N4 determine the NMOS power. The discharge speed of the crystal gate is fast, so the appropriate internal resistance can be set for the switch N4 according to the discharge speed of the NMOS transistor gate to be controlled. That is to say, the internal resistances of the switches N2, P1, P3, and N4 can be adjusted as needed according to the respective switching speeds and conduction capacities of the switches N2, P1, P3, and N4.

As can be seen from the above, in the charge pump shown in Fig. 4, the capacitor The voltage difference between the upper and lower plates of C0 is not large, so it is not necessary to use a large capacitor or a cascode capacitor to achieve a high withstand voltage capacitor, so the cost of the wafer C can be effectively reduced.

In some embodiments, the logic control circuit 430 may also not receive the soft start signal SST and not generate the voltage selection signals PH1 and PH2, in which case only one of the constant voltage AVDD and the ramp voltage Vramp may be employed as the voltage VS.

In the case where the constant voltage AVDD is used as the voltage VS, when the charge pump main circuit 410 is in the second state, the upper plate voltage VCP of the capacitor C0 is immediately raised to VOUT+AVDD, thereby making the gate voltage of the NMOS power transistor Vgate quickly increases to VOUT+AVDD.

In the case where the ramp voltage Vramp (for example, from 0 V to AVDD) is employed as the voltage VS, the upper plate voltage VCP of the capacitor C0 is passed through the plurality of switching between the first state and the second state by the charge pump main circuit 410. Gradually rising to VOUT+AVDD, the gate voltage Vgate of the NMOS power transistor is gradually increased, thereby achieving soft start of the NMOS power transistor.

In some embodiments, a combination of a constant voltage AVDD and a ramp voltage Vramp may also be employed as the voltage VS (ie, the soft start signal SST, and the voltage selection signals PH1 and PH2 are not required). In this case, the soft start can be first performed using the ramp voltage Vramp, and then the gate voltage Vgate of the NMOS power transistor is finally increased to VOUT+AVDD using the constant voltage AVDD.

In some embodiments, the switches P1 and P3 shown in FIG. 4 can be implemented as a P-channel Metal-Oxide-Semiconductor (PMOS) transistor, and the switches N1-N4 can be implemented. It is an NMOS transistor. In addition, the diode D0 shown in FIG. 4 can be implemented as a PMOS transistor in which the gate and the source are connected together. In other embodiments, the switch shown in Figure 4 can also be implemented using a transfer gate.

As can be seen in conjunction with Figures 1 through 5, the present invention provides a control device for an analog power switch (e.g., an NMOS power transistor) comprising: a capacitor (e.g., capacitor C0), the upper plate of the capacitor Analogy via a diode (eg, diode D0) The gate of the power switch is connected and connected to an input voltage (eg, a constant voltage AVDD, a ramp voltage Vramp, or a combination thereof) via a first switch (eg, switch P1), the lower plate of the capacitor being via a second switch (eg, a switch P3) coupled to the source of the analog power switch and coupled to ground via a third switch (eg, switch N2); and a logic control element (eg, logic control circuit 430) configured to control the first switch, The second switch and the third switch are closed and opened to control the charging and discharging of the capacitor, thereby controlling the analog power switch to be turned on and off, wherein the capacitor is charged when the first switch and the third switch are closed and the second switch is turned off. The capacitor discharges when the first switch and the third switch are turned off and the second switch is closed.

In other words, the present invention provides a control method for an analog power switch (eg, an NMOS power transistor), including: passing an upper plate of a capacitor (eg, capacitor C0) via a diode (eg, diode D0) Connected to the gate of the analog power switch and connected to the input voltage (eg, constant voltage AVDD, ramp voltage Vramp, or a combination thereof) via the first switch (eg, switch P1); the lower plate of the capacitor is passed through the second switch (eg, switch P3) is coupled to the source of the analog power switch and to ground via a third switch (eg, switch N2); and by controlling the closing and opening of the first switch, the second switch, and the third switch Controlling the charging and discharging of the capacitor, thereby controlling the analog power switch to be turned on and off, wherein the capacitor is charged when the first switch and the third switch are closed, and the second switch is turned off, when the first switch and the third switch are turned off, and the second The above capacitor discharges when the switch is closed.

In the control apparatus and method for an analog power switch according to an embodiment of the present invention, the voltage difference between the upper and lower plates of the capacitor is not large, so that it is not necessary to use a large capacitor or a cascade capacitor to realize a high withstand voltage capacitor, The cost of implementing the wafer C for the control apparatus and method for the analog power switch according to an embodiment of the present invention can be effectively reduced.

The invention may be embodied in other specific forms without departing from the spirit and essential characteristics. For example, the algorithms described in the specific embodiments can be modified, and the system architecture does not depart from the basic spirit of the invention. The present embodiments are to be considered in all respects as illustrative and not limiting, and the scope of the invention All changes in the scope of the invention are thus included in the scope of the invention.

VIN‧‧‧ input voltage

SST‧‧‧ soft start signal

VOUT‧‧‧ output voltage

CLK‧‧‧ clock signal

GND, VS‧‧‧ terminal

SD, PA, PB, PC‧‧‧ switch control signals

C0‧‧‧ capacitor

PH1, PH2‧‧‧ voltage selection signal

Vsel‧‧‧Voltage selection

AVDD‧‧‧ Constant voltage

410‧‧‧Charging pump main circuit

Vramp‧‧‧ ramp voltage

430‧‧‧Logic Control Circuit

VCP‧‧‧ plate voltage

D0‧‧‧ diode

R1, R2, R3, R4‧‧‧ resistance

MOS_EN‧‧‧Switch enable signal

D1‧‧‧ voltage clamp diode

P1, P3, N1, N2, N3, N4‧‧‧ switch

420‧‧‧Voltage selection (Vsel) circuit

Claims (16)

A control device for an analog power switch, comprising: a capacitor, an upper plate of the capacitor being connected to a gate of the analog power switch via a diode and connected to an input voltage via a first switch, under the capacitor a plate connected to a source of the analog power switch via a second switch and to a ground via a third switch; and a logic control element configured to control the first switch, the second switch, and the Closing and opening of the third switch to control charging and discharging of the capacitor, thereby controlling the analog power switch to be turned on and off, wherein when the first switch and the third switch are closed, the second switch is turned off The capacitor is charged, the capacitor is discharged when the first switch and the third switch are turned off, and the second switch is closed, wherein the logic control element generates a control for the first based on a clock signal a first switch control signal for closing and opening of the switch, a second switch control signal for controlling closing and opening of the second switch, and a third switch for controlling the third switch Engaged with the third switching control signal off. The control device of claim 1, wherein the gate of the analog power switch is connected to the ground via a fourth switch, and the logic control element is controlled by controlling the closing and opening of the fourth switch. The analog power switch is enabled and disabled. The control device of claim 1, further comprising: a voltage selection element configured to select one of a ramp voltage and a constant voltage as the input voltage. The control device of claim 3, wherein the voltage selection element selects one of the ramp voltage and the constant voltage as the input voltage under control of the logic control element. The control device of claim 1, wherein the diode is implemented by a P-channel metal oxide semiconductor transistor in which a gate and a source are connected together. The control device of claim 2, wherein the first switch and the The second switch is implemented by a P-channel metal oxide semiconductor transistor, and the third switch and the fourth switch are implemented by an N-channel metal oxide semiconductor transistor. The control device of claim 2, wherein the first to fourth switches are implemented by a transfer gate. The control device of claim 2, wherein the internal resistances of the first to fourth switches are formulated according to their respective switching speeds and conduction capabilities. The control device according to claim 1, wherein the input voltage is one of a ramp voltage and a constant voltage or a combination thereof. A control method for an analog power switch, comprising: connecting an upper plate of a capacitor to a gate of an analog power switch via a diode and connecting with an input voltage via a first switch; and causing a lower plate of the capacitor to pass through the second switch Connected to a source of the analog power switch and connected to ground via a third switch; and control the capacitor by controlling closing and opening of the first switch, the second switch, and the third switch Charging and discharging, thereby controlling the analog power switch to be turned on and off, wherein the capacitor is charged when the first switch and the third switch are closed, and the second switch is turned off, when the first switch and The third switch is turned off, and the capacitor is discharged when the second switch is closed, wherein a first switch control signal for controlling closing and opening of the first switch is generated based on a clock signal for controlling the A second switch control signal for closing and opening of the second switch, and a third switch control signal for controlling closing and opening of the third switch. The control method of claim 10, further comprising: connecting a gate of the analog power switch to a ground via a fourth switch; controlling the analogy by controlling closing and opening of the fourth switch The power switch is enabled and disabled. The control method described in claim 10, further comprising: One of the ramp voltage and the constant voltage or a combination thereof is used as the input voltage. The control method of claim 10, wherein the diode is implemented using a P-channel metal oxide semiconductor transistor in which a gate and a source are connected together. The control method of claim 11, wherein the first switch and the second switch are implemented using a P-channel metal oxide semiconductor transistor, and an N-channel metal oxide semiconductor transistor is used The third switch and the fourth switch are implemented. The control method of claim 11, wherein the first to fourth switches are implemented using a transmission gate. The control method according to claim 11, wherein the internal resistances of the first to fourth switches are adjusted according to their respective switching speeds and conduction capacities.