CN106027013B - Control device and control method for analog power switch - Google Patents
Control device and control method for analog power switch Download PDFInfo
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- CN106027013B CN106027013B CN201610464952.8A CN201610464952A CN106027013B CN 106027013 B CN106027013 B CN 106027013B CN 201610464952 A CN201610464952 A CN 201610464952A CN 106027013 B CN106027013 B CN 106027013B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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Abstract
The invention provides a control device and a control method for an analog power switch. The control device for an analog power switch comprises: a capacitor, an upper plate of which is connected to a gate of the analog power switch via a diode and to the input voltage via a first switch, and a lower plate of which is connected to a source of the analog power switch via a second switch and to ground via a third switch; and the logic control component is configured to control the capacitor to be charged and discharged by controlling the first switch, the second switch and the third switch to be closed and opened so as to control the analog power switch to be switched on and off, wherein the capacitor is charged when the first switch and the third switch are closed and the second switch is opened, and the capacitor is discharged when the first switch and the third switch are opened and the second switch is closed.
Description
Technical Field
The present invention relates to the field of circuits, and more particularly, to a control apparatus and a control method for an analog power switch.
Background
Currently, analog power switches are widely used in various circuit systems. When the analog power switch is applied in a circuit system, it may be controlled to be turned on and off by controlling a voltage difference value Vgs (Vgate-Vsource) between a gate voltage (Vgate) and a source voltage (Vsource) of the analog power switch. Specifically, when Vgs < Vth, the analog power switch is turned off; when Vgs ≧ Vth, which is the turn-on threshold voltage of the analog power switch, the analog power switch turns on, and its turn-on impedance decreases with increasing Vgs.
Fig. 1 is a schematic diagram of an example application of an analog power switch (e.g., an N-channel metal oxide semiconductor (NMOS) power tube). As shown in fig. 1, the NMOS power transistor is included in the chip C; the chip C has three terminals of VIN, VOUT and GND, and comprises three parts of an NMOS power tube, a gate drive circuit and a control circuit. The drain electrode of the NMOS power tube is connected with a VIN terminal, and an input voltage VIN is input to the drain electrode of the NMOS power tube through the VIN terminal; the source electrode of the NMOS power tube is connected with a VOUT terminal, and the output voltage VOUT is supplied to a load through the VOUT terminal; the control circuit generates a control signal for controlling the NMOS power tube to be switched on and switched off; the grid driving circuit generates a driving signal for driving the NMOS power tube to be switched on and switched off based on the control signal generated by the control circuit and provides the driving signal to the grid of the NMOS power tube.
Before the NMOS power tube is conducted, the VOUT terminal is grounded; when Vgs is larger than or equal to Vth, the NMOS power tube is conducted. Because the on-resistance of the turned-on NMOS power tube is very small, the VOUT terminal and the VIN terminal can be regarded as a short circuit, and therefore the output voltage VOUT is increased to the input voltage VIN after the NMOS power tube is turned on. In order to maintain the conduction state of the NMOS power tube, the grid drive circuit is configured to control the grid voltage Vgate of the NMOS power tube to be higher along with the rising of the output voltage VOUT, namely, the grid voltage Vgate is maintained to be more than or equal to VOUT + Vth, so that the conduction condition that Vgs is more than or equal to Vth can be ensured to be met.
In general, the gate driving circuit generates a driving signal in any one of a Bootstrap method and a charge pump method. However, both the Bootstrap mode and the charge pump mode generally require a large external capacitor, and the chip C generally cannot integrate such a large capacitor due to cost considerations.
Disclosure of Invention
The invention provides a control device and a control method for an analog power switch.
The control device for the analog power switch according to the embodiment of the invention comprises: a capacitor, an upper plate of which is connected to a gate of the analog power switch via a diode and to the input voltage via a first switch, and a lower plate of which is connected to a source of the analog power switch via a second switch and to ground via a third switch; and the logic control component is configured to control the capacitor to be charged and discharged by controlling the first switch, the second switch and the third switch to be closed and opened so as to control the analog power switch to be switched on and off, wherein the capacitor is charged when the first switch and the third switch are closed and the second switch is opened, and the capacitor is discharged when the first switch and the third switch are opened and the second switch is closed.
The control method for the analog power switch comprises the following steps: connecting an upper plate of a capacitor to a gate of an analog power switch via a diode and to an input voltage via a first switch; connecting the lower plate of the capacitor to the source of the analog power switch via a second switch and to ground via a third switch; and controlling the capacitor to be charged and discharged by controlling the first switch, the second switch and the third switch to be closed and opened so as to control the analog power switch to be switched on and off, wherein the capacitor is charged when the first switch and the third switch are closed and the second switch is opened, and the capacitor is discharged when the first switch and the third switch are opened and the second switch is closed.
In the control device and method for the analog power switch according to the embodiment of the invention, the voltage difference between the upper and lower plates of the capacitor is not large, so that a large capacitor or a cascade capacitor is not required to be adopted to realize a capacitor with high withstand voltage, and the cost of a chip for realizing the control device and method for the analog power switch according to the embodiment of the invention can be effectively reduced.
Drawings
The invention may be better understood from the following description of specific embodiments thereof taken in conjunction with the accompanying drawings, in which like reference numerals identify identical or functionally similar elements:
FIG. 1 is a schematic diagram of an example application of an analog power switch (e.g., an N-channel metal oxide semiconductor (NMOS) power tube);
fig. 2 is an example circuit diagram of a conventional charge pump used in the gate driving circuit shown in fig. 1;
fig. 3 is an example circuit diagram of a conventional charge pump using cascade capacitors used in the gate driving circuit shown in fig. 1;
FIG. 4 is a schematic diagram of a charge pump for use in the gate drive circuit shown in FIG. 1, according to an embodiment of the present invention;
fig. 5 shows a timing diagram of signals related to the logic control circuit shown in fig. 4.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is in no way limited to any specific configuration and algorithm set forth below, but rather covers any modification, replacement or improvement of elements, components or algorithms without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present invention.
Fig. 2 is an example circuit diagram of a conventional charge pump used in the gate driving circuit shown in fig. 1. In the case of the high voltage application of the charge pump shown in fig. 2, since the voltage difference between the upper and lower plates of the capacitors C1 and C2 is too large, a capacitor with high withstand voltage needs to be realized by cascading capacitors, which may result in a significant increase in the cost of the chip C.
Fig. 3 is an example circuit diagram of a conventional charge pump using cascade capacitors used in the gate driving circuit shown in fig. 1. In the charge pump shown in fig. 3, the problem of withstand voltage of the upper and lower plates of the capacitors C1 and C2 is solved by adopting a series capacitor method. However, as shown in fig. 3, the capacitors C1 and C2 and their series capacitors C3-C6 commonly introduce parasitic capacitances to ground (e.g., C1p, C2p, C3p, C4p), which may reduce the equivalent capacitance value of the capacitors C1-C6 in the operating state. Therefore, more capacitors need to be cascaded to achieve the same effect, which further increases the cost of chip C.
To solve one or more problems in the charge pump described in conjunction with fig. 2 and 3, a novel charge pump for use in the gate driving circuit shown in fig. 1 is proposed to effectively reduce the cost of the chip C. A charge pump used in the gate driving circuit shown in fig. 1 according to an embodiment of the present invention is described in detail below with reference to the accompanying drawings.
Fig. 4 is a schematic diagram of a charge pump for use in the gate driving circuit shown in fig. 1 according to an embodiment of the present invention. As shown in fig. 4, the charge pump according to the embodiment of the present invention includes a charge pump main circuit 410, a voltage select (Vse1) circuit 420, and a logic control circuit 430. Specifically, the method comprises the following steps:
the charge pump main circuit 410 comprises switches P1, P3, N1-N4, a capacitor C0 and a diode D0; the VS terminal of the charge pump main circuit 410 is connected to the output of the Vse1 circuit 420, the GATE terminal of the charge pump main circuit 410 is connected to the GATE of the NMOS power transistor, and the VOUT terminal of the charge pump main circuit 410 is connected to the source of the NMOS power transistor.
The logic control circuit 430 receives the switch enable signal MOS _ EN, the soft start signal SST, and the clock signal CLK, generates the switch control signal SD based on the switch enable signal MOS _ EN, generates the voltage selection signals PH1 and PH2 based on the switch enable signal MOS _ EN and the soft start signal SST, and generates the switch control signals PA, PB, and PC based on the switch enable signal MOS _ EN and the clock signal CLK. Wherein:
PH1＝SST·MOS_EN，
That is, when MOS _ EN is equal to 1, PH1 is equal to SST,
when MOS _ EN is equal to 0, PH1 is equal to PH2 is equal to 0.
Fig. 5 shows a timing diagram of signals related to the logic control circuit shown in fig. 4. It should be noted that, since the logic control circuit has a certain delay, the waveforms of the switch control signals PA, PB, and PC are not exactly aligned with the clock signal CLK.
The actions of the above signals and the operation of the charge pump main circuit 410 are described in detail below with reference to fig. 4 and 5:
the switch enable signal MOS _ EN indicates whether the NMOS power transistor is enabled, and the switch control signal SD controls the switch N4 to be turned on and off so as to control whether the NMOS power transistor is enabled. Specifically, when the switch enable signal MOS _ EN is at a high level, the switch control signal SD is at a low level, the switch N4 is turned off, and the NMOS power transistor is enabled; when the switch enable signal MOS _ EN is at a low level, the switch control signal SD is at a high level, the switch N4 is closed, the gate of the NMOS power transistor is grounded, and the NMOS power transistor is disabled.
The soft-start signal SST indicates whether a soft-start process is employed, and the voltage selection signals PH1 and PH2 control the Vse1 circuit 420 to select one of the constant voltage AVDD and the ramp voltage Vramp to be provided to the charge pump main circuit 410 (hereinafter, the selected voltage is referred to as a voltage VS for convenience). Specifically, when the soft-start signal SST is at a high level, the voltage selection signal PH1 is at a high level, the voltage selection signal PH2 is at a low level, and the Vse1 circuit 420 selects the ramp voltage Vramp as the voltage VS to be provided to the charge pump main circuit 410 (i.e., a soft-start process is employed); when the soft-start signal SST is low, the voltage selection signal PH1 is low, the voltage selection signal PH2 is high, and the Vse1 circuit 420 selects the constant voltage AVDD as the voltage VS to be provided to the charge pump main circuit 410 (i.e., without a soft-start process).
The clock signal CLK provides a clock signal of a certain frequency. The switch control signal PA controls the switch N2 to be closed and opened; the switch control signal PB controls the closing and opening of the switches N3 and P3 (the switch P3 is closed or opened simultaneously with the switch N3); the switch control signal PC controls the closing and opening of the switches N1 and P1 (the switches P1 and N1 are closed or opened simultaneously).
As is apparent from the above description, the logic control circuit 430 generates the voltage selection signals PH1 and PH2 based on the soft start signal SST and generates the switching control signals PA, PB, and PC based on the clock signal CLK in the case where the NMOS transistors are enabled.
In the case where the NMOS transistor is enabled, when the soft start process is employed, the charge pump main circuit 410 switches between a first state and a second state described below, thereby achieving control of the gate voltage of the NMOS power transistor. Specifically, the method comprises the following steps:
in the first state, N2 is on, P1 is on, P3 is off, N4 is off, the lower plate of the capacitor C0 is grounded, the upper plate of the capacitor C0 is connected to the voltage VS, and at this time, the capacitor C0 charges until the voltage between the upper and lower plates of the capacitor C0 reaches the voltage VS.
In the second state, N2 is off, P1 is off, P3 is on, N4 is off, and the lower plate of the capacitor C0 is connected with the output voltage VOUT; since the voltage between the upper and lower plates of the capacitor C0 cannot change abruptly, the upper plate voltage VCP of the capacitor C0 is raised to VOUT + VS instantly, and at this time, the upper plate voltage VCP of the capacitor C0 charges the gate voltage of the NMOS power transistor through the diode D0.
Through switching of the charge pump main circuit 410 between the first state and the second state for a plurality of times, a voltage difference value Vgs between a gate voltage Vgate and a source voltage Vsource of the NMOS power tube gradually increases to a peak value of a voltage Vramp (the peak value is greater than or equal to Vth), and the NMOS power tube is turned on.
Here, the magnitude of the internal resistances of the switches N2, P1 and P3 determines the switching speed and the conduction capability of the switches, which in turn determine the charging or discharging speed of the capacitor C0, so that the proper internal resistances can be set for the switches according to the charging or discharging speed of the capacitor C0 to be controlled; the magnitude of the internal resistance of the switch N4 determines the switching speed and the conducting capability of the switch N4, and the switching speed and the conducting capability of the switch N4 determine the discharging speed of the gate of the NMOS transistor, so that the proper internal resistance can be set for the switch N4 according to the discharging speed of the gate of the NMOS transistor to be controlled. That is, the internal resistances of the switches N2, P1, P3, N4 can be adjusted as required according to the switching speeds and the conduction capabilities of the switches N2, P1, P3, N4, respectively.
As can be seen from the above description, in the charge pump shown in fig. 4, the voltage difference between the upper and lower plates of the capacitor C0 is not large, so that it is not necessary to use a large capacitor or a cascade capacitor to realize a high withstand voltage capacitor, and thus the cost of the chip C can be effectively reduced.
In some embodiments, the logic control circuit 430 may also not receive the soft start signal SST and not generate the voltage selection signals PH1 and PH2, and at this time, may adopt only one of the constant voltage AVDD and the ramp voltage Vramp as the voltage VS.
In the case of using the constant voltage AVDD as the voltage VS, when the charge pump main circuit 410 is in the second state, the upper plate voltage VCP of the capacitor C0 is immediately raised to VOUT + AVDD, so that the gate voltage Vgate of the NMOS power transistor is rapidly increased to VOUT + AVDD.
In the case of using the ramp voltage Vramp (e.g., from 0V to AVDD) as the voltage VS, the upper plate voltage VCP of the capacitor C0 is gradually raised to VOUT + AVDD through a plurality of switching of the charge pump main circuit 410 between the first state and the second state, so that the gate voltage Vgate of the NMOS power transistor is gradually increased, thereby achieving a soft start of the NMOS power transistor.
In some embodiments, a combination of the constant voltage AVDD and the ramp voltage Vramp may also be employed as the voltage VS (i.e., the soft-start signal SST and the voltage selection signals PH1 and PH2 are not required). In this case, the soft start may be performed first with the ramp voltage Vramp, and then the gate voltage Vgate of the NMOS power transistor may be increased to VOUT + AVDD finally with the constant voltage AVDD.
In some embodiments, the switches P1 and P3 shown in fig. 4 may be implemented as P-channel metal-oxide-semiconductor (PMOS) transistors, and the switches N1-N4 may be implemented as NMOS transistors. In addition, the diode D0 shown in fig. 4 may be implemented as a PMOS transistor with the gate and source connected together. In other embodiments, the switch shown in FIG. 4 may also be implemented using transmission gates.
As can be seen in fig. 1 to 5, the present invention provides a control device for an analog power switch (e.g., NMOS power transistor), comprising: a capacitor (e.g., a capacitor C0) having an upper plate connected to the gate of the analog power switch via a diode (e.g., a diode D0) and to the input voltage (e.g., a constant voltage AVDD, a ramp voltage Vramp, or a combination thereof) via a first switch (e.g., a switch P1), and a lower plate connected to the source of the analog power switch via a second switch (e.g., a switch P3) and to ground via a third switch (e.g., a switch N2); and a logic control component (e.g., logic control circuit 430) configured to control the capacitor to charge and discharge by controlling the first switch, the second switch, and the third switch to be closed and opened, thereby controlling the analog power switch to be turned on and off, wherein the capacitor is charged when the first switch and the third switch are closed and the second switch is opened, and the capacitor is discharged when the first switch and the third switch are opened and the second switch is closed.
In other words, the present invention provides a control method for an analog power switch (e.g., NMOS power transistor), comprising: connecting an upper plate of a capacitor (e.g., capacitor C0) to a gate of an analog power switch via a diode (e.g., diode D0) and to an input voltage (e.g., constant voltage AVDD, ramp voltage Vramp, or a combination thereof) via a first switch (e.g., switch P1); connecting the lower plate of the capacitor to the source of the analog power switch via a second switch (e.g., switch P3) and to ground via a third switch (e.g., switch N2); and controlling the capacitor to be charged and discharged by controlling the first switch, the second switch and the third switch to be closed and opened so as to control the analog power switch to be switched on and off, wherein the capacitor is charged when the first switch and the third switch are closed and the second switch is opened, and the capacitor is discharged when the first switch and the third switch are opened and the second switch is closed.
In the control device and method for the analog power switch according to the embodiment of the invention, the voltage difference between the upper and lower plates of the capacitor is not large, so that a large capacitor or a cascade capacitor is not required to be adopted to realize a capacitor with high withstand voltage, and therefore, the cost of a chip C for realizing the control device and method for the analog power switch according to the embodiment of the invention can be effectively reduced.
The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (18)
1. A control device for an analog power switch, comprising:
a charge pump circuit including a capacitor, a diode, a first switch, a second switch, and a third switch, an upper plate of the capacitor being connected with a gate of the analog power switch via the diode and with an input voltage via the first switch, a lower plate of the capacitor being connected with a source of the analog power switch via the second switch and with a ground via the third switch; and
a logic control component configured to control the capacitor to charge and discharge by controlling the first switch, the second switch, and the third switch to be closed and opened, thereby controlling the analog power switch to be turned on and off
In a first state, the first switch and the third switch are closed, the second switch is opened, the lower plate of the capacitor is grounded, the upper plate of the capacitor is connected with the input voltage, the capacitor is charged until the voltage between the upper plate and the lower plate of the capacitor reaches the input voltage,
in a second state, the first switch and the third switch are turned off, the second switch is turned on, the lower plate of the capacitor is connected with the source of the analog power switch, the voltage of the upper plate of the capacitor is instantly raised to the sum of the source voltage of the analog power switch and the input voltage, the voltage of the upper plate of the capacitor charges the gate voltage of the analog power switch, and
wherein the charge pump circuit causes the analog power switch to turn on by switching between the first state and the second state a plurality of times such that a voltage difference between a gate voltage and a source voltage of the analog power switch increases beyond a turn-on threshold voltage of the analog power switch.
2. The control apparatus of claim 1, wherein the logic control component generates a first switch control signal for controlling the closing and opening of the first switch, a second switch control signal for controlling the closing and opening of the second switch, and a third switch control signal for controlling the closing and opening of the third switch based on a clock signal.
3. The control device of claim 1, wherein a gate of the analog power switch is connected to ground via a fourth switch, the logic control component controlling enabling and disabling of the analog power switch by controlling closing and opening of the fourth switch.
4. The control device of claim 1, further comprising:
a voltage selection component configured to select one of a ramp voltage and a constant voltage as the input voltage.
5. The control apparatus of claim 4, wherein the voltage selection component selects one of the ramp voltage and the constant voltage as the input voltage under control of the logic control component.
6. The control device of claim 1, wherein the diode is implemented by a P-channel metal-oxide-semiconductor transistor with a gate and a source connected together.
7. The control apparatus of claim 3, wherein the first switch and the second switch are implemented by P-channel metal oxide semiconductor transistors, and the third switch and the fourth switch are implemented by N-channel metal oxide semiconductor transistors.
8. The control apparatus of claim 3, wherein the first to fourth switches are implemented by transmission gates.
9. The control device of claim 3, wherein the internal resistances of the first through fourth switches are adapted according to their respective switching speeds and conduction capabilities.
10. The control device of claim 1, wherein the input voltage is one of a ramp voltage and a constant voltage or a combination thereof.
11. A control method for an analog power switch, comprising:
connecting an upper plate of a capacitor in the charge pump circuit to a gate of the analog power switch via a diode and to the input voltage via a first switch;
connecting a lower plate of a capacitor to a source of the analog power switch via a second switch and to ground via a third switch; and
controlling the capacitor to charge and discharge by controlling the first switch, the second switch, and the third switch to be turned on and off, thereby controlling the analog power switch to be turned on and off
In a first state, the first switch and the third switch are closed, the second switch is opened, the lower plate of the capacitor is grounded, the upper plate of the capacitor is connected with the input voltage, the capacitor is charged until the voltage between the upper plate and the lower plate of the capacitor reaches the input voltage,
in a second state, the first switch and the third switch are turned off, the second switch is turned on, the lower plate of the capacitor is connected with the source of the analog power switch, the voltage of the upper plate of the capacitor is instantly raised to the sum of the source voltage of the analog power switch and the input voltage, the voltage of the upper plate of the capacitor charges the gate voltage of the analog power switch, and
wherein the charge pump circuit causes the analog power switch to turn on by switching between the first state and the second state a plurality of times such that a voltage difference between a gate voltage and a source voltage of the analog power switch increases beyond a turn-on threshold voltage of the analog power switch.
12. The control method of claim 11, wherein a first switch control signal for controlling the closing and opening of the first switch, a second switch control signal for controlling the closing and opening of the second switch, and a third switch control signal for controlling the closing and opening of the third switch are generated based on a clock signal.
13. The control method according to claim 11, further comprising:
connecting a gate of the analog power switch to ground via a fourth switch;
controlling enabling and disabling of the analog power switch by controlling closing and opening of the fourth switch.
14. The control method according to claim 11, further comprising:
one of a ramp voltage and a constant voltage or a combination thereof is used as the input voltage.
15. The control method of claim 11, wherein the diode is implemented using a P-channel metal oxide semiconductor transistor with a gate and a source connected together.
16. The control method of claim 13, wherein the first switch and the second switch are implemented using P-channel metal oxide semiconductor transistors, and the third switch and the fourth switch are implemented using N-channel metal oxide semiconductor transistors.
17. The control method of claim 13, wherein the first to fourth switches are implemented using transmission gates.
18. The control method according to claim 13, wherein the internal resistances of the first to fourth switches are adjusted in accordance with their respective switching speeds and conduction capacities.
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| CN201610464952.8A CN106027013B (en) | 2016-06-23 | 2016-06-23 | Control device and control method for analog power switch |
| TW105123297A TWI593231B (en) | 2016-06-23 | 2016-07-22 | A control device and control method for analog power switch |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332898A (en) * | 2011-08-17 | 2012-01-25 | 深圳市英唐数码电器有限公司 | Switching circuit with zero standby power consumption |
| CN103125071A (en) * | 2010-08-18 | 2013-05-29 | 美国亚德诺半导体公司 | Charge sharing analog computation circuitry and applications |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345520B (en) * | 2008-08-20 | 2011-09-28 | 启攀微电子（上海）有限公司 | Anti-back flow circuit |
| WO2010034162A1 (en) * | 2008-09-28 | 2010-04-01 | Bosch Power Tools (China) Co., Ltd. | Control device for controlling a motor in a low voltage dc power tool and control method thereof |
| CN101867364A (en) * | 2009-04-16 | 2010-10-20 | 皓威科技有限公司 | Output stage circuit for capacitively loaded driver and control method thereof |
| CN102394608B (en) * | 2011-09-28 | 2014-06-04 | 上海复旦微电子集团股份有限公司 | Oscillator circuit |
| US9483065B2 (en) * | 2012-05-23 | 2016-11-01 | Texas Instruments Incorporated | Power regulation with load detection |
| CN102983561B (en) * | 2012-11-15 | 2017-05-31 | 上海航空电器有限公司 | A kind of accumulator of under-voltage surge protection |
| CN103325338B (en) * | 2013-06-18 | 2015-06-24 | 京东方科技集团股份有限公司 | AMOLED driving circuit, AMOLED driving method and AMOLED display device |
| CN103985352B (en) * | 2014-05-08 | 2017-03-08 | 京东方科技集团股份有限公司 | Compensation pixel circuit and display device |
| CN104038072A (en) * | 2014-07-01 | 2014-09-10 | 浙江海得新能源有限公司 | High-voltage input auxiliary power circuit |
| CN104835474B (en) * | 2015-06-02 | 2017-04-05 | 京东方科技集团股份有限公司 | Voltage output device, gate driver circuit and display device |
| CN205336626U (en) * | 2015-12-01 | 2016-06-22 | 科博达技术有限公司 | Discharge lamp's control circuit |
-
2016
- 2016-06-23 CN CN201610464952.8A patent/CN106027013B/en active Active
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103125071A (en) * | 2010-08-18 | 2013-05-29 | 美国亚德诺半导体公司 | Charge sharing analog computation circuitry and applications |
| CN102332898A (en) * | 2011-08-17 | 2012-01-25 | 深圳市英唐数码电器有限公司 | Switching circuit with zero standby power consumption |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106027013A (en) | 2016-10-12 |
| TW201801476A (en) | 2018-01-01 |
| TWI593231B (en) | 2017-07-21 |
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