CN111181560A

CN111181560A - Grid voltage bootstrap switch design applied to high-speed analog-to-digital converter

Info

Publication number: CN111181560A
Application number: CN202010027345.1A
Authority: CN
Inventors: 林鑫; 周雄; 李强
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-01-10
Filing date: 2020-01-10
Publication date: 2020-05-19

Abstract

The gate voltage bootstrapped switch is the most front end of the high-speed analog-to-digital converter, is a vital part in the sample-hold circuit, and is responsible for sampling and holding an input analog signal. The performance of the sampling switch determines the highest resolution and sampling rate that can be achieved by the overall analog-to-digital converter. The traditional grid voltage bootstrap switch is not enough in linearity and sampling rate to be applied to high-speed ADC application due to the structure. The invention provides a grid voltage bootstrap switch applied to a high-speed analog-to-digital converter, which is provided with two parallel paths during sampling, so that the grid voltage can be pulled up to an expected high potential more quickly at the beginning of sampling, the on-resistance of a loop is reduced, the output can start to follow an input signal in a shorter time, and the parasitic capacitance of the switch is correspondingly reduced due to the optimization of the structure. The design enables the grid voltage bootstrapped switch to achieve a higher sampling rate and better linearity, so that the grid voltage bootstrapped switch is very suitable for a high-speed analog-to-digital converter.

Description

Grid voltage bootstrap switch design applied to high-speed analog-to-digital converter

Technical Field

The invention provides a gate voltage Bootstrap Switch (Bootstrap Switch), which belongs to the technical field of Analog integrated circuits, and is suitable for being used as a sampling Switch of a sampling holding circuit in an Analog to digital Converter (ADC) due to the characteristics of high sampling speed and high linearity.

Background

An analog-to-digital converter (hereinafter referred to as ADC) is used as a bridge for connecting the analog world and digital signal processing, and is used for converting external continuously-changing analog quantity into digital signals which are easy to be processed by digital signals, wherein the high-speed ADC is developed rapidly due to wide application fields, such as digital measurement, software radio, radar and the like. As the foremost end of the high-speed ADC, the sample-and-hold circuit plays a vital role, and the accuracy and the sampling rate which can be realized by the sample-and-hold circuit determine the highest resolution and the fastest conversion rate which can be achieved by the whole ADC, so that the design of the sample-and-hold circuit is more critical.

The sample-and-hold circuit functions to sample and hold the input signal periodically, with the sample period and hold period typically each taking one-half of the clock period, i.e., a duty cycle of 0.5. When the sampling hold circuit is in a sampling period, the sampling capacitor stores an input signal, and the output changes along with the input change; when the sampling capacitor is in the holding period, the sampling capacitor is disconnected from the input signal, the output is held at the value of the input signal at the end of the sampling period, and the output is held until the next sampling period.

The performance of the sampling switch in the sample-and-hold circuit is a key module determining the performance of the whole circuit, so that it is important to design a switch with high sampling speed and high linearity. There are generally three types of sampling switches: the single MOS tube can be an NMOS tube or a PMOS tube; the complementary switch is formed by connecting an NMOS tube and a PMOS tube in parallel; the bootstrap switch is composed of a circuit. The three switches have advantages and disadvantages, and the single-tube switch has the main advantages of simple structure, low linearity and obvious change of on-resistance along with input voltage; the structure of the complementary switch is simpler, the on-resistance is smaller than that of a single-tube switch, and the complementary switch can be used in conventional applications; the bootstrap switch has small on-resistance, highest linearity and large input range, but the structure is more complex than the former two kinds, and the bootstrap switch has higher power consumption, so that the bootstrap switch is the optimal choice in the situation with higher requirements on precision and linearity.

A schematic diagram of the basic concept of a gate voltage bootstrapped switch is shown in fig. 1. The switches operate on two non-overlapping clock signals CLK and CLKB. When the switch is in an open state (CLK is low, CLKB is high), SW1, SW2 and SW4 are closed, the power supply voltage charges the capacitor C1 to the power supply voltage Vdd, SW3 and SW5 are open, the voltage at point G is pulled to ground, which is also referred to as a hold state; when the sampling circuit is in a sampling state, namely when the switch is closed (CLK is high, CLKB is low), SW1, SW2 and SW4 are opened, SW3 and SW5 are closed to form a loop, at the moment, the upper electrode of the capacitor C1 is connected to the grid electrode of the sampling tube, the lower electrode is connected to the source electrode of the sampling tube, and the input signal is also connected to the source electrode of the sampling tube, so that the grid voltage of the sampling tube can be pulled to Vdd + Vin, the grid source voltage Vgs is equal to Vdd, and the on-resistance of the switch does not change along with the change of the input signal and is stabilized at a fixed value, thereby reducing harmonic distortion and improving the linearity of the sampling switch. In the sampling phase, when CLKB is low, M7 is turned on, pulling down the gate of M9 transistor, turning on M9 so that the gate voltages of M10 and Ms are pulled high and turned on, and finally the VG point voltage is pulled close to Vdd + Vin in the following state, as shown in fig. 2. During the hold phase, CLKB is high, M1 and M2 turn on to charge capacitor Cb, and M13 turns on to let VG point voltage be pulled low, leaving sample tube Ms off and the output no longer following the input change. The main disadvantage of the conventional structure is that the parasitic capacitance and the on-resistance of the G point are large, which results in the bandwidth of the sampling switch being reduced, so that the sampling rate is not enough to deal with the ADC with a relatively high sampling rate.

Disclosure of Invention

The invention provides a grid voltage bootstrap switch applied to a high-speed analog-to-digital converter. When sampling high frequency input signals, the non-linearity of the sampling switch is mainly due to the combined effect of the on-resistance associated with the signal and the parasitic capacitance of the sampling tube, and the time constant created by the resistance and capacitance also determines the maximum sampling rate of the switch. Therefore, the invention carries out corresponding optimization design on the traditional grid voltage bootstrap circuit aiming at the two influences, thereby obtaining the bootstrap switch with high sampling rate and high linearity.

Fig. 3 shows a schematic diagram of a gate voltage bootstrapped switch applied to a high-speed analog-to-digital converter according to the present invention. As with the conventional gate voltage bootstrapped switch, two non-overlapping clocks are required for control, and while maintaining the phase, the gate voltage VG of the sampling tube Ms is pulled low and the sampling tube Ms is turned off, while the capacitor Cb is charged to the power supply voltage Vdd. During sampling phase, two ends of the capacitor Cb are respectively connected to the gate and the source of the sampling tube Ms through the conductive M9 tube and the conductive M10 tube, so that the voltage of VG is Vdd + Vin, the gate-source voltage of the sampling tube can be basically stabilized at a power voltage without considering parasitics, the on-resistance is not related to the input signal as much as possible, and better linearity is realized.

The main optimization design of the invention is to reduce the on-resistance of the switch and the parasitic capacitance on the grid electrode of the sampling tube, so that the switch can achieve higher sampling rate and better linearity. The conventional gate-voltage bootstrapped switch has several disadvantages, as shown in fig. 2, the critical path M10-Cb-M9 when the switch is first turned on is sampled and a series resistor R is introduced_M10And R_M9Parasitic capacitance C_VG+C_PThe time constant RC is increased, the bandwidth of the switch is limited, and the sampling linearity of the high-frequency input signal is reduced; secondly, large parasitic capacitance is introduced into M5, M9, M10 and M12, so that the voltage of VG is smaller than Vdd + Vin when the switch performs sampling, and for this reason, a larger capacitance Cb is needed to reduce this influence, but too large Cb causes the voltage of VG to rise slowly when the sampling time comes, and also causes the sampling rate to slow down; finally, the traditional gate voltage bootstrapped switch is M9 leading-in, so that VG is connected to the upper board of the capacitor Cb, VG is pulled high, M10 is conducted, and obviously, the connection of the whole key loop is slower. Aiming at the disadvantages of the traditional grid voltage bootstrap switch, the M3-M5 tube introduced by the invention enables the M10 tube to be disconnected from a sampling key path, the M9 and the M10 work in a parallel state, namely, the M9 and the M10 are conducted simultaneously during sampling, and the M9 and the M10 are conducted simultaneously, so that the two tubes can have the maximum grid source voltage just at the beginning of sampling, and therefore, a smaller conducting resistance is obtained, and the voltage of a VG point rises more quickly at the beginning of sampling. In addition, M10 is disconnected from the critical path, so that the parasitic capacitance is obviously reduced, the voltage of the VG point and the bandwidth of the switch can be improved, and the voltage of the VG point can be pulled to a low level more quickly at the end of the sampling phase, so that the VG point can be pulled to a low levelThe instantaneous state of the sampling can be better controlled.

Drawings

Fig. 1 is a schematic diagram of the basic concept of a gate voltage bootstrapped switch.

Fig. 2 is a structural diagram of a conventional gate voltage bootstrapped switch.

Fig. 3 is a structural diagram of the gate voltage bootstrapped switch of the present invention.

Detailed Description

The embodiments and technical details of the present invention will be described in detail below with reference to specific embodiments and the accompanying drawings.

The grid voltage bootstrap switch provided by the invention is suitable for a sampling hold circuit of a high-speed analog-digital converter. Fig. 3 is a structural diagram of the gate voltage bootstrap switch according to the present invention.

The gate voltage bootstrapped switch designed by the invention is respectively controlled by two non-overlapping clocks CLK and CLKB. When the circuit is in the hold state, CLK is low and CLKB is high. The low CLK turns on PMOS transistor M8, the on M8 turns on VP high, and the high VP turns off the M5 and M9 transistors. CLKB is high turning on NMOS transistors M1, M3, and M13, while M3 is on turning VN low turning off the M10 transistor, disconnecting the critical path Ms-M10-Cb-M9. Meanwhile, M1 and M13 are turned on to pull the voltage of the lower plate of the capacitor Cb and the point VG to ground, VG is low to turn off the sampling tube Ms and turn on the PMOS tube M2, and M2 is turned on to pull the upper plate of the capacitor Cb to the power voltage Vdd, thereby completing the charging process of the capacitor Cb.

When the circuit is in the sampling state, CLK is high and CLKB is low. CLKB is low causing M1, M3, and M13 tubes to be disconnected. The transistor CLK is turned on for high M7, so that the bottom plate of Cb is connected to VP, VP is low, so that the M9 transistor and the M5 transistor are turned on, M5 is turned on, and M10 is turned on, and finally the upper plate of the capacitor Cb is connected to the gate of the sampling transistor Ms, and the bottom plate is connected to the source of Ms, so that a loop is formed. In the working mode, the CLKB is low, so that the M14 tube is conducted, the source stage of the M12 is pulled to be high, the VG can be pulled to be high level quickly when the sampling clock arrives, the output voltage can follow the input voltage in a shorter time, and the faster sampling rate is realized. Finally, the sampling loop formed by Ms-M10-Cb-M9 enables the grid voltage of Ms to be Vdd + Vin, so that the grid-source voltage of the sampling tube Ms is close to Vdd. Compared with the traditional grid voltage bootstrap switch, the M3-M5 tube is added to control the M10 tube, so that the M10 tube is separated from a key loop, the input parasitic capacitance and the output resistance are reduced, the sampling rate of the switch is higher, the linearity is better, and the switch is more suitable for the design of a high-speed analog-to-digital converter.

It will be understood by those skilled in the art that various modifications and combinations of modifications may be made to the present invention without departing from the spirit of the present invention, and the scope of the appended claims is to be accorded the full scope of the invention.

Claims

1. The invention provides a grid voltage bootstrap switch design applied to a high-speed analog-to-digital converter, which is characterized in that the grid voltage of a sampling tube can be pulled up to the sum of a power supply voltage and an input signal voltage during sampling, so that the grid source voltage of the sampling tube can be stabilized at a power supply voltage, a conducting resistance irrelevant to an input signal is realized, and the linearity of the whole switch is improved.

2. A gate voltage bootstrapped switch as claimed in claim 1, wherein the gate voltage bootstrapped switch incorporates M3-M5 transistors to disconnect the M10 transistor from the critical path of sampling, so that M9 and M10 operate in parallel, i.e. conduct simultaneously during sampling, and the simultaneous conduction of M9 and M10 makes both transistors have the maximum gate source voltage at the beginning of sampling, thereby obtaining smaller conduction resistance, and making the voltage at VG point rise faster at the beginning of sampling.

3. A gate voltage bootstrapped switch according to claim 1, wherein the gate voltage bootstrapped switch disconnects M10 from the critical path of the sampling, such that the parasitic capacitance is significantly reduced, and therefore the maximum voltage at which point VG is pulled up and the bandwidth of the switch are both improved, and the voltage at point VG can be pulled down to a low level more quickly at the end of the sampling period, thereby better controlling the transient state of the sampling.