CN218976674U

CN218976674U - Grid voltage bootstrapping switch circuit

Info

Publication number: CN218976674U
Application number: CN202223025254.8U
Authority: CN
Inventors: 解宁; 王欣; 陈世军
Original assignee: Shanghai Institute of Technical Physics of CAS
Current assignee: Shanghai Institute of Technical Physics of CAS
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2023-05-05
Anticipated expiration: 2032-11-11

Abstract

The patent belongs to the technical field of integrated circuits, and particularly relates to a gate voltage bootstrap switch circuit. The gate voltage bootstrapping switch circuit comprises a gate voltage bootstrapping circuit, a sampling transistor M10, an input end, an output end and a clock signal CLK; the gate voltage bootstrap circuit includes transistors M1, M2, M3, M4, M5, M6, M8, M9, M11, and M12, and a capacitor C1. This patent has accelerated the sampling rate of grid voltage bootstrap circuit input through the improved design to grid voltage bootstrap circuit to make and compare with traditional grid voltage bootstrap switch circuit, this patent has higher sampling rate and precision.

Description

Grid voltage bootstrapping switch circuit

Technical Field

The patent belongs to the technical field of integrated circuits, and particularly relates to a gate voltage bootstrap switch circuit.

Background

Analog-to-digital converter (ADC) plays a very important role in digital-to-analog hybrid integrated circuit, is the tie connecting analog signal and digital signal, all circuit system and terminal equipment are indispensable part when interacting with nature, and all electronic products are developing to frivolous, portable and wearable orientation now, especially some implanted biochips for treating, monitoring the disease that are very popular now have very high demands on operating duration, therefore whole equipment is higher to battery duration requirement, but receive battery volume and capacity restriction, can only through reducing the consumption of chip self, in order to prolong the operating duration of equipment.

The sample-hold circuit is used as one of the most important modules in an analog-to-digital converter (ADC) circuit and is positioned at the forefront end of the whole ADC circuit to convert an analog signal into a sampling signal for processing by a later-stage circuit, so that the performance of the sample-and-hold circuit is particularly remarkable for the performance of the whole ADC circuit. In the sample hold circuit, the nonlinear factor of the on-resistance of the sampling switch and the influence of channel charge injection and the like on the sampling precision are very remarkable, and in order to reduce the influence, the gate voltage bootstrapping switch circuit is inoculated. As shown in fig. 1, the conventional gate voltage bootstrap switch circuit generally includes two parts, namely a sampling tube M0 and a gate voltage bootstrap circuit T1, the sampling tube M0 is usually an NMOS tube, the source of the sampling tube M0 is connected to the input signal VIN, the drain of the sampling tube M0 generates the output signal VOP, the input terminal 1 of the gate voltage bootstrap circuit T1 is connected to the clock signal CLK, and the input terminal 2 and the output terminal 3 of the gate voltage bootstrap circuit T1 are connected to the source and the gate of the sampling tube M0, respectively.

A low-power-consumption and high-linearity sampling switch is a key of the design of a high-precision and low-power-consumption analog-digital converter. Therefore, it is desirable to design a gate voltage bootstrap circuit with higher speed and accuracy to meet the existing operating scenario requirements.

Disclosure of Invention

This patent lacks the technical problem of a switching circuit that high speed and high accuracy adopted to prior art, aim at provides a grid voltage bootstrap switching circuit.

A gate voltage bootstrapping switch circuit comprises a gate voltage bootstrapping circuit, a sampling tube, an input end, an output end and a clock signal CLK;

the sampling tube adopts a transistor M10;

the grid voltage bootstrap circuit comprises transistors M1, M2, M3, M4, M5, M6, M8, M9, M11 and M12 and a capacitor C1;

the grid of M1 is connected with the grid of M2 and connected to the clock signal CLK, the drain of M1 is connected with the drain of M2 and connected to the grid of M5 and the drain of M6 respectively, the drain of M3 is connected with the source of M2, the lower pole plate of C1 and the source of M6 respectively, the source of M8 and the drain of M9 respectively, the grid of M3 is connected to the inverted signal CLKB of the clock signal CLK, the drain of M4 is connected with the upper pole plate of C1 and the source of M5 respectively, the grid of M4 is connected with the drain of M5, the grid of M6, the grid of M8 and the source of M10 respectively, the source of M8 is connected with the source of M9 and connected to the source of M10, the source of M10 serves as the input end, the drain of M10 serves as the output end, the drain of M11 is connected with the source of M12, the grid of M12 is connected with the grid of M9 and connected to the inverted signal CLKB of the clock signal CLK, the grid of M3 is connected with the source of M12 and connected with the source of M1 and the source of M11 is connected with the ground potential.

Preferably, the transistors M1, M4, M5 and M9 are preferably N-channel insulated gate bipolar transistors, and the transistors M2, M3, M6, M8, M11 and M12 are preferably P-channel insulated gate bipolar transistors.

Preferably, the gate voltage bootstrap circuit further includes a transistor M7, a gate of the transistor M7 is connected to the clock signal CLK, a source of the transistor M7 is connected to the ground potential, and a drain of the transistor M7 is connected to a drain of the transistor M1.

Preferably, the transistor M7 is preferably a P-channel insulated gate bipolar transistor.

The positive progress effect of this patent lies in: the utility model adopts the grid voltage bootstrapping switch circuit, through the improved design to the grid voltage bootstrapping circuit, especially increased transistor M9 and/or transistor M7 in the grid voltage bootstrapping circuit for the sampling rate of grid voltage bootstrapping circuit input to make and compare with traditional grid voltage bootstrapping switch circuit, this patent has higher sampling rate and precision.

Drawings

FIG. 1 is a circuit diagram of a prior art gate voltage bootstrapped switch circuit;

FIG. 2 is a circuit diagram of the present patent;

FIG. 3 is another circuit diagram of the present patent;

fig. 4 is a circuit diagram of comparative example 1.

Detailed Description

In order to make the technical means, the creation features, the achievement of the purpose and the effect of the present patent easy to understand, the present patent is further described below with reference to the specific drawings.

Referring to fig. 2 and 3, a gate voltage bootstrapped switch circuit includes a gate voltage bootstrapped circuit, a sampling transistor M10, an input terminal, an output terminal, and a clock signal CLK. The input terminal is connected to the input signal VIN, the output terminal generates the output signal VOP, and the inverted signal of the clock signal CLK is CLKB.

The gate voltage bootstrap circuit includes transistors M1, M2, M3, M4, M5, M6, M8, M9, M11, and M12, and a capacitor C1. Wherein, the gate of M1 is connected with the gate of M2 and connected to the clock signal CLK, the drain of M1 is connected with the drain of M2 and connected to the gate of M5 and the drain of M6 respectively, the drain of M3 is connected with the source of M2, the lower plate of C1 and the source of M6 respectively, the source of M8 and the drain of M9 respectively, the gate of M3 is connected to the inverted signal CLKB of the clock signal CLK, the drain of M4 is connected with the upper plate of C1 and the source of M5 respectively, the gate of M4 is connected with the drain of M5, the gate of M6, the gate of M8 and the source of M10 respectively, the drain of M8 is connected with the source of M9 and connected to the source of M10, the source of M10 is used as an input terminal, the drain of M11 is connected with the source of M12, the gate of M12 is connected with the gate of M9 and connected to the inverted signal CLKB of the clock signal CLK, the source of M3 is connected with the source of M12 and connected with the source of M1 and the source of M11 and connected with the source of M11.

In some embodiments, transistors M1, M4, M5, and M9 are preferably N-channel insulated gate bipolar transistors, and transistors M2, M3, M6, M8, M11, and M12 are preferably P-channel insulated gate bipolar transistors. If the transistors are designed in reverse, the whole circuit needs to be trimmed.

In some embodiments, referring to fig. 3, the gate voltage bootstrapping circuit further includes a transistor M7, the gate of M7 is connected to the clock signal CLK, the source of M7 is connected to ground potential, and the drain of M7 is connected to the drain of M1.

In some embodiments, transistor M7 is preferably a P-channel insulated gate bipolar transistor. If the transistor M7 is designed as an N-channel insulated gate bipolar transistor, the entire circuit needs to be trimmed.

The grid voltage bootstrapping switch circuit of the patent has two working states, namely a holding state and a sampling state. When the clock signal CLK is low and CLKB is high, the gate voltage bootstrapped switch circuit of this patent is in a hold state. When the clock signal CLK is at a high level and CLKB is at a low level, the gate voltage bootstrapped switch circuit of the present patent is in a sampling state, and samples the input signal VIN at the input end.

When the clock signal CLK is low and CLKB is high, the gate voltage bootstrapped switch circuit of this patent is in a hold state. Transistors M1, M3, M4, M11, and M12 are on, and transistors M2, M5, M6, M7, M8, M9, and M10 are off, resulting in the upper plate of capacitor C1 being charged to the supply potential and the lower plate of capacitor C1 being reset to ground potential. Since the transistor M10 is turned off, the voltage of the output signal VOP generated at the output terminal of the gate voltage bootstrap switch circuit remains unchanged.

When the clock signal CLK is high and CLKB is low, the gate voltage bootstrapped switch circuit of this patent is in a sampling state. The input signal VIN inputted from the input terminal is sampled by the gate voltage bootstrap switch circuit. Transistors M1, M3, M4, M6, M11 and M12 are turned off, transistors M2, M5, M7 and M9 are turned on, capacitor C1 begins to discharge and charges the gate of M8 and the gate of M9, resulting in M8 and M9 being turned on, so that the output signal VOP generated at the output terminal of the gate voltage bootstrap switch circuit follows the input signal VIN at the input terminal, and the sampling process is completed.

Example 1:

the gate voltage bootstrap switching circuit of fig. 2 of this patent was taken as example 1 of this patent, the gate voltage bootstrap switching circuit of fig. 3 of this patent was taken as example 2 of this patent, and fig. 4 with M7 and M9 removed in fig. 3 was taken as comparative example 1. The same input signal VIN is accessed to the patent example 1, the patent example 2 and the comparative example 1, and the sampling speed and the sampling accuracy are compared by adopting a circuit simulation method. The comparison results are shown below:

sampling speed: inventive example 2> inventive example 1> comparative example 1;

sampling precision: inventive example 2> inventive example 1> comparative example 1.

As can be seen from the above, in the utility model example 1, compared with the comparative example 1, the sampling speed of the input signal VIN is greatly increased due to the transistor M9 added in the gate voltage bootstrap circuit.

Compared with the utility model example 1 of the patent, the utility model example 2 of the patent increases the current path and improves the signal sampling speed due to the transistor M7 added in the gate voltage bootstrap circuit.

Compared with the comparative example 1, the utility model example 2 of the patent greatly improves the signal sampling speed due to the fact that the transistors M7 and M9 are added in the grid voltage bootstrap circuit, two current paths are added.

The foregoing has outlined and described the basic principles, main features and advantages of the present patent. Principal line

It will be appreciated by those skilled in the art that the present patent is not limited by the foregoing embodiments, and that the foregoing embodiments and description are merely illustrative of the principles of the patent, and that various changes and modifications may be made therein without departing from the spirit and scope of the patent, which is defined by the appended claims. The scope of protection of this patent is defined by the claims appended hereto and their equivalents.

Claims

1. A gate voltage bootstrapping switch circuit comprises a gate voltage bootstrapping circuit, a sampling tube, an input end, an output end and a clock signal CLK;

the sampling tube is characterized by adopting a transistor M10;

the grid of M1 is connected with the grid of M2 and connected to the clock signal CLK, the drain of M1 is connected with the drain of M2 and connected to the grid of M5 and the drain of M6 respectively, the drain of M3 is connected with the source of M2, the lower polar plate of C1 and the source of M6 respectively, the source of M8 and the drain of M9 are connected, the grid of M3 is connected with the inverted signal CLKB of the clock signal CLK, the drain of M4 is connected with the upper polar plate of C1 and the source of M5 respectively, the grid of M4 is connected with the drain of M5, the grid of M6, the grid of M8 and the source of M10 respectively, the drain of M8 is connected with the source of M9 and connected to the source of M10, the source of M10 serves as the output end, the drain of M11 is connected with the source of M12, the grid of M12 is connected with the grid of M9 and connected with the inverted signal CLKB of the clock signal CLK, and the source of M3 is connected with the source of M12 and connected with the source of M1 and the source of M11.

2. The gate voltage bootstrapped switch circuit of claim 1, wherein the transistors M1, M4, M5, and M9 are N-channel insulated gate bipolar transistors, and the transistors M2, M3, M6, M8, M11, and M12 are P-channel insulated gate bipolar transistors.

3. The gate voltage bootstrapped switch circuit of claim 1 or 2, further comprising a transistor M7, a gate of M7 being connected to the clock signal CLK, a source of M7 being connected to a ground potential, a drain of M7 being connected to a drain of M1.

4. A gate voltage bootstrapped switch circuit as in claim 3, wherein the transistor M7 is a P-channel insulated gate bipolar transistor.