CN115694500A - Grid voltage bootstrap switch circuit - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a gate voltage bootstrap switch circuit. A grid voltage bootstrap switch circuit comprises a grid voltage bootstrap circuit, a sampling transistor M10, an input end, an output end and a clock signal CLK; the grid voltage bootstrap circuit comprises transistors M1, M2, M3, M4, M5, M6, M8, M9, M11 and M12 and a capacitor C1. The invention accelerates the sampling speed of the input end of the grid voltage bootstrap circuit through the improved design of the grid voltage bootstrap circuit, thereby leading the grid voltage bootstrap circuit to have higher sampling speed and precision compared with the traditional grid voltage bootstrap switch circuit.

Description

Grid voltage bootstrap switch circuit

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a gate voltage bootstrap switch circuit.

Background

An analog-to-digital converter (ADC) plays an important role in a digital-to-analog hybrid integrated circuit, which is a link for connecting an analog signal and a digital signal, and all circuit systems and terminal devices are essential for interaction with the nature, and nowadays, all electronic products are developed in the direction of being light, thin, portable and wearable, especially some implantable biochips for treating and monitoring diseases, which are very popular at present, have high requirements on the working time, so that the whole device has high requirements on battery life, but is limited by the battery volume and capacity, and can only prolong the working time of the device by reducing the power consumption of the chip itself.

The sample-and-hold circuit is one of the most important modules in an analog-to-digital converter (ADC) circuit, is located at the foremost end of the whole ADC circuit, and converts an analog signal into a sample signal for processing by a subsequent circuit, so that the performance of the sample-and-hold circuit is particularly significant for the performance of the whole ADC circuit. In the sample-and-hold circuit, the influence of the non-linear factor of the on-resistance of the sampling switch, channel charge injection and the like on the sampling precision is remarkable, and in order to reduce the influence, a gate voltage bootstrap switch circuit is developed. As shown in fig. 1, a conventional gate voltage bootstrap switch circuit generally includes two parts, which are a sampling tube M0 and a gate voltage bootstrap circuit T1, respectively, where the sampling tube M0 is generally an NMOS tube, a source of the sampling tube M0 is connected to an input signal VIN, a drain of the sampling tube M0 generates an output signal VOP, an input end 1 of the gate voltage bootstrap circuit T1 is connected to a clock signal CLK, and an input end 2 and an output end 3 of the gate voltage bootstrap circuit T1 are connected to a source and a gate of the sampling tube M0, respectively.

The low-power consumption and high-linearity sampling switch is a key for designing a high-precision and low-power consumption analog-digital converter. Therefore, it is necessary to design a gate voltage bootstrap circuit with higher adoption speed and precision to meet the existing working scene requirements.

Disclosure of Invention

The invention aims to solve the technical problem that a switch circuit adopted at high speed and high precision is lacked in the prior art, and provides a grid voltage bootstrap switch circuit.

A grid voltage bootstrap switch circuit comprises a grid voltage bootstrap circuit, a sampling tube, an input end, an output end and a clock signal CLK;

the sampling tube adopts a transistor M10;

the grid voltage bootstrap circuit comprises transistors M1, M2, M3, M4, M5, M6, M8, M9, M11 and M12 and a capacitor C1;

the gate of M1 is connected to the gate of M2 and connected to the clock signal CLK, the drain of M1 is connected to the drain of M2 and connected to the gate of M5 and the drain of M6, respectively, the drain of M3 is connected to the source of M2, the bottom plate of C1, the source of M6, the source of M8 and the drain of M9, the gate of M3 is connected to the inverted signal CLKB of clock signal CLK, the drain of M4 is connected to the top plate of C1 and the source of M5, respectively, the gate of M4 is connected to the drain of M5, the gate of M6, the gate of M8, the gate of M10 and the source of M11, the drain of M8 is connected to the source of M10, the source of M10 is used as the input terminal, the drain of M10 is used as the output terminal, the drain of M11 is connected to the source of M12, the gate of M12 is connected to the gate of M9 and connected to the inverted signal CLKB of the clock signal CLK, the source of M3 and the source of M12 is connected to the ground potential, and the source of M1 is connected to the source of M11.

Preferably, the transistors M1, M4, M5, and M9 are N-channel insulated gate bipolar transistors, and the transistors M2, M3, M6, M8, M11, and M12 are P-channel insulated gate bipolar transistors.

Preferably, the gate voltage bootstrap circuit further includes a transistor M7, a gate of the transistor M7 is connected to the clock signal CLK, a source of the transistor M7 is connected to the ground potential, and a drain of the transistor M7 is connected to the drain of the transistor M1.

Preferably, the transistor M7 is a P-channel insulated gate bipolar transistor.

The positive progress effects of the invention are as follows: the invention adopts the grid voltage bootstrap switch circuit, and increases the sampling speed of the input end of the grid voltage bootstrap circuit by improving the design of the grid voltage bootstrap circuit, particularly adding the transistor M9 and/or the transistor M7 in the grid voltage bootstrap circuit, thereby leading the invention to have higher sampling speed and precision compared with the traditional grid voltage bootstrap switch circuit.

Drawings

FIG. 1 is a circuit diagram of a gate voltage bootstrapped switch circuit in the prior art;

FIG. 2 is a circuit diagram of the present invention;

FIG. 3 is another circuit diagram of the present invention;

fig. 4 is a circuit diagram of comparative example 1.

Detailed Description

In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific drawings.

Referring to fig. 2 and 3, a gate voltage bootstrapped switch circuit includes a gate voltage bootstrapped circuit, a sampling transistor M10, an input terminal, an output terminal, and a clock signal CLK. The input end is connected with an input signal VIN, the output end generates an output signal VOP, and the inverted signal of the clock signal CLK is CLKB.

The grid voltage bootstrap circuit comprises transistors M1, M2, M3, M4, M5, M6, M8, M9, M11 and M12 and a capacitor C1. The gate of M1 is connected to the gate of M2 and connected to the clock signal CLK, the drain of M1 is connected to the drain of M2 and connected to the gate of M5 and the drain of M6, respectively, the drain of M3 is connected to the source of M2, the bottom plate of C1 and the source of M6, the source of M8 and the drain of M9, the gate of M3 is connected to the inverted signal CLKB of the clock signal CLK, the drain of M4 is connected to the top plate of C1 and the source of M5, the gate of M4 is connected to the drain of M5, the gate of M6, the gate of M8, the gate of M10 and the source of M11, the drain of M8 is connected to the source of M9, the source of M10 is used as an input terminal, the drain of M10 is used as an output terminal, the drain of M11 is connected to the source of M12, the gate of M12 is connected to the gate of M9 and connected to the inverted signal CLKB of the clock signal CLK, the source of M3 is connected to the source of M12 and connected to the ground potential, and the source of M1 is connected to the source of M11.

In some embodiments, transistors M1, M4, M5, and M9 are preferably N-channel insulated gate bipolar transistors, and transistors M2, M3, M6, M8, M11, and M12 are preferably P-channel insulated gate bipolar transistors. If the transistors are designed in reverse, the whole circuit needs to be trimmed.

In some embodiments, referring to fig. 3, the gate bootstrap circuit further includes a transistor M7, a gate of M7 is connected to the clock signal CLK, a source of M7 is connected to the ground potential, and a drain of M7 is connected to the drain of M1.

In some embodiments, transistor M7 is preferably a P-channel insulated gate bipolar transistor. If the transistor M7 is designed as an N-channel insulated gate bipolar transistor, the entire circuit needs to be trimmed.

The grid voltage bootstrap switch circuit has two working states, namely a holding state and a sampling state. When the clock signal CLK is low and CLKB is high, the gate voltage bootstrapped switch circuit of the present invention is in a hold state. When the clock signal CLK is at a high level and the CLKB is at a low level, the gate voltage bootstrapped switch circuit of the present invention is in a sampling state, sampling the input signal VIN at the input terminal.

When the clock signal CLK is low and CLKB is high, the gate voltage bootstrapped switch circuit of the present invention is in a hold state. Transistors M1, M3, M4, M11, and M12 are turned on, and transistors M2, M5, M6, M7, M8, M9, and M10 are turned off, resulting in the upper plate of capacitor C1 being charged to the power supply potential and the lower plate of capacitor C1 being reset to ground potential. Since the transistor M10 is turned off, the voltage of the output signal VOP generated at the output terminal of the gate-voltage bootstrapped switch circuit remains unchanged.

When the clock signal CLK is high and CLKB is low, the gate voltage bootstrapped switch circuit of the present invention is in a sampling state. An input signal VIN input by the input end is sampled by a grid voltage bootstrap switch circuit. The transistors M1, M3, M4, M6, M11, and M12 are turned off, the transistors M2, M5, M7, and M9 are turned on, the capacitor C1 starts to discharge, and the gate of M8 and the gate of M9 are charged, which causes the transistors M8 and M9 to be turned on, so that the output signal VOP generated at the output terminal of the gate-voltage bootstrapped switch circuit follows the input signal VIN at the input terminal to complete the sampling process.

Example 1:

the gate voltage bootstrapped switch circuit of fig. 2 of the present invention is regarded as inventive example 1, the gate voltage bootstrapped switch circuit of fig. 3 of the present invention is regarded as inventive example 2, and fig. 4 with M7 and M9 removed in fig. 3 is regarded as comparative example 1. The same input signal VIN is accessed to the inventive example 1, the inventive example 2 and the comparative example 1, and the sampling speed and the sampling precision are compared by adopting a circuit simulation method. The comparison results are shown below:

sampling speed: inventive example 2> inventive example 1> comparative example 1;

sampling precision: inventive example 2> inventive example 1> comparative example 1.

As can be seen from the above, in comparison with comparative example 1, in example 1 of the present invention, since the transistor M9 is added in the gate voltage bootstrap circuit, the sampling speed of the input signal VIN is greatly increased.

Compared with the embodiment 1 of the present invention, in the embodiment 2 of the present invention, since the transistor M7 is added to the gate voltage bootstrap circuit, a current path is increased, and a signal sampling speed is increased.

Compared with the comparative example 1, in the example 2 of the invention, because the transistors M7 and M9 are added in the grid voltage bootstrap circuit, two current paths are added, and the signal sampling speed is greatly improved.

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are given by way of illustration of the principles of the present invention, but that various changes and modifications may be made without departing from the spirit and scope of the invention, and such changes and modifications are within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (4)

1. A grid voltage bootstrap switch circuit comprises a grid voltage bootstrap circuit, a sampling tube, an input end, an output end and a clock signal CLK;

the sampling tube is characterized in that a transistor M10 is adopted;

the grid voltage bootstrap circuit comprises transistors M1, M2, M3, M4, M5, M6, M8, M9, M11 and M12 and a capacitor C1;

the gate of M1 is connected with the gate of M2 and connected to the clock signal CLK, the drain of M1 is connected with the drain of M2 and respectively connected to the gate of M5 and the drain of M6, the drain of M3 is connected with the source of M2, the bottom plate of C1 and the source of M6, the source of M8 and the drain of M9, the gate of M3 is connected with the inverted signal CLKB of the clock signal CLK, the drain of M4 is connected with the top plate of C1 and the source of M5, the gate of M4 is connected with the drain of M5, the gate of M6, the gate of M8, the gate of M10 and the source of M11, the drain of M8 is connected with the source of M9 and connected to the source of M10, the source of M10 is used as the input terminal, the drain of M10 is used as the output terminal, the drain of M11 is connected with the source of M12, the gate of M12 is connected with the gate of M9 and connected to the inverted signal CLKB of the clock signal CLK, the source of M3 and the source of M12 are connected to the ground, and the source of M1 is connected with the source of M11 is connected to the ground potential, and connected with the source of M4 is connected to the source of M11.

2. The gate voltage bootstrapped switch circuit of claim 1, wherein the transistors M1, M4, M5, and M9 are N-channel insulated gate bipolar transistors, and the transistors M2, M3, M6, M8, M11, and M12 are P-channel insulated gate bipolar transistors.

3. A gate-voltage bootstrapped switch circuit as recited in claim 1 or 2, wherein said gate-voltage bootstrapped switch circuit further comprises a transistor M7, a gate of M7 is connected to said clock signal CLK, a source of M7 is connected to ground potential, and a drain of M7 is connected to a drain of M1.

4. The gate voltage bootstrapped switch circuit of claim 3, wherein the transistor M7 is a P-channel insulated gate bipolar transistor.

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