CN215120751U - Charge injection cancellation circuit, analog switch circuit, and sampling device - Google Patents
Charge injection cancellation circuit, analog switch circuit, and sampling device Download PDFInfo
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- CN215120751U CN215120751U CN202120830055.0U CN202120830055U CN215120751U CN 215120751 U CN215120751 U CN 215120751U CN 202120830055 U CN202120830055 U CN 202120830055U CN 215120751 U CN215120751 U CN 215120751U
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Abstract
The application discloses charge injection cancelling circuit, analog switch circuit and sampling device concatenates first electric capacity through the grid at the second field effect transistor of charge injection cancelling circuit and the source electrode of second field effect transistor to concatenate the second electric capacity at the grid of second field effect transistor and the drain electrode of second field effect transistor, compensate the grid electric capacity of second field effect transistor. So as to reduce or eliminate the charge injection effect of the first field effect transistor and the second field effect transistor in the on-off switching state. When the charge injection elimination circuit is applied to an analog switch in a sampling system, the charge injection effect can be reduced or eliminated, so that the non-linear effects of acquisition gain error, direct current offset and the like of the acquisition system are reduced, and the sampling precision of the sampling system is improved. Meanwhile, the analog switch circuit benefits from wide-range voltage power supply and supports single-power supply and double-power supply, so that the analog switch circuit has smaller on-resistance, and the low on-resistance improves the linearity of data sampling of the analog switch circuit.
Description
Technical Field
The application belongs to the technical field of analog switches, and particularly relates to a charge injection elimination circuit, an analog switch circuit and a sampling device.
Background
Because the gate capacitances of the NMOS transistor and the PMOS transistor of the conventional analog switch are different, when the conventional analog switch is turned on or turned off, a small amount of charges are coupled to the analog signal path from the digital control line of the analog switch through the capacitance, so that a charge injection effect is generated, and the charge injection effect interferes with the output of the analog switch. When the analog switch with the traditional structure is applied to a sampling system, the sampling system has the problem of low sampling precision due to gain errors, direct current offset and nonlinear errors caused by the charge injection effect of the analog switch.
SUMMERY OF THE UTILITY MODEL
The application aims to provide a charge injection elimination circuit and aims to solve the problem that a traditional analog switch is applied to a sampling system and sampling precision is low.
A first aspect of an embodiment of the present application provides a charge injection cancellation circuit, including a first field effect transistor, a second field effect transistor, a first capacitor, and a second capacitor;
the grid electrode of the first field effect transistor is connected to a first control signal input end of the charge injection elimination circuit, the source electrode of the first field effect transistor, the source electrode of the second field effect transistor and the first end of the first capacitor are connected in common and connected to a first input signal input end of the charge injection elimination circuit, the drain electrode of the first field effect transistor, the drain electrode of the second field effect transistor and the first end of the second capacitor are connected in common and connected to an output signal output end of the charge injection elimination circuit, and the grid electrode of the second field effect transistor, the second end of the first capacitor and the second end of the second capacitor are connected in common and connected to a second control signal input end of the charge injection elimination circuit.
In one embodiment, the charge injection cancellation circuit comprises a control circuit and the charge injection cancellation circuit as in the first aspect;
the control circuit is connected with the charge injection elimination circuit and is configured to generate the first control signal and the second control signal according to a second input signal.
In one embodiment, the control circuit includes:
an inverting module configured to generate a first level signal and a second level signal from the second input signal; wherein the first level signal and the second level signal are in opposite phases;
a shift module, connected to the inverting module, configured to pull up a voltage maximum of the first level signal and the second level signal and/or pull down a voltage minimum of the first level signal and the second level signal to generate the first control signal and the second control signal; wherein the first control signal and the second control signal are in opposite phases.
In one embodiment, the inverting module includes:
a first inverting component configured to invert the second input signal and output the first level signal; and
a second inverting component coupled to the first inverting component and configured to invert the first level signal and generate the second level signal.
In one embodiment, the shift module includes:
a first shift component respectively connected with the phase inversion module and the positive voltage power supply and configured to pull up the voltage maximum value of the first level signal and the second level signal to the positive power supply voltage to generate a third level signal and a fourth level signal; wherein the positive voltage power supply outputs the positive power supply voltage, and the third level signal and the fourth level signal have opposite phases;
a second shift component, connected to the first shift component and a negative voltage power supply respectively, configured to pull down a voltage minimum of the third level signal and the fourth level signal to a negative power supply voltage to generate the second control signal; and
a third inverting component coupled to the second shifting component and configured to invert the second control signal to generate the first control signal.
In one embodiment, the first inverting assembly comprises a third field effect transistor and a fourth field effect transistor;
the grid electrode of the third field effect tube and the grid electrode of the fourth field effect tube are connected and connected to the second input signal input end of the first inverting assembly, the source electrode of the third field effect tube and the substrate of the third field effect tube are connected and connected to a logic power supply, the source electrode of the fourth field effect tube is connected with a power ground, the substrate of the fourth field effect tube is connected with a negative voltage power supply, and the drain electrode of the third field effect tube and the drain electrode of the fourth field effect tube are connected and connected to the first level signal output end of the first inverting assembly;
the second inverting assembly comprises a fifth field effect transistor and a sixth field effect transistor;
the grid of the fifth field effect tube is connected with the grid of the sixth field effect tube and is connected to the first level signal input end of the second inverting component, the source electrode of the fifth field effect tube is connected with the substrate of the fifth field effect tube and is connected to the logic power supply, the source electrode of the sixth field effect tube is connected with the power ground, the substrate of the sixth field effect tube is connected with the negative voltage power supply, and the drain electrode of the fifth field effect tube is connected with the drain electrode of the sixth field effect tube and is connected to the second level signal output end of the second inverting component.
In one embodiment, the first shift assembly includes a seventh fet, an eighth fet, a ninth fet, and a tenth fet;
a gate of the eighth field effect transistor is connected to the first level signal input terminal of the first shift element, a gate of the tenth field effect transistor is connected to the second level signal input terminal of the first shift element, a drain of the seventh field effect transistor, a drain of the eighth field effect transistor, and a gate of a ninth field effect transistor are commonly connected and connected to the third level signal output terminal of the first shift element, a gate of the seventh field effect transistor, a drain of the ninth field effect transistor, and a drain of the tenth field effect transistor are commonly connected and connected to the fourth level signal output terminal of the first shift element, a source of the seventh field effect transistor, a substrate of the seventh field effect transistor, a source of the ninth field effect transistor, and a substrate of the ninth field effect transistor are commonly connected and connected to the positive voltage power supply, and a source of the eighth field effect transistor and a source of the tenth field effect transistor are both connected to a power ground, the substrate of the eighth field effect transistor and the substrate of the tenth field effect transistor are connected in common and connected to the negative voltage power supply.
In one embodiment, the second displacement assembly comprises an eleventh fet, a twelfth fet, a thirteenth fet, and a fourteenth fet;
a gate of the eleventh fet is connected to the third level signal input terminal of the second shift element, a gate of the thirteenth fet is connected to the fourth level signal input terminal of the second shift element, a gate of the twelfth fet, a drain of the thirteenth fet, and a drain of the fourteenth fet are connected in common and to the second control signal output terminal of the second shift element, a drain of the eleventh fet, a drain of the twelfth fet, and a gate of the fourteenth fet are connected in common, a source of the eleventh fet, a substrate of the eleventh fet, a source of the thirteenth fet, and a substrate of the thirteenth fet are connected in common and to the positive voltage power supply, a source of the twelfth fet, a substrate of the twelfth fet, a gate of the thirteenth fet, And the source electrode of the fourteenth field effect transistor and the substrate of the fourteenth field effect transistor are connected in common and connected to the negative voltage power supply.
In one embodiment, the third inverting assembly includes a fifteenth fet and a sixteenth fet;
the grid electrode of the fifteenth field effect transistor is connected with the grid electrode of the sixteenth field effect transistor and is connected to the second control signal input end of the third inverting component, the source electrode of the fifteenth field effect transistor is connected with the substrate of the fifteenth field effect transistor and is connected to the positive voltage power supply, the source electrode of the sixteenth field effect transistor is connected with the substrate of the sixteenth field effect transistor and is connected to the negative voltage power supply, and the drain electrode of the fifteenth field effect transistor is connected with the drain electrode of the sixteenth field effect transistor and is connected to the first control signal output end of the third inverting component.
A third aspect of embodiments of the present application provides a sampling device comprising an analog switching circuit as defined in any one of the second aspects.
Compared with the prior art, the embodiment of the utility model beneficial effect who exists is: the grid electrode of the second field effect tube of the charge injection elimination circuit is connected with the source electrode of the second field effect tube in series with a first capacitor, and the grid electrode of the second field effect tube is connected with the drain electrode of the second field effect tube in series with a second capacitor, so that the grid electrode capacitor of the second field effect tube is compensated. So that the difference value between the grid capacitance of the second field effect transistor and the grid capacitance of the first field effect transistor after compensation is reduced to 0, and the charge injection effect of the first field effect transistor and the second field effect transistor in the on-off switching state is reduced or eliminated. When the charge injection elimination circuit is applied to an analog switch in a sampling system, the charge injection effect can be reduced or eliminated, so that the non-linear effects of acquisition gain error, direct current offset and the like of the acquisition system are reduced, and the sampling precision of the sampling system is improved.
Drawings
Fig. 1 is an exemplary circuit schematic diagram of a charge injection cancellation circuit provided in an embodiment of the present application;
fig. 2 is a first exemplary functional block diagram of an analog switch circuit provided in an embodiment of the present application;
fig. 3 is a second exemplary functional block diagram of an analog switch circuit provided in an embodiment of the present application;
fig. 4 is a third exemplary functional block diagram of an analog switch circuit provided in an embodiment of the present application;
fig. 5 is an exemplary circuit schematic diagram of an analog switch circuit provided in an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Referring to fig. 1, an embodiment of the present application provides a charge injection cancellation circuit, which includes a first fet M1, a second fet M2, a first capacitor C1, and a second capacitor C2.
The gate of the first fet M1 is connected to the first control signal input CN1 of the charge injection cancellation circuit, the source of the first fet M1, the source of the second fet M2 and the first end of the first capacitor C1 are connected IN common and to the first input signal input IN of the charge injection cancellation circuit, the drain of the first fet M1, the drain of the second fet M2 and the first end of the second capacitor C2 are connected IN common and to the output signal output OUT of the charge injection cancellation circuit, and the gate of the second fet M2, the second end of the first capacitor C1 and the second end of the second capacitor C2 are connected IN common and to the second control signal input CN2 of the charge injection cancellation circuit.
The gate capacitance of the first field effect transistor M1 is greater than that of the second field effect transistor M2.
In this embodiment, when the first control signal and the second control signal generate level shift, the on/off states of the first fet M1 and the second fet M2 change accordingly, for example, when the first control signal is shifted from high level to low level and the second control signal is shifted from low level to high level, both the first fet M1 and the second fet M2 are turned off to on state; when the first control signal is converted from low level to high level and the second control signal is converted from high level to low level, both the first fet M1 and the second fet M2 are turned from on state to off state. The gate capacitance of the first fet M1 is greater than the gate capacitance of the second fet M2, so that the on-resistance of the first fet M1 and the on-resistance of the second fet M2 are close to each other, so that the on-time of the first input signal at the first fet M1 and the second fet M2 are close to each other. The gate capacitance of the second fet M2 is compensated by connecting the gate of the second fet M2 with the source of the second fet M2 in series with the first capacitor C1, and connecting the gate of the second fet M2 with the drain of the second fet M2 in series with the second capacitor C2. The difference between the gate capacitance of the second fet M2 and the gate capacitance of the first fet M1 after compensation is reduced to 0 or less, so as to reduce or eliminate the charge injection effect occurring in the switching on/off state of the first fet M1 and the second fet M2. When the charge injection elimination circuit is applied to an analog switch in a sampling system, the charge injection effect can be reduced or eliminated, so that the non-linear effects of acquisition gain error, direct current offset and the like of the acquisition system are reduced, and the sampling precision of the sampling system is improved.
In one embodiment, the first fet M1 is a PMOS transistor, and the second fet M2 is an NMOS transistor. The transistor size of the PMOS transistor corresponding to the first fet M1 is twice as large as the transistor size of the NMOS transistor corresponding to the second fet M2, and the transistor size refers to the area of the transistor.
Referring to fig. 2, an analog switch circuit according to an embodiment of the present invention includes a control circuit 100 and a charge injection cancellation circuit 200 according to any of the embodiments. Since the analog switch circuit of the present embodiment includes the charge injection cancellation circuit 200 of any of the embodiments, the analog switch circuit of the present embodiment at least includes the corresponding advantageous effects of the charge injection cancellation circuit 200 of any of the embodiments.
The control circuit 100 is connected to the charge injection cancellation circuit 200, and configured to generate a first control signal and a second control signal according to a second input signal.
Wherein the first control signal and the second control signal have opposite phases. The opposite phase means that the voltage of one signal reaches a minimum value when the voltage of the other signal reaches a maximum value. The phase identity means that the voltages of the two signals reach a maximum value at the same time or reach a minimum value at the same time.
In this embodiment, the control circuit 100 generates the first control signal and the second control signal suitable for controlling the charge injection cancellation circuit 200 according to the second input signal, so that the control circuit 100 can control the on/off of the charge injection cancellation circuit 200 according to the second input signal, thereby controlling whether the charge injection cancellation circuit 200 outputs the first input signal as the output signal.
The second input signal is an externally input signal, and the second input signal is a digital signal.
Referring to fig. 3, in an embodiment, the control circuit 100 includes an inverting module 110 and a shifting module 120.
An inverting module 110 configured to generate a first level signal and a second level signal according to a second input signal; wherein the first level signal and the second level signal are opposite in phase.
A shift module 120 connected to the inverting module 110 and configured to pull up a maximum voltage value of the first level signal and the second level signal and/or pull down a minimum voltage value of the first level signal and the second level signal to generate a first control signal and a second control signal; wherein the first control signal and the second control signal are in opposite phase.
In this embodiment, the inverting module 110 generates a first level signal and a second level signal with opposite phases according to the second input signal, and outputs the first level signal and the second level signal to the shifting module 120. The shift module 120 pulls up the voltage maximum values of the first and second level signals to generate the first and second control signals, or pulls down the voltage minimum values of the first and second level signals to generate the first and second control signals, or pulls up the voltage maximum values of the first and second level signals and pulls down the voltage minimum values of the first and second level signals to generate the first and second control signals. Therefore, the voltage ranges of the first control signal and the second control signal generated by the shift module 120 are increased, the increase of the voltage range of the first control signal means the increase of the difference between the maximum voltage value and the minimum voltage value of the first control signal, and the increase of the voltage range of the second control signal means the increase of the difference between the maximum voltage value and the minimum voltage value of the second control signal. Therefore, the voltage range acting on the first fet M1 and the second fet M2 is increased, so that the resistance of the first fet M1 and the second fet M2 is decreased when they are turned on, and the linearity of the first input signal converted into the output signal is higher. Therefore, when the analog switch circuit of the present embodiment is applied to a sampling system, the linearity of data sampling can be improved, thereby improving the sampling accuracy.
Referring to fig. 4, in one embodiment, the inverting module 110 includes a first inverting element 111 and a second inverting element 112.
The first inverting component 111 is configured to invert the second input signal and output a first level signal.
And a second inverting component 112 connected to the first inverting component 111 and configured to invert the first level signal and generate a second level signal.
In the embodiment, the first inverting component 111 inverts the second input signal to generate a first level signal, the second inverting component 112 inverts the first level signal to generate a second level signal, and the levels of the first level signal and the second level signal are suitable for subsequent control requirements.
Referring to fig. 4, in an embodiment, the shift module 120 includes a first shift element 121, a second shift element 122, and a third inverting element 123.
A first shift module 121 respectively connected to the inverting module 110 and the positive voltage power supply, and configured to pull up a voltage maximum of the first level signal and the second level signal to the positive power supply voltage to generate a third level signal and a fourth level signal; wherein the positive voltage power supply outputs a positive power supply voltage, and the third level signal and the fourth level signal have opposite phases.
And a second shift element 122, connected to the first shift element 121 and the negative voltage power supply, respectively, and configured to pull down a minimum voltage value of the third level signal and the fourth level signal to a negative power supply voltage to generate a second control signal.
And a third inverting component 123, connected to the second shifting component 122, configured to invert the second control signal to generate the first control signal.
In the present embodiment, the first shift component 121 pulls up the maximum voltage values of the first and second level signals to the positive power voltage to generate the third and fourth level signals with opposite phases. The second shift component 122 pulls down the voltage minimum of the third level signal and the fourth level signal to the negative power supply voltage to generate the second control signal. The third inverting component 123 inverts the second control signal to generate the first control signal. The voltage maximum value of the second control signal and the voltage maximum value of the first control signal are both pulled high, and the voltage minimum value of the second control signal and the voltage minimum value of the first control signal are both pulled low, so that the voltage ranges of the second control signal and the first control signal are widened, and the on-resistance of the analog switch circuit is reduced.
Referring to fig. 5, in one embodiment, the first inverting element 111 includes a third fet M3 and a fourth fet M4.
The gate of the third fet M3 and the gate of the fourth fet M4 are connected to the second input signal input terminal of the first inverter module 111, the source of the third fet M3 and the substrate of the third fet M3 are connected to the logic power supply, the source of the fourth fet M4 is connected to the power ground, the substrate of the fourth fet M4 is connected to the negative voltage power supply, and the drain of the third fet M3 and the drain of the fourth fet M4 are connected to the first level signal output terminal of the first inverter module 111.
Referring to fig. 5, in one embodiment, the second inverting element 112 includes a fifth fet M5 and a sixth fet M6.
The grid of the fifth field effect transistor M5 and the grid of the sixth field effect transistor M6 are connected and connected to the first level signal input end of the second inverter component 112, the source of the fifth field effect transistor M5 and the substrate of the fifth field effect transistor M5 are connected and connected to the logic power supply, the source of the sixth field effect transistor M6 is connected with the power ground, the substrate of the sixth field effect transistor M6 is connected with the negative voltage power supply, and the drain of the fifth field effect transistor M5 and the drain of the sixth field effect transistor M6 are connected and connected to the second level signal output end of the second inverter component 112.
Referring to fig. 5, in an embodiment, the first shift element 121 includes a seventh fet M7, an eighth fet M8, a ninth fet M9, and a tenth fet M10.
A gate of the eighth fet M8 is connected to the first level signal input terminal of the first shifter element 121, a gate of the tenth fet M10 is connected to the second level signal input terminal of the first shifter element 121, a drain of the seventh fet M7, a drain of the eighth fet M8, and a gate of the ninth fet M9 are commonly connected and connected to the third level signal output terminal of the first shifter element 121, a gate of the seventh fet M7, a drain of the ninth fet M9, and a drain of the tenth fet M10 are commonly connected and connected to the fourth level signal output terminal of the first shifter element 121, a source of the seventh fet M7, a substrate of the seventh fet M7, a source of the ninth fet M9, and a substrate of the ninth fet M9 are commonly connected and connected to a positive voltage source, a source of the eighth fet M8 and a source of the tenth fet M10 are all connected to a power ground, the substrate of the eighth fet M8 and the substrate of the tenth fet M10 are connected in common and to a negative voltage source.
Referring to fig. 5, in an embodiment, the second shift element 122 includes an eleventh fet M11, a twelfth fet M12, a thirteenth fet M13, and a fourteenth fet M14.
A gate of the eleventh fet M11 is connected to the third level signal input terminal of the second shifter element 122, a gate of the thirteenth fet M13 is connected to the fourth level signal input terminal of the second shifter element 122, a gate of the twelfth fet M12, a drain of the thirteenth fet M13, and a drain of the fourteenth fet M14 are commonly connected and connected to the second control signal output terminal of the second shifter element 122, a drain of the eleventh fet M11, a drain of the twelfth fet M12, and a gate of the fourteenth fet M14 are commonly connected, a source of the eleventh fet M11, a substrate of the eleventh fet M11, a source of the thirteenth fet M13, and a substrate of the thirteenth fet M13 are commonly connected and connected to the positive voltage source, the source of the twelfth FET M12, the substrate of the twelfth FET M12, the source of the fourteenth FET M14, and the substrate of the fourteenth FET M14 are connected in common and to a negative voltage source.
Referring to fig. 5, in an embodiment, the third inverting element 123 includes a fifteenth fet M15 and a sixteenth fet M16.
The gate of the fifteenth fet M15 and the gate of the sixteenth fet M16 are connected to the second control signal input terminal of the third inverting component 123, the source of the fifteenth fet M15 and the substrate of the fifteenth fet M15 are connected to the positive voltage power supply, the source of the sixteenth fet M16 and the substrate of the sixteenth fet M16 are connected to the negative voltage power supply, and the drain of the fifteenth fet M15 and the drain of the sixteenth fet M16 are connected to the first control signal output terminal of the third inverting component 123.
The analog switching circuit shown in fig. 5 will be described with reference to the operation principle:
when the second input signal is at a logic low level, the second input signal is respectively applied to the gate of the third fet M3 and the gate of the fourth fet M4, the third fet M3 is turned on, the fourth fet M4 is turned off, and the third fet M3 outputs a high-level first level signal and is applied to the gate of the fifth fet M5 and the gate of the sixth fet M6. The fifth fet M5 is turned off and the sixth fet M6 is turned on, and the sixth fet M6 outputs the second level signal of low level.
The high first level signal acts on the gate of the eighth fet M8, turning on the eighth fet M8. The low second level signal is applied to the gate of the tenth fet M10, and the tenth fet M10 is turned off. The gate of the ninth fet M9 and the gate of the eleventh fet M11 are both connected to the power ground through the eighth fet M8, the power ground acts on the gate of the eleventh fet M11 as a low-level third level signal, and the ninth fet M9 and the eleventh fet M11 are both turned on. The positive power voltage outputted by the positive voltage power supply is respectively applied to the gate of the seventh fet M7 and the gate of the thirteenth fet M13 through the ninth fet M9, and both the seventh fet M7 and the thirteenth fet M13 are turned off. The positive power supply voltage is applied to the gate of the thirteenth fet M13 as a high-level fourth level signal through the ninth fet M9, and the maximum voltage value of the high level of the fourth level signal is the same as the positive power supply voltage. The positive power voltage is applied to the gate of the fourteenth fet M14 through the eleventh fet M11, and the fourteenth fet M14 is turned on. The negative power voltage is output to the gate of the second fet M2, the gate of the fifteenth fet M15, and the gate of the sixteenth fet M16, respectively, as the low-level second control signal through the fourteenth fet M14. The second fet M2 is turned off, the fifteenth fet M15 is turned on, the sixteenth fet M16 is turned off, and the positive power voltage is output to the gate of the first fet M1 as a high-level first control signal through the fifteenth fet M15, so that the first fet M1 is turned off. The first fet M1 and the second fet M2 are both turned off, so that the analog switch circuit is in an off state, and the first fet M1 and the second fet M2 stop outputting the output signal according to the first input signal.
When the second input signal is at a logic high level, the second input signal is respectively applied to the gate of the third fet M3 and the gate of the fourth fet M4, the third fet M3 is turned off, the fourth fet M4 is turned on, and the fourth fet M4 outputs a low-level first level signal and is applied to the gate of the fifth fet M5 and the gate of the sixth fet M6. The fifth fet M5 is turned on and the sixth fet M6 is turned off, and the fifth fet M5 outputs the second level signal of high level.
The first level signal of the low level is applied to the gate of the eighth fet M8, and the eighth fet M8 is turned off. The high second level signal is applied to the gate of the tenth fet M10, and the tenth fet M10 is turned on. The grid electrode of the seventh field effect transistor M7 and the grid electrode of the thirteenth field effect transistor M13 are both connected with the power ground through the tenth field effect transistor M10, and the seventh field effect transistor M7 is conducted; the power ground is applied to the gate of the thirteenth fet M13 as a low-level third level signal, and the thirteenth fet M13 is turned on. The positive power voltage outputted by the positive voltage power supply is respectively applied to the gate of the ninth fet M9 and the gate of the eleventh fet M11 through the seventh fet M7, and both the ninth fet M9 and the eleventh fet M11 are turned off. The positive power supply voltage is applied to the gate of the eleventh fet M11 as a high-level third level signal through the seventh fet M7, and the maximum voltage value of the high level of the third level signal is the same as the positive power supply voltage. The positive power voltage is applied to the gate of the twelfth fet M12 through the thirteenth fet M13, and the twelfth fet M12 is turned on. And the positive power voltage is output to the gate of the second fet M2, the gate of the fifteenth fet M15 and the gate of the sixteenth fet M16, respectively, as a high-level second control signal through the thirteenth fet M13. The second fet M2 is turned on, the fifteenth fet M15 is turned off, the sixteenth fet M16 is turned on, and the negative power voltage is output to the gate of the first fet M1 as a low-level first control signal through the sixteenth fet M16, so that the first fet M1 is turned on. The first fet M1 and the second fet M2 are both turned on, so that the analog switch circuit is in a turned-on state, and the first input signal is output as an output signal through the first fet M1 and the second fet M2.
The present embodiment also provides a sampling apparatus, including the analog switch circuit according to any one of the above embodiments. Since the sampling device of the present embodiment includes the analog switch circuit of any of the above embodiments, the sampling device of the present embodiment at least includes the analog switch circuit of any of the above embodiments.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A charge injection elimination circuit is characterized by comprising a first field effect transistor, a second field effect transistor, a first capacitor and a second capacitor;
the grid electrode of the first field effect transistor is connected to a first control signal input end of the charge injection elimination circuit, the source electrode of the first field effect transistor, the source electrode of the second field effect transistor and the first end of the first capacitor are connected in common and connected to a first input signal input end of the charge injection elimination circuit, the drain electrode of the first field effect transistor, the drain electrode of the second field effect transistor and the first end of the second capacitor are connected in common and connected to an output signal output end of the charge injection elimination circuit, and the grid electrode of the second field effect transistor, the second end of the first capacitor and the second end of the second capacitor are connected in common and connected to a second control signal input end of the charge injection elimination circuit;
and the grid capacitance of the first field effect transistor is larger than that of the second field effect transistor.
2. An analog switch circuit comprising a control circuit and the charge injection cancellation circuit of claim 1;
the control circuit is connected with the charge injection elimination circuit and is configured to generate the first control signal and the second control signal according to a second input signal.
3. The analog switch circuit of claim 2, wherein the control circuit comprises:
an inverting module configured to generate a first level signal and a second level signal from the second input signal; wherein the first level signal and the second level signal are in opposite phases;
a shift module, connected to the inverting module, configured to pull up a voltage maximum of the first level signal and the second level signal and/or pull down a voltage minimum of the first level signal and the second level signal to generate the first control signal and the second control signal; wherein the first control signal and the second control signal are in opposite phases.
4. The analog switch circuit of claim 3, wherein the inverting module comprises:
a first inverting component configured to invert the second input signal and output the first level signal; and
a second inverting component coupled to the first inverting component and configured to invert the first level signal and generate the second level signal.
5. The analog switch circuit of claim 3, wherein the shift module comprises:
a first shift component respectively connected with the phase inversion module and the positive voltage power supply and configured to pull up the voltage maximum value of the first level signal and the second level signal to the positive power supply voltage to generate a third level signal and a fourth level signal; wherein the positive voltage power supply outputs the positive power supply voltage, and the third level signal and the fourth level signal have opposite phases;
a second shift component, connected to the first shift component and a negative voltage power supply respectively, configured to pull down a voltage minimum of the third level signal and the fourth level signal to a negative power supply voltage to generate the second control signal; and
a third inverting component coupled to the second shifting component and configured to invert the second control signal to generate the first control signal.
6. The analog switch circuit of claim 4, wherein the first inverting component includes a third field effect transistor and a fourth field effect transistor;
the grid electrode of the third field effect tube and the grid electrode of the fourth field effect tube are connected and connected to the second input signal input end of the first inverting assembly, the source electrode of the third field effect tube and the substrate of the third field effect tube are connected and connected to a logic power supply, the source electrode of the fourth field effect tube is connected with a power ground, the substrate of the fourth field effect tube is connected with a negative voltage power supply, and the drain electrode of the third field effect tube and the drain electrode of the fourth field effect tube are connected and connected to the first level signal output end of the first inverting assembly;
the second inverting assembly comprises a fifth field effect transistor and a sixth field effect transistor;
the grid of the fifth field effect tube is connected with the grid of the sixth field effect tube and is connected to the first level signal input end of the second inverting component, the source electrode of the fifth field effect tube is connected with the substrate of the fifth field effect tube and is connected to the logic power supply, the source electrode of the sixth field effect tube is connected with the power ground, the substrate of the sixth field effect tube is connected with the negative voltage power supply, and the drain electrode of the fifth field effect tube is connected with the drain electrode of the sixth field effect tube and is connected to the second level signal output end of the second inverting component.
7. The analog switch circuit of claim 5, wherein the first shifting component comprises a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, and a tenth field effect transistor;
a gate of the eighth field effect transistor is connected to the first level signal input terminal of the first shift element, a gate of the tenth field effect transistor is connected to the second level signal input terminal of the first shift element, a drain of the seventh field effect transistor, a drain of the eighth field effect transistor, and a gate of a ninth field effect transistor are commonly connected and connected to the third level signal output terminal of the first shift element, a gate of the seventh field effect transistor, a drain of the ninth field effect transistor, and a drain of the tenth field effect transistor are commonly connected and connected to the fourth level signal output terminal of the first shift element, a source of the seventh field effect transistor, a substrate of the seventh field effect transistor, a source of the ninth field effect transistor, and a substrate of the ninth field effect transistor are commonly connected and connected to the positive voltage power supply, and a source of the eighth field effect transistor and a source of the tenth field effect transistor are both connected to a power ground, the substrate of the eighth field effect transistor and the substrate of the tenth field effect transistor are connected in common and connected to the negative voltage power supply.
8. The analog switch circuit of claim 5, wherein the second shifting component comprises an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, and a fourteenth field effect transistor;
a gate of the eleventh fet is connected to the third level signal input terminal of the second shift element, a gate of the thirteenth fet is connected to the fourth level signal input terminal of the second shift element, a gate of the twelfth fet, a drain of the thirteenth fet, and a drain of the fourteenth fet are connected in common and to the second control signal output terminal of the second shift element, a drain of the eleventh fet, a drain of the twelfth fet, and a gate of the fourteenth fet are connected in common, a source of the eleventh fet, a substrate of the eleventh fet, a source of the thirteenth fet, and a substrate of the thirteenth fet are connected in common and to the positive voltage power supply, a source of the twelfth fet, a substrate of the twelfth fet, a gate of the thirteenth fet, And the source electrode of the fourteenth field effect transistor and the substrate of the fourteenth field effect transistor are connected in common and connected to the negative voltage power supply.
9. The analog switch circuit of claim 5, wherein the third inverting component includes a fifteenth fet and a sixteenth fet;
the grid electrode of the fifteenth field effect transistor is connected with the grid electrode of the sixteenth field effect transistor and is connected to the second control signal input end of the third inverting component, the source electrode of the fifteenth field effect transistor is connected with the substrate of the fifteenth field effect transistor and is connected to the positive voltage power supply, the source electrode of the sixteenth field effect transistor is connected with the substrate of the sixteenth field effect transistor and is connected to the negative voltage power supply, and the drain electrode of the fifteenth field effect transistor is connected with the drain electrode of the sixteenth field effect transistor and is connected to the first control signal output end of the third inverting component.
10. A sampling device comprising an analog switching circuit according to any one of claims 2 to 9.
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| CN113225055A (en) * | 2021-04-21 | 2021-08-06 | 深圳市国微电子有限公司 | Charge injection cancellation circuit, analog switch circuit, and sampling device |
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| CN113225055A (en) * | 2021-04-21 | 2021-08-06 | 深圳市国微电子有限公司 | Charge injection cancellation circuit, analog switch circuit, and sampling device |
| CN113225055B (en) * | 2021-04-21 | 2024-02-13 | 深圳市国微电子有限公司 | Charge injection cancellation circuit, analog switch circuit, and sampling device |
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