CN1901372A - High linearity CMOS analogue switch suitable for low voltage - Google Patents

Abstract

This invention relates to a CMOS analog sample switch suitable for low voltages and high linearity composed of three divider resistors, an operational amplifier, a duplicated sample switch, a sample switch, a false sample switch and two boosted circuits, in which, the operational amplifier and the duplicated sample switch form a negative feed-back circuit to duplicate a threshold voltage same to the sample switch for the duplicated sample switch, then the grating voltage of the duplicated sample switch is taken as the control signal of the sample switch to eliminate the change of the switch conduction resistor along with the input signal and the threshold voltage so as to increase the linearity of the sample switch.

Description

Be applicable to the high linearity CMOS analogue switch of low-voltage

Technical field

The invention belongs to technical field of integrated circuits, be specifically related to a kind of high linearity CMOS analogue switch that is applicable to low-voltage.

Background technology

In current composite signal integrated circuits design field, switched-capacitor circuit is just being played the part of extremely important role.Past tends to use resistance in the circuit, but is difficult to the accurately resistance of control in CMOS technology, so the precision of circuit can be subjected to severely restricts.By contrast, realize that accurate electric capacity is then more or less freely, so switched-capacitor circuit can obtain higher precision.In addition, switched-capacitor circuit has utilized the charge storage principle, so have bigger dynamic range and better temperature characterisitic.Rely on the plurality of advantages of himself, switched-capacitor circuit has been widely used in the systems such as base band signal process of voice modulation, transceiver.With regard to physical circuit, be mainly mould/number, D/A and various filter.

But along with development of integrated circuits, the problem of simple switched-capacitor circuit embodies gradually.Fig. 1 has shown a simple switched-capacitor circuit, when clock Ck is high level (supply voltage V _Dd) time, the conducting resistance expression formula that can derive switch 1 is as follows:

$R_{\mathrm{ON}}=\frac{1}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}\frac{W}{L}(V_{\mathrm{dd}}-V_{\mathrm{in}}-V_{\mathrm{THN}})}$

Wherein, R _ONBe switch conduction resistance, μ _nBe electron mobility, C _OxBe the gate oxide electric capacity of unit are, W/L is the breadth length ratio of metal-oxide-semiconductor, V _InBe input signal, V _THNBe the metal-oxide-semiconductor threshold voltage.From expression formula two main problems as can be seen: at first, the maximum level of input signal must be lower than threshold voltage (V of metal-oxide-semiconductor grid voltage _THN) just can make switch conduction, in today that supply voltage constantly reduces, this can badly influence the amplitude of oscillation of input signal; Secondly, the conducting resistance of switch can be along with metal-oxide-semiconductor gate source voltage (V _Dd-V _In) and threshold voltage V _THNAnd change, this directly has influence on the linearity of entire circuit, makes it can not satisfy the requirement of current high-precision circuit.How to solve this two problems, become an important research direction of switched-capacitor circuit.

A comparison effective method of head it off is to utilize technology shown in Figure 2, and this technology proposes already abroad, concrete visible H.Pan, M.Segami, M.Choi, J.Cao, and A.Abidi, " A 3.3-V 12-b 50-MS/sA/D Converter in 0.6-um CMOS with over 80-dB SFDR; " IEEE J.Solid-State Circuits, vol.35, NO.12, pp.1769-1780, Dec.2001.As shown in Figure 2, this circuit is made up of reference resistance 3～4, constant-current source 5, operational amplifier 6, replica samples switch 7, booster circuit 8～13, sampling switch 14.Wherein the resistance of resistance 4 is much larger than the resistance of resistance 3, and therefore the partial pressure value at node 15 gained is approximately equal to input signal V _InCrossing current source 5 is biased in the saturation region with replica samples switch 7, because operational amplifier 6 and replica samples switch 7 form negative feedback, so node 16 is identical with the voltage of node 15, all equals input signal V _InBecause the current constant of replica samples switch 7, according to current formula its also substantially constant of gate source voltage as can be known, so the voltage of node 17 (is V than node 16 all the time _In) a high fixing value.At last the voltage of node 17 is promoted behind the fixed voltage control voltage as sampling switch 14 grid ends through a booster circuit 8～13, just can be so that the gate source voltage basic fixed of 14 pipes, thus eliminated non-linear that its variation introduced.Simultaneously, because the source end of 7 pipes and 14 pipes all equals V _In, so they have identical source one and serve as a contrast voltage partially, by following formula as can be known their threshold voltage equate, thereby eliminated non-linear that threshold voltage variation introduces.Wherein booster circuit 8～13 has specifically adopted structure shown in Figure 3, the node 17 in the Vin connection layout 2 among Fig. 3, the node 18 in the Vg connection layout 2 among Fig. 3.

$V_{\mathrm{THN}}=V_{\mathrm{TH}0}+{\mathrm{\γ}}_{\mathrm{sub}}[\sqrt{2\left|{\mathrm{\Φ}}_f\right|+V_{\mathrm{SB}}}-\sqrt{2\left|{\mathrm{\Φ}}_f\right|}]$

Here, V _THOBe intrinsic threshold voltage, γ _SubBe body-effect coefficient, Φ _fBe surface potential, V _SBFor the source bulk potential poor.Yet as can be seen from Figure 2, the voltage of node 17 (is V than the voltage of node 16 all the time _In) a high threshold voltage, because the output voltage swing of operational amplifier 6 is limited, 16 voltage is seriously limited, it is impossible to make that use long arc input signal becomes.Along with current supply voltage constantly reduces, this problem is serious day by day.Therefore, how when guaranteeing the switched linear degree, to increase the input signal amplitude of oscillation of switch, become a problem demanding prompt solution.

Summary of the invention

The objective of the invention is to propose a kind of high linearity CMOS analogue switch that is applicable to low-voltage,, satisfied the strict demand of current low-voltage, high-precision circuit analog switch to overcome the existing less deficiency of the analog switch amplitude of oscillation.

The novel analog switch that the present invention proposes is the high linearity CMOS analogue switch that is applicable to low-voltage, is made up of 3 divider resistances, 1 operational amplifier, 1 replica samples switch, 1 sampling switch, 1 pseudo-sampling switch, 2 booster circuits.Form negative-feedback circuit by operational amplifier and replica samples switch, thereby copy the threshold voltage identical for the replica samples switch with sampling switch.Again with the gate voltage of replica samples switch control signal, eliminating the sampling switch conducting resistance, thereby improved the linearity of sampling switch greatly with input signal and variations in threshold voltage as sampling switch.Utilize 2 booster circuits simultaneously, eliminated of the restriction of amplifier output voltage swing, realized the operate as normal under the low-voltage circuit function.

Particular circuit configurations of the present invention is seen shown in Figure 4.Form by divider resistance 36～38, replica samples switch 39, sampling switch 40, pseudo-sampling switch 41, booster circuit one, booster circuit two, operational amplifier 56, to the dividing potential drop the ground, dividing potential drop output is connected to the positive input terminal of operational amplifier 56 from the input signal end for divider resistance 37 and 38 formation.The drain terminal of replica samples pipe 39 is connected to the input signal end, and the grid end is connected to the common output end node 61 of booster circuit one, booster circuit two, and the source end is connected to the negative input end of operational amplifier 56.One end of divider resistance 36 is connected to the source end of replica samples switch 39, and the other end is connected to ground.

Booster circuit one by the switch 43,45 and 47 that is subjected to clock Φ 1 control, connected to form through circuit by the switch 42,46,48 of reverse clock Φ 2 controls.Booster circuit two is connected and composed by the switch 50,52 and 54 of reverse clock Φ 2 controls through circuit by the switch 49,53 and 55 that is subjected to clock Φ 1 control, booster circuit one and booster circuit two are conventional booster circuit, and particular circuit configurations is seen shown in Figure 5.In the booster circuit one, Vin is connected to the output of operational amplifier 56 among Fig. 4, and Vg is connected to the grid end of sampling switch 40 among Fig. 4, and Vout is connected to the grid end of replica samples switch 39 among Fig. 4.In the booster circuit two, Vin is connected to the output of operational amplifier 56 among Fig. 4, and Vg is connected to the grid end of pseudo-sampling switch 41 among Fig. 4, and Vout is connected to the grid end of replica samples switch 39 among Fig. 4.The drain terminal of sampling switch 40 is connected to the input signal end, and the grid end is connected to the output node 58 of booster circuit one, and the source end is connected to the sampling output.The drain terminal of pseudo-sampling switch 41, source end short circuit are connected to the input signal end after together, and the grid end is connected to the output node 62 of booster circuit two.

Among the present invention, resistance 36 and 38 has identical resistance, and greater than the resistance of resistance 37.Booster circuit one utilizes two phase clock Φ 1, Φ 2 controls.Wherein booster circuit two utilizes opposite two phase clock Φ 2, Ф 1 control.Wherein replica samples switch 39, pseudo-sampling switch 41 should have identical size with sampling switch 40.To specify its operation principle below.

The effect of booster circuit one and booster circuit two only is the voltage V of output lifting with amplifier 56 _Dd, do not introduce other influence, so operational amplifier 56 and replica samples switch 39 (adopting the NMOS pipe) form negative feedback, so the level of node 59 and node 60 equates.Because resistance 37 is far smaller than resistance 36 and 38, so equal input signal V substantially in the dividing potential drop of node 60 _In, the level of node 59 also equals input signal V substantially so _InTherefore the drain source voltage of replica samples switch 39 will be very little, and pipe work is at dark linear zone, and this operating state with sampling switch 40 (adopting the NMOS pipe) is consistent.By regulating the resistance of resistance 36,37,38, can allow the drain source voltage of 39 pipes and 40 pipes equal substantially.Because their drain terminal is all followed V _In, so their source terminal potential is equal, promptly has identical source-body and serves as a contrast voltage V partially _SB, so have equal threshold voltage.

Because the level of node 59 and node 60 equals V _In, and resistance 36 and 38 equates, so the conducting resistance of replica samples switch 39 equals resistance 37.Can obtain the current potential of node 61 so by following derivation.So, just can allow sampling switch 40 with the voltage of node 61 control signal as sampling switch 40

$R_{\mathrm{ON},\mathrm{<figure-callout\; id="39"\; label="M"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">M</figure-callout>}39}=\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}(V_{61}-V_{\mathrm{in}}-V_{\mathrm{THN}})}={\mathrm{<figure-callout\; id="37"\; label="R"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">R</figure-callout>}}_{37}\&RightArrow;{\mathrm{<figure-callout\; id="61"\; label="V"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\text{61}}=V_{\mathrm{in}}+V_{\mathrm{THN}}+\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{\mathrm{<figure-callout\; id="37"\; label="W\; L\; R"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">W</figure-callout>}}{L}{R}_{}{}_{37}}$

Conducting resistance and V _InAnd V _THNAll have nothing to do (formula as follows), thereby realized the very high linearity.Because the existence of booster circuit one and booster circuit two makes the output voltage swing of operational amplifier 56 improve greatly, thereby can realize the very high input signal amplitude of oscillation, is suitable for the work under the low voltage mode.

$R_{\mathrm{ON},\mathrm{<figure-callout\; id="40"\; label="M"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">M</figure-callout>}40}=\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}(V_{\mathrm{in}}+V_{\mathrm{THN}}+\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}{R}_{37}}-V_{\mathrm{in}}-V_{\mathrm{THN}})}=\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}\left(\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}{R}_{37}}\right)}={\mathrm{<figure-callout\; id="37"\; label="R"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">R</figure-callout>}}_{37}$

Here, R _{ON, M39}, R _{ON, M40}The conducting resistance of representing metal-oxide-semiconductor 30 and 31 respectively, R ₂₀, R ₃₂The resistance of representing resistance 20,32 respectively, all the other symbol implications are the same.

Description of drawings

Fig. 1 is the sampling switch schematic diagram.

Fig. 2 is traditional high linearity switching circuit figure.

Fig. 3 is the voltage lifting circuit figure in traditional high linearity switch.

The high linearity CMOS analogue switch structure chart that is applicable to low-voltage that Fig. 4 proposes for the present invention.

Fig. 5 is employed voltage lifting circuit figure among the present invention.

Label declaration: 1,7,14,19,22,25,27,29,31,32,33,34,39,40,41,63,66,69,71,73,75,76,77,78 are the NMOS pipe, 28,30,72,74,79 are the PMOS pipe, 2,10,20,23,26,44,51,64,67,70 be electric capacity,, 3,4,36,37,38 is resistance, 5 is current source, 6,56 is operational amplifier, and 21,24,65,68 is reverser, and 8,12,43,45,47,49,53,55 is clock Φ ₁The switch of control, 9,11,13,42,46,48,50,52,54 is inversion clock Φ ₂The switch of control, 57,58,59,60,61 is node.

Embodiment

Further describe the present invention below in conjunction with accompanying drawing.

In Fig. 4, resistance 36 and 38 has identical resistance, and much larger than the resistance of resistance 37.Input signal V _InAfter resistance 37,38 dividing potential drops, produce one at node 60 and be approximately equal to V _InSignal, as the input of operational amplifier 56 anodes.Operational amplifier 56 and replica samples switch 39 are formed negative-feedback circuit, make the voltage of node 59 equal the voltage of node 60, promptly are approximately equal to input signal V _In, so replica samples switch 39 is operated in dark linear zone, with the state consistency of sampling switch 40.By regulating the resistance of resistance 36,37,38, can allow the drain source voltage of replica samples switch 39 and sampling switch 40 equal substantially.Because their drain terminal all meets V _In, then source electric potential equates, identical bulk effect is promptly arranged, thereby have identical threshold voltage V _THNBecause the level of node 43 and node 44 equals V _In, and resistance 20 and 22 equates, can get the conducting resistance R of transistor 23 _{ON, M23}Equal the resistance of resistance 37, the voltage that can derive node 61 thus is as follows.Last again the voltage of node 61 as sampling switch 40 grid ends

${\mathrm{<figure-callout\; id="61"\; label="V"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">V</figure-callout>}}_{61}=V_{\mathrm{in}}+V_{\mathrm{THN}}+\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{\mathrm{<figure-callout\; id="37"\; label="W\; L\; R"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">W</figure-callout>}}{L}{R}_{}{}_{37}}$

The control voltage of (node 58), then can calculate 40 pipes conducting resistance will with input signal and threshold voltage independent from voltage (formula as follows), therefore can reach the very high linearity.

$R_{\mathrm{ON},\mathrm{<figure-callout\; id="40"\; label="M"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">M</figure-callout>}40}=\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}(V_{\mathrm{in}}+V_{\mathrm{THN}}+\frac{1}{{\mathrm{\&mu;}}_u{C}_{\mathrm{ox}}\frac{\mathrm{<figure-callout\; id="37"\; label="W\; L\; R"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">W</figure-callout>}}{L}{R}_{}{}_{37}}+V_{\mathrm{in}}-V_{\mathrm{THN}})}=\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}\left(\frac{1}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}{R}_{37}}\right)}={\mathrm{<figure-callout\; id="37"\; label="R"\; filenames="A20061002916900091.png"\; state="\{\{state\}\}">R</figure-callout>}}_{37}$

Again the low voltage operating principle of this switch is set forth below.In this switch, two booster circuits have been used.Wherein booster circuit one is worked for 2 times at two phase clock Φ 1, Φ, and booster circuit two is in 1 time work of opposite two phase clock Φ 2, Ф.Their purpose all is the fixed value V of current potential lifting with node 57 _DdThereby, realize circuit operate as normal under low-voltage.If do not have this two voltage lifting circuits, as input signal V _InNear V _DdThe time, the voltage of node 61 also can be followed V _InNear V _Dd, the level of node 57 will exceed V so _DdAnd the output voltage swing of amplifier can not exceed V _Dd, so the work of circuit can be subjected to the restriction of amplifier output voltage swing.After adding voltage lifting circuit, even the voltage of node 61 exceeds V _Dd, also can not cause the voltage of node 57 to exceed the output voltage swing of amplifier.Therefore circuit still can operate as normal.As can see from Figure 3, as clock Φ 2 effectively the time, sampling switch 54 conductings, pseudo-sampling switch 41 ends; As clock Φ 1 effectively the time, sampling switch 40 ends, pseudo-sampling switch 41 conductings.No matter under that clock phase, amplifier all has constant load, has more guaranteed the operate as normal of circuit.In actual use, booster circuit adopts the structure of Fig. 5, and it is the circuit improvement from Fig. 3.For booster circuit one, the Vin among Fig. 5 should be received 57 nodes among Fig. 4, the Vout among Fig. 5 is received 61 nodes among Fig. 4, the Vg among Fig. 5 is received 58 nodes among Fig. 4.For booster circuit two, the Vin among Fig. 5 should be received 57 nodes among Fig. 4, the Vout among Fig. 5 is received 61 nodes among Fig. 4, the Vg among Fig. 5 is received 58 nodes among Fig. 4.

Claims (5)

1, a kind of high linearity CMOS analogue switch that is applicable to low-voltage is characterized in that being connected and composed through circuit by divider resistance (36,37,38), replica samples switch (39), sampling switch (40), pseudo-sampling switch (41), booster circuit one, booster circuit two, operational amplifier (56); Wherein, to the dividing potential drop the ground, dividing potential drop output is connected to the positive input terminal of operational amplifier (56) from the input signal end for divider resistance (37) and (38) formation; The drain terminal of replica samples pipe (39) is connected to the input signal end, and the grid end is connected to the common output end node (61) of booster circuit one and booster circuit two, and the source end is connected to the negative input end of operational amplifier (56); One end of divider resistance (36) is connected to the source end of replica samples switch (39), and the other end is connected to ground.

2, the high linearity CMOS analogue switch that is applicable to low-voltage according to claim 1, it is characterized in that the Vin of voltage lifting circuit one is connected to the output of operational amplifier (56), Vg is connected to the grid end of sampling switch (40), and Vout is connected to the grid end of replica samples switch (39).

3, the high linearity CMOS analogue switch that is applicable to low-voltage according to claim 1, it is characterized in that the Vin of voltage lifting circuit two is connected to the output of operational amplifier (56), Vg is connected to the grid end of pseudo-sampling switch (41), and Vout is connected to the grid end of replica samples switch (39).

4, the high linearity CMOS analogue switch that is applicable to low-voltage according to claim 1, the drain terminal that it is characterized in that sampling switch (40) is connected to the input signal end, the grid end is connected to the output node (58) of booster circuit one, and the source end is connected to the sampling output.

5, the high linearity CMOS analogue switch that is applicable to low-voltage according to claim 1, the drain terminal, source end short circuit that it is characterized in that pseudo-sampling switch (41) is connected to the input signal end after together, and the grid end is connected to the output node (62) of booster circuit two.

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