CN112636758B - Sampling hold circuit used in snapshot type readout circuit - Google Patents
Sampling hold circuit used in snapshot type readout circuit Download PDFInfo
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- CN112636758B CN112636758B CN202011525814.9A CN202011525814A CN112636758B CN 112636758 B CN112636758 B CN 112636758B CN 202011525814 A CN202011525814 A CN 202011525814A CN 112636758 B CN112636758 B CN 112636758B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/54—Input signal sampled and held with linear return to datum
Abstract
The invention discloses a sample hold circuit used in a snapshot type readout circuit, comprising: the low-error sampling circuit comprises a low-error sampling switch circuit, a compensation circuit, a clamping circuit and a sampling capacitor Cint; the low-error sampling switch circuit comprises a first low-error sampling switch gate1 and a second low-error sampling switch gate2 which are consistent in structure, voltage to be sampled is injected from a first low-error sampling switch gate1, the first low-error sampling switch gate1 is connected with a second low-error sampling switch gate2, and the other end of the second low-error sampling switch gate2 is connected with a sampling capacitor Cint and then grounded; the gate1 and the gate2 are synchronously switched, and the clamping circuits are connected to two ends of the gate2 in parallel, so that the voltages of two ends of the gate2 are equal; the compensation circuit is connected in parallel with two ends of the gate2 and compensates leakage current in the process of sample holding to the sampling capacitor Cint. After the leakage current compensation structure is adopted, the reduction amplitude of the sampling voltage is reduced compared with the voltage when the structure is not adopted; the clamp structure combined with the sampling switch limits the leakage current of the switch in a closed state, and further reduces the amplitude reduction of the sampling voltage.
Description
Technical Field
The invention relates to the technical field of analog integrated circuit design, in particular to a sample-and-hold circuit used in a snapshot type readout circuit.
Background
The sensor array readout circuit usually includes a sample-and-hold circuit, for example, a voltage obtained by integrating generated photocurrent in a plurality of photosensors is sampled and held, so as to output the integrated voltage or perform analog-to-digital conversion, and for a snapshot readout circuit, the working mode is that for an M × N photosensor array, each pixel circuit includes an integrating circuit, a sample-and-hold circuit, etc., all pixels in the array start to work simultaneously, the generated photocurrent starts to be integrated simultaneously, then is sampled and held, and is output row by row under the control of a timing signal. Due to the fact that the array size M multiplied by N is larger and larger, the time required by the whole output is longer, due to the limitation of the area of a pixel layout, the influence of leakage current on the voltage of a sampling point is larger due to the fact that the integration capacitance is smaller, larger errors can be generated between the finally output voltage and the actual voltage, and even the voltage is completely lost. Therefore, a voltage sample-and-hold circuit is needed to reduce charge loss and improve the accuracy of the sampled voltage.
Disclosure of Invention
In order to solve the above technical problem, the present invention provides a sample-and-hold circuit for use in a snapshot readout circuit.
The invention is realized by the following technical scheme:
the invention provides a sample-and-hold circuit used in a snapshot readout circuit, comprising: the low-error sampling circuit comprises a low-error sampling switch circuit, a compensation circuit, a clamping circuit and a sampling capacitor Cint;
the low-error sampling switch circuit comprises a first low-error sampling switch gate1 and a second low-error sampling switch gate2 which are consistent in structure, voltage to be sampled is injected from the first low-error sampling switch gate1, the first low-error sampling switch gate1 is connected with a second low-error sampling switch gate2, and the other end of the second low-error sampling switch gate2 is connected with a sampling capacitor Cint and then grounded;
the first low-error sampling switch gate1 and the second low-error sampling switch gate2 are synchronously switched;
the clamping circuit is connected in parallel with two ends of the second low-error sampling switch gate2, so that the voltage of two ends of the second low-error sampling switch gate2 is equal;
the compensation circuit is connected in parallel at two ends of the second low-error sampling switch gate2, and the compensation circuit compensates leakage current in the sampling and holding process to the sampling capacitor.
The clamping circuit adopts a unit gain amplifier OP2, the forward end of the unit gain amplifier OP2 is connected with the sampling capacitor Cint, the output end of the unit gain amplifier OP2 is connected with the reverse end, and the output end of the unit gain amplifier OP2 is connected between the first low-error sampling switch gate1 and the second low-error sampling switch gate 2.
Further preferably, the compensation circuit includes: a third low-error sampling switch gate3, a current mirror structure and a negative feedback circuit, which are consistent with the structure of the first low-error sampling switch gate 1;
the third low-error sampling switch gate3 has a potential difference, one end of the third low-error sampling switch gate3 is connected between the first low-error sampling switch gate1 and the second low-error sampling switch gate2, the other end of the third low-error sampling switch gate3 is connected with a current mirror structure, and the current mirror structure is connected with the sampling capacitor Cint and then grounded;
the negative feedback circuit keeps the voltages on the left and right sides of the current mirror structure equal, thereby completely simulating the voltage magnitude across the second low-error sampling switch gate 2.
The current mirror structure further comprises a field effect transistor PM19 and a field effect transistor PM20, the source electrodes of the field effect transistor PM19 and the field effect transistor PM20 are connected with a power supply voltage VDD, the field effect transistor PM19 is connected with the grid electrode of the field effect transistor PM20, the drain electrode of the field effect transistor PM19 is connected with a third low-error sampling switch gate3, and the drain electrode of the field effect transistor PM20 is connected with a sampling capacitor Cint and then grounded;
the negative feedback circuit adopts an operational amplifier OP1, the positive end of the operational amplifier OP1 is connected with the drain electrode of a field effect tube PM19, the reverse end of the operational amplifier OP1 is connected with the drain electrode of a field effect tube PM20, and the output end of the operational amplifier OP1 is connected with the grid electrode of the field effect tube PM19 or the grid electrode of the field effect tube PM 20.
In a further preferred embodiment, the basic circuit structure of the third low-error sampling switch gate3, the first low-error sampling switch gate1 and the second low-error sampling switch gate2 includes: the field effect transistor comprises a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor and a sixth field effect transistor; the first field effect transistor, the second field effect transistor and the third field effect transistor are of NM type, and the fourth field effect transistor, the fifth field effect transistor and the sixth field effect transistor are of PM type.
In the basic circuit structure, the drain electrodes of the first field effect transistor, the third field effect transistor, the fourth field effect transistor and the sixth field effect transistor are in short circuit with the source electrode;
the drain electrode of the first field effect tube is connected with the source electrode of the fourth field effect tube, the source electrode of the first field effect tube is connected with the drain electrode of the second field effect tube, the source electrode of the second field effect tube is connected with the drain electrode of the third field effect tube, the source electrode of the third field effect tube is connected with the drain electrode of the sixth field effect tube, the source electrode of the sixth field effect tube is connected with the drain electrode of the fifth field effect tube, and the source electrode of the fifth field effect tube is connected with the drain electrode of the fourth field effect tube.
In a further optimized scheme, in the first low-error sampling switch gate1 and the second low-error sampling switch gate 2: the gates of the first field effect transistor, the third field effect transistor and the fifth field effect transistor are connected with a control signal ckB, the gates of the second field effect transistor, the fourth field effect transistor and the sixth field effect transistor are connected with a control signal ck, and the control signal ck and the control signal ckB are opposite clock signals.
In the third low-error sampling switch gate 3: the grids of the first field effect tube, the second field effect tube and the third field effect tube are connected with a low potential GND, and the grids of the fourth field effect tube, the fifth field effect tube and the sixth field effect tube are connected with a high potential VDD.
The further optimization scheme is that the device further comprises a reset switch gate4 and a reset switch gate5 which are consistent in structure, the reset switch gate4 is connected between the positive end and the negative end of the unit gain amplifier OP2, one end of the reset switch gate5 is connected with the negative end of the unit gain amplifier OP2, and the other end of the reset switch gate5 is grounded.
Further optimization scheme is that the reset switch gate4 or the reset switch gate5 is a complementary switch, and the complementary switch includes: the drain electrode of the seventh field effect transistor is connected with the source electrode of the eighth field effect transistor, and the source electrode of the seventh field effect transistor is connected with the drain electrode of the eighth field effect transistor; the grid electrode of the seventh field effect transistor is connected with a control signal rst, the grid electrode of the seventh field effect transistor is connected with a control signal rstB, and the control signal rs and the control signal rstB are opposite clock signals.
The working principle of the invention is as follows: when the sampling hold circuit is in a sampling state, due to the fact that the switch has a charge injection effect, the first low-error sampling switch gate1 and the second low-error sampling switch gate2 are opened, the sampling capacitor Cint starts to be charged, after the sampling process is finished, the first low-error sampling switch gate1 and the second low-error sampling switch gate2 are closed, and then charges injected into the sampling capacitor Cint flow into the field effect tube with the short-circuited drain-source electrode, so that the precision of sampling voltage is improved; wherein the compensating circuit is used for compensating the leakage current that flows into in the field effect transistor of drain-source utmost point short circuit, in snapshot formula readout circuit, whole read-out time is longer, and the on-chip electric capacity sampling is less, after a considerable time, electric charge can flow out from the sampling electric capacity and flow into the substrate through the utmost point of field effect transistor among the low error sampling switch circuit or drain electrode, thereby make sampling voltage and actual voltage great error appear, and the compensating circuit structure passes through the junction leakage current with sampling switch and compensates the leakage current back to sampling electric capacity through the current mirror structure, thereby reduce the reduction of sampling voltage.
The clamp circuit is used for reducing the leakage current passing through the sampling switch, when the sampling and holding circuit is in a holding state, a small amount of charges still flow to the drain through the source or flow to the source through the drain due to the fact that the field effect transistor is in a closed state, therefore, when the sampling and holding circuit is in the holding state, partial charges in the sampling capacitor are continuously lost through the first low-error sampling switch gate1 and the reset switch gate4, and after a long time, the sampling voltage still has a large error, the clamp circuit structure enables the voltage between the first low-error sampling switch gate1 and the second low-error sampling switch gate2, the voltage between the first low-error sampling switch gate1 and the sampling capacitor Cint, and the voltage between the reset switch gate4 and the reset switch gate5 to be equal, so that the voltage at two ends of the second low-error sampling switch gate2 is equal, the voltage at two ends of the reset switch gate4 are equal, that is, the leakage current flowing through the second low error sampling switch gate2 and the reset switch gate4 is reduced in the closed state.
By combining the technical means, the invention reduces the charge loss in the sampling capacitor, and simultaneously compensates part of the charge lost through junction leakage current, so that the whole sampling point voltage is reduced within a range meeting the requirement.
Compared with the prior art, the invention has the following advantages and beneficial effects:
compared with the situation that a low-error sampling switch is not adopted, the sampling hold circuit for the snapshot reading circuit provided by the invention reduces the charge injection effect by using the low-error sampling switch and improves the precision of sampling voltage; by adopting a leakage current compensation structure, the voltage reduction amplitude of the sampling voltage is obviously reduced; and the clamp structure of the sampling switch is combined to further limit the leakage current of the analog switch in the closed state, so that the reduction amplitude of the sampling voltage is further reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention.
In the drawings:
FIG. 1 is a schematic diagram of a sample and hold circuit of the present invention;
FIG. 2 is a schematic diagram of a portion of leakage current in the first low-error sampling switch gate 1;
FIG. 3 is a schematic diagram of a second low-error sampling switch gate 2;
FIG. 4 is a schematic structural diagram of a third low-error sampling switch gate 3;
FIG. 5 is a diagram of a conventional sampling circuit in a snapshot readout circuit;
FIG. 6 is a diagram showing the comparison result of the voltage variation with time between the circuit of the present invention and the conventional sampling circuit under the same conditions.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and the accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not used as limiting the present invention.
Example 1
As shown in the schematic diagram of a common sampling circuit in the snapshot readout circuit of fig. 5, the sampling circuit (Vin is an external voltage to be sampled) has a certain error in the sampling voltage due to the charge injection effect; now, using the specific circuit for the sample-and-hold circuit in the snapshot readout circuit provided by the present invention shown in fig. 1, the first low-error sampling switch gate1 and the second low-error sampling switch gate2 in the circuit are the same low-error sampling switches; as shown in fig. 2 and fig. 3, the gates of fet NM2, fet PM4, fet PM6, fet NM8, fet PM10 and fet PM12 in the first low-error sampling switch gate1 and the second low-error sampling switch gate2 are connected to the control signal ck, the gates of fet NM1, fet NM3, fet PM5, fet NM7, fet NM9 and fet PM11 are connected to the control signal ckB, and the control signal ck and the control signal ckB are opposite clock signals, and both are used as the periodic sampling complementary clock signals in the readout circuit. As shown in fig. 4, the third low-error sampling switch gate3 is the same sampling switch as the first low-error sampling switch gate1 and the second low-error sampling switch gate2, but the gates of the fet NM13, the fet NM14 and the fet NM15 in the third low-error sampling switch gate3 are connected to the low potential GND, and the gates of the fet PM16, the fet PM17 and the fet PM18 are connected to the high potential VDD; the reset switch gate4 and the reset switch gate5 are the same complementary switches, the gates of the field effect transistor NM21 and the field effect transistor NM23 are connected with a signal rst, the gates of the field effect transistor NM22 and the field effect transistor NM24 are connected with a reset signal rstB, the control signal rst and the control signal rstB are opposite clock signals, and the control signal rst and the control signal rstB are used as periodic sampling voltage reset complementary clock signals in the reading circuit.
The basic structure of the low-error sampling switch is a complementary analog switch, as shown in fig. 2, wherein the gate1, the gate2 and the gate3 are all sampling switches with the same structure size. Taking gate1 as an example, the gate comprises a field effect transistor NM1, a field effect transistor NM2, a field effect transistor NM3, a field effect transistor PM4, a field effect transistor PM5 and a field effect transistor PM 6; the drain electrodes and the source electrodes of the field effect transistor NM1, the field effect transistor NM3, the field effect transistor PM4 and the field effect transistor PM6 are short-circuited. In the figure, the current a is a schematic diagram of the drain/source-substrate leakage current of the fet NM1 in the off state of the switch, and the current b is a schematic diagram of the drain-source leakage current of the fet NM 2. The same principle of leakage current is applied to gate2 and gate 3.
The compensation circuit includes a third low-sampling error switch gate3, an operational amplifier OP1 and a current mirror circuit. The operational amplifier OP1 plays a role of negative feedback, so that the voltage of the point D at the right end of the third low-error sampling switch gate3 and the voltage of the point B at the right end of the second low-error sampling switch gate2 are kept equal, the voltages at the two ends of the second low-error sampling switch gate2 are completely equal, and the compensated current Inc is equal to In.
The clamp circuit mainly comprises a unit gain amplifier OP2, wherein the positive end of the unit gain amplifier OP2 is connected with the B point of the sampling capacitor Cint, the output end is connected with the reverse end, and the output end is respectively connected with the A point in the middle of the first low sampling error switch gate1 and the second low sampling error switch gate2 and the C point in the middle of the reset switches gate4 and gate 5.
Example 2
Based on the principle of the above embodiments, the present invention will be described in detail below with reference to specific examples. In this example, the parameters of the whole circuit diagram of the present invention in fig. 1 are set under the CSMS 0.18 μm cmos process, where the fets NM 1-NM 3, PM 4-PM 6, NM 7-NM 9, PM 10-PM 12, NM 13-NM 15, PM 16-PM 18, and PM 21-PM 24 all use fets with gate width of 1 μm and gate length of 350NM, the PMs 19-PM 20 use fets with gate length of 2 μm, the sampling capacitor Cint uses a capacitor of 36fF, the dc gains of the OP1 and OP2 are 54.3dB, the unit gain bandwidths are 16MHz, VDD and GND are set to 3.3V and 1.8V, respectively, and the sampling voltage is set to 2.13V.
The parameters of the ordinary sample-and-hold circuit in fig. 5 are also set, where the gate widths of the fets NM1, PM2, NM3, PM4 are 1 μm, the gate length is 350NM, and the sampling capacitor Cint is also 36 fF. The two circuits are simulated at 27 ℃, and the voltage change curves of the circuit and the voltage change curves of the common sample-and-hold circuit along with time under the same conditions can be obtained by comparing the two circuits.
In fig. 6, when the sampling voltage is 2.13V, the sampling voltage of the ordinary sample-and-hold circuit is 2.156V at the time of 0ms, and the sampling voltage of the sample-and-hold circuit of the present invention is 2.132V.
After 5ms, the voltage drop of the common sample-and-hold circuit is 1.918V, the amplitude drop is 0.212V, and the voltage is reduced by 9.95%; the voltage drop of the circuit is 2.106V, the amplitude reduction is 0.024V, and the voltage is reduced by 1.12%. Compared with the common sample hold circuit, the sample hold circuit has the advantage that the effect is improved by 8.8 times. In addition, the circuit is limited by the gain and mismatch of the operational amplifier, and the performance of the operational amplifier is improved, so that the circuit performance can be further improved.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A sample-and-hold circuit for use in a snapshot readout circuit, comprising: the low-error sampling circuit comprises a low-error sampling switch circuit, a compensation circuit, a clamping circuit and a sampling capacitor Cint;
the low-error sampling switch circuit comprises a first low-error sampling switch gate1 and a second low-error sampling switch gate2 which are consistent in structure, voltage to be sampled is injected from the first low-error sampling switch gate1, the first low-error sampling switch gate1 is connected with a second low-error sampling switch gate2, and the other end of the second low-error sampling switch gate2 is connected with a sampling capacitor Cint and then grounded;
the first low-error sampling switch gate1 and the second low-error sampling switch gate2 are synchronously switched;
the clamping circuit is connected in parallel with two ends of the second low-error sampling switch gate2, so that the voltage of two ends of the second low-error sampling switch gate2 is equal;
the compensation circuit is connected in parallel at two ends of a second low-error sampling switch gate2 and compensates leakage current in the sampling and holding process to the sampling capacitor;
the clamping circuit adopts a unit gain amplifier OP2, the forward end of the unit gain amplifier OP2 is connected with a sampling capacitor Cint, the output end of the unit gain amplifier OP2 is connected with the reverse end, and the output end of the unit gain amplifier OP2 is connected between a first low-error sampling switch gate1 and a second low-error sampling switch gate 2;
the compensation circuit includes: a third low-error sampling switch gate3, a current mirror structure and a negative feedback circuit, which are consistent with the structure of the first low-error sampling switch gate 1;
the third low-error sampling switch gate3 has a potential difference, one end of the third low-error sampling switch gate3 is connected between the first low-error sampling switch gate1 and the second low-error sampling switch gate2, the other end of the third low-error sampling switch gate3 is connected with a current mirror structure, and the current mirror structure is connected with the sampling capacitor Cint and then grounded;
the negative feedback circuit keeps the voltages on the left and right sides of the current mirror structure equal.
2. A sample-and-hold circuit for use in a snapshotting readout circuit according to claim 1,
the current mirror structure comprises a field effect transistor PM19 and a field effect transistor PM20, the source electrodes of the field effect transistor PM19 and the field effect transistor PM20 are connected with a power supply voltage VDD, the field effect transistor PM19 is connected with the grid electrode of the field effect transistor PM20, the drain electrode of the field effect transistor PM19 is connected with a third low-error sampling switch gate3, and the drain electrode of the field effect transistor PM20 is connected with a sampling capacitor Cint and then grounded;
the negative feedback circuit adopts an operational amplifier OP1, the positive end of the operational amplifier OP1 is connected with the drain electrode of the field effect transistor PM19, the reverse end of the operational amplifier OP1 is connected with the drain electrode of the field effect transistor PM20, and the output end of the operational amplifier OP1 is connected with the grid electrode of the field effect transistor PM19 and the grid electrode of the field effect transistor PM 20.
3. The sample-and-hold circuit for use in a snapshotting readout circuit of claim 1, wherein the basic circuit structure of the third low-error sampling switch gate3, the first low-error sampling switch gate1, and the second low-error sampling switch gate2 comprises: the field effect transistor comprises a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor and a sixth field effect transistor; the first field effect transistor, the second field effect transistor and the third field effect transistor are of NM type, and the fourth field effect transistor, the fifth field effect transistor and the sixth field effect transistor are of PM type.
4. The sample-and-hold circuit for use in a snapshotting readout circuit of claim 3, wherein in a basic circuit structure, drains of the first field effect transistor, the third field effect transistor, the fourth field effect transistor, and the sixth field effect transistor are shorted to a source;
the drain electrode of the first field effect tube is connected with the source electrode of the fourth field effect tube, the source electrode of the first field effect tube is connected with the drain electrode of the second field effect tube, the source electrode of the second field effect tube is connected with the drain electrode of the third field effect tube, the source electrode of the third field effect tube is connected with the drain electrode of the sixth field effect tube, the source electrode of the sixth field effect tube is connected with the drain electrode of the fifth field effect tube, and the source electrode of the fifth field effect tube is connected with the drain electrode of the fourth field effect tube.
5. A sample-and-hold circuit for use in a snapshotting readout circuit according to claim 3,
in the first low-error sampling switch gate1 and the second low-error sampling switch gate 2: the gates of the first field effect transistor, the third field effect transistor and the fifth field effect transistor are connected with a control signal ckB, the gates of the second field effect transistor, the fourth field effect transistor and the sixth field effect transistor are connected with a control signal ck, and the control signal ck and the control signal ckB are opposite clock signals;
in the third low-error sampling switch gate 3: the grids of the first field effect tube, the second field effect tube and the third field effect tube are connected with a low potential GND, and the grids of the fourth field effect tube, the fifth field effect tube and the sixth field effect tube are connected with a high potential VDD.
6. The sample-and-hold circuit for use in a snapshot readout circuit as claimed in claim 1, further comprising a reset switch gate4 and a reset switch gate5, wherein the reset switch gate4 is connected between the forward terminal and the reverse terminal of the unit gain amplifier OP2, one end of the reset switch gate5 is connected to the reverse terminal of the unit gain amplifier OP2, and the other end of the reset switch gate5 is grounded.
7. A sample-and-hold circuit for use in a snapshotting readout circuit, according to claim 6, wherein the reset switch gate4 and reset switch gate5 are complementary switches comprising: the drain electrode of the seventh field effect transistor is connected with the source electrode of the eighth field effect transistor, and the source electrode of the seventh field effect transistor is connected with the drain electrode of the eighth field effect transistor; the grid electrode of the seventh field effect transistor is connected with a control signal rst, the grid electrode of the seventh field effect transistor is connected with a control signal rstB, and the control signal rs and the control signal rstB are opposite clock signals.
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| US5994841A (en) * | 1996-10-25 | 1999-11-30 | Welch Allyn, Inc. | Circuit for biasing display device by compensating for a varying leakage current |
| CN101330261A (en) * | 2007-06-18 | 2008-12-24 | 天钰信息科技（上海）有限公司 | Switch power circuit |
| DE102007048453B3 (en) * | 2007-10-10 | 2009-06-10 | Texas Instruments Deutschland Gmbh | Switch with low power loss for sampling and holding |
| US8427353B2 (en) * | 2011-02-15 | 2013-04-23 | Credo Semiconductor (Hong Kong) Limited | High-speed flash analog to digital converter |
| US8415985B2 (en) * | 2011-07-11 | 2013-04-09 | Texas Instruments Incorporated | Circuits and methods for sampling and holding differential input signals |
| CN103023469B (en) * | 2011-09-23 | 2015-12-02 | 国民技术股份有限公司 | A kind of boot-strapped switch circuit |
| CN103913700B (en) * | 2014-04-18 | 2017-04-05 | 电子科技大学 | A kind of detection circuit of infrared focal plane read-out circuit |
| CN108449557B (en) * | 2018-03-23 | 2019-02-15 | 上海芯仑光电科技有限公司 | Pixel Acquisition Circuit, light stream sensor and light stream and image information collecting system |
| CN109974863B (en) * | 2019-03-01 | 2020-08-11 | 电子科技大学 | Integration circuit applied to ultraviolet focal plane detector |
| CN111277236B (en) * | 2020-02-04 | 2021-09-07 | 西安交通大学 | Front-end circuit based on gain self-adaptive adjustment and dynamic range improving method |
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