JP2013191911A - Analog switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce noise caused by substrate bias control of a MOS transistor.SOLUTION: A transistor P5 turns on when a transistor P1 is on, and a transistor P6 turns on when the transistor P1 is off to whereby perform substrate bias control. When the transistor P1 is on, a supply voltage VDD is applied to a back gate of a transistor N2 via a transistor P3, and when the transistor P1 is off, a ground potential is applied to the back gate of the transistor N2 via a transistor P4. This can reduce noise due to clock feedthrough via a capacitance between a drain and a back gate of the MOS transistor P1.

Description

  The present invention relates to an analog switch using a MOS transistor.

  Generally, a low impedance signal source is connected to one terminal (first terminal) of an analog switch, and an input terminal such as a comparator or an operational amplifier or a hold capacitor is connected to the other terminal (second terminal). . Input capacitors exist at input terminals of comparators and operational amplifiers. The analog switch is required to have a low internal resistance when conducting, a small leakage current when shut off, and a small potential fluctuation due to the injection of charge into the second terminal during the off operation.

  Patent Document 1 discloses an analog switch that performs substrate bias control on a MOS transistor that operates as a main switch. This analog switch lowers the internal resistance by applying the voltage of the first terminal or the second terminal to the back gate to make the substrate bias zero when the MOS transistor is turned on. Further, when the MOS transistor is shut off, a leakage current is reduced by applying a power supply voltage or a ground potential to the back gate.

  Further, it is known that when a MOS transistor that operates as a main switch turns from on to off, potential fluctuation occurs at the second terminal due to charge injection or clock feedthrough. Charge injection is a phenomenon in which the charge of the channel when the MOS transistor is on escapes to the source or drain as it is turned off. Clock feedthrough is a phenomenon in which a change in a clock signal applied to a gate passes through the source or drain through a gate-drain capacitance or a gate-source capacitance. In the following description, the potential fluctuation caused by the charge transfer is referred to as noise.

  In order to eliminate the effects of charge injection and clock feedthrough, means using a dummy transistor in which the source and drain are commonly connected to the second terminal of the analog switch and the inverted signal of the clock signal is given to the gate is known. . Patent Document 2 describes means using a dummy transistor in which a gate is connected to a second terminal of an analog switch, and an inverted signal of the clock signal is applied to a commonly connected source and drain.

JP-A-6-169247 JP-A 64-42916

  The dummy transistor described above is effective for charge injection of a MOS transistor and clock feedthrough between the gate and drain or between the gate and source. However, when the substrate bias control is performed, the potential of the back gate is changed, so that a clock feedthrough is newly generated via the capacitance between the drain and the back gate of the MOS transistor, and noise is generated.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an analog switch capable of reducing noise caused by substrate bias control of a MOS transistor.

  The analog switch according to claim 1 is provided with a power supply voltage by a high-potential-side power supply line and a low-potential-side power supply line, and in response to a first control signal and a second control signal that is an inverted signal thereof, Open and close the energization path between the two terminals. The P-channel type first MOS transistor (P1) has a source and a drain connected to the first terminal and the second terminal, respectively, and energization between the first terminal and the second terminal using the second control signal as a gate signal. Open and close the route.

  The first bias circuit (12) performs substrate bias control of the first MOS transistor. That is, the potential of the back gate (substrate) is controlled to be equal to the source potential when the first MOS transistor is driven on, and the potential of the back gate is equal to the power supply voltage when the first MOS transistor is driven off. Control. As a result, the internal resistance when the analog switch is conducting can be lowered, and the leakage current when shutting off can be reduced.

  However, when the substrate bias control of the first MOS transistor is performed, clock feedthrough occurs in which the potential change of the back gate provided by the first bias circuit leaks through the capacitance CDB between the drain and the back gate of the first MOS transistor. Therefore, the second MOS transistor (N2) and the second bias circuit (11) are provided to cancel the influence of this clock feedthrough.

  The source and drain of the second MOS transistor (N2) are connected in common, one of the commonly connected source, drain and gate is connected to the drain of the first MOS transistor, and a constant voltage is applied to the other. The second bias circuit (11) controls the back gate potential of the second MOS transistor to be equal to the power supply voltage when the first MOS transistor is turned on, and the second MOS transistor when the first MOS transistor is driven off. The back gate potential is controlled to be equal to a constant voltage lower than the power supply voltage.

  According to this configuration, when the first MOS transistor is turned off, noise (potential fluctuation) generated in the drain due to the increase in the back gate potential of the first MOS transistor due to the substrate bias control, and the back gate potential of the second MOS transistor are By lowering, noise (potential fluctuation) generated in the drain is reversed and acts to cancel. As a result, noise generated by the substrate bias control of the first MOS transistor can be reduced.

  According to the means described in claim 2, the second bias circuit (11) is connected between the high-potential side power supply line and the back gate of the second MOS transistor, and has a P channel using the second control signal as a gate signal. Type third MOS transistor (P3) and an N-channel type fourth MOS transistor (N4) connected between the back gate of the second MOS transistor and the low-potential side power supply line and using the second control signal as a gate signal It is configured.

  According to this configuration, when the first MOS transistor is turned off, the potential of the back gate of the first MOS transistor changes from the input voltage Vin to the power supply voltage VDD by (VDD−Vin) by the substrate bias control. In contrast, the potential of the back gate of the second MOS transistor changes from the power supply voltage VDD to the ground potential by −VDD. Thus, since both voltages change in the opposite directions, noise due to clock feedthrough through the capacitor CDB of the first MOS transistor can be reduced.

  According to the means described in claim 3, the first bias circuit (12) is connected between the source of the first MOS transistor and the back gate, and the P-channel fifth MOS using the second control signal as a gate signal. It comprises a transistor (P5) and a P-channel sixth MOS transistor (P6) connected between the high-potential side power line and the back gate of the first MOS transistor and using the first control signal as a gate signal. . Since the fifth MOS transistor is connected to the source of the first MOS transistor, no charge injection occurs.

  According to the means described in claim 4, the source and drain are connected in common, one of the commonly connected source, drain and gate is connected to the drain of the first MOS transistor, and the other is the first control signal. A P-channel type seventh MOS transistor (P7) is provided. The seventh MOS transistor corresponds to the above-described dummy transistor, and can reduce noise due to charge injection of the first MOS transistor and clock feedthrough between its gate and drain.

  The analog switch according to any one of claims 5 to 8, further comprising an N-channel first MOS transistor in a current-carrying path between the first terminal and the second terminal. And substantially the same operation and effect.

  According to the means described in claim 9, the capacitance between the source and the back gate of the second MOS transistor and the capacitance between the drain and the back gate are respectively the capacitance between the drain and the back gate of the first MOS transistor. 1/2 of this. According to this configuration, the capacitance between the drain and the back gate of the first MOS transistor is equal to the capacitance between the source and drain commonly connected to the second MOS transistor and the back gate. As a result, the noise canceling effect by the clock feedthrough via the capacitor CDB can be further enhanced.

  According to a tenth aspect of the present invention, the analog switch includes a short switch provided in the input part of the chopper comparator, a changeover switch provided in the A / D converter, a changeover switch provided in the multiplexer, or a switched capacitor filter. Applies to changeover switches. Thereby, comparison of analog signals, A / D conversion, and switching of analog signals can be performed with high accuracy.

The block diagram of the analog switch which shows the 1st Embodiment of this invention FIG. 1 equivalent diagram showing a second embodiment of the present invention The figure which is the 3rd Embodiment of this invention, and shows the example of application to the A / D converter of an analog switch

(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIG. The analog switch 1 shown in FIG. 1 operates by a power supply voltage VDD supplied through a power supply line 2 (high potential power supply line) and a ground line 3 (low potential power supply line). Terminal 4 (first terminal) and terminal 5 (second terminal) are input / output terminals for analog signals, and terminal 6 is a control terminal to which a control signal Sc for controlling opening and closing of the switch is input. When formed as a semiconductor integrated circuit device, the terminals 4 to 6 become nodes 4 to 6.

  A low-impedance signal source (not shown) is connected to the terminal 4, and a load capacitor CL such as an input capacitor of a comparator or an operational amplifier or a hold capacitor is connected between the terminal 5 and the ground line 3. . However, this connection form is merely an example, and any element, terminal, node, or the like that inputs and outputs an analog signal can be connected to the terminal 4 and the terminal 5.

  The control signal Sc input to the terminal 6 becomes the control signals S1 and S2 through the buffer 7 and the inverter 8, respectively, and is given to the gate of the MOS transistor described below. The energization paths 9 and 10 between the terminal 4 and the terminal 5 are respectively provided with a P-channel first MOS transistor P1 and an N-channel first MOS transistor N1 that operate as main switches. Here, the terminal 4 side is a source, and the terminal 5 side is a drain. The gate signals of the MOS transistors P1 and N1 are control signals S2 and S1, respectively.

  The second MOS transistor N2 and the second bias circuit 11 are provided to cancel the influence of clock feedthrough via the capacitance CDB between the drain and back gate of the MOS transistor P1. The source and drain of the MOS transistor N2 are both connected to the drain of the MOS transistor P1, and the gate is connected to the ground line 3.

  The bias circuit 11 includes a P-channel third MOS transistor P3 and an N-channel fourth MOS transistor N4. The MOS transistor P3 is connected between the power supply line 2 and the back gate of the MOS transistor N2, and uses the control signal S2 as a gate signal. The MOS transistor N4 is connected between the back gate of the MOS transistor N2 and the ground line 3, and uses the control signal S2 as a gate signal.

  The first bias circuit 12 is provided for performing substrate bias control of the MOS transistor P1. The bias circuit 12 includes a P-channel fifth MOS transistor P5 and a P-channel sixth MOS transistor P6. The MOS transistor P5 is connected between the source and back gate of the MOS transistor P1, and uses the control signal S2 as a gate signal. The MOS transistor P6 is connected between the power supply line 2 and the back gate of the MOS transistor P1, and uses the control signal S1 as a gate signal.

  The seventh MOS transistor P7 is provided to cancel the influence of the charge injection of the MOS transistor P1 and the clock feedthrough between its gate and drain. The source and drain of the MOS transistor P7 are both connected to the drain of the MOS transistor P1, and a control signal S1 is applied to the gate.

  The seventh MOS transistor N7 is provided to cancel the influence of the charge injection of the MOS transistor N1 and the clock feedthrough between its gate and drain. The source and drain of the MOS transistor N7 are both connected to the drain of the MOS transistor N1, and a control signal S2 is applied to the gate.

  In the present embodiment, a simple configuration is adopted for the energization path 10 including the MOS transistor N1. Therefore, a configuration corresponding to the second MOS transistor N2, the first bias circuit 12, and the second bias circuit 11 provided for the energization path 9 including the MOS transistor P1 is not provided.

  Next, the operation of this embodiment will be described. When the control signal Sc is at the H level (VDD), both the MOS transistors P1 and N1 are turned on, and the analog switch 1 is turned on. When the control signal Sc is at the L level (0 V), both the MOS transistors P1 and N1 are turned off, and the analog switch 1 is cut off. The bias circuit 12 performs substrate bias control by switching the potential of the back gate (substrate) of the MOS transistor P1.

  That is, when the MOS transistor P1 is turned on, the MOS transistor P5 is turned on to make the back gate potential (substrate potential) equal to the source potential. As a result, the threshold voltage Vth of the transistor P1 is lowered, and the internal resistance during conduction can be lowered. On the other hand, when the MOS transistor P1 is off, the MOS transistor P6 is turned on to make the back gate potential (substrate potential) equal to the power supply voltage VDD. As a result, the threshold voltage Vth of the transistor P1 is increased, and the leakage current at the time of interruption can be reduced.

  When the MOS transistors P1 and N1 turn from on to off, charges are injected into the drain side (terminal 5 side) of the MOS transistors P1 and N1 for the following reasons (1) and (2), and potential fluctuation, that is, noise is generated. To reduce the accuracy of the signal. The charge injection of the MOS transistor P5 does not affect the subsequent stage (terminal 5 side) because the drain (source) is connected to the terminal 4 side.

(1) Charge injection by channel charge of MOS transistors P1, N1 and clock feedthrough via gate-drain capacitance CGD (2) Via capacitance CDB between the drain and back gate of MOS transistors P1, N1 In this embodiment, the noise due to (1) is reduced by the MOS transistors P7 and N7, and the noise due to the MOS transistor P1 in (2) is reduced by the MOS transistor N2 and the bias circuit 11. Regarding the noise caused by the MOS transistor N1 in (2), no circuit for canceling is provided.

  Regarding (1), the MOS transistors P7 and N7 operating in opposite phases to the MOS transistors P1 and N1, respectively, are dummy transistors conventionally used. That is, by turning on the MOS transistor P7 when the MOS transistor P1 is turned off, the MOS transistor P7 absorbs the channel charge injected from the MOS transistor P1 into the conduction path 9 on the drain side as its own channel charge. Thereby, noise due to charge injection can be reduced. Further, if the channel width of the MOS transistor P7 is ½ of the channel width of the MOS transistor P1 (the channel length is equal), noise due to clock feedthrough can be reduced. The operation of the MOS transistor N7 is the same.

  Regarding (2), when the MOS transistor P1 is turned off, a voltage change opposite in phase to the voltage change of the back gate of the MOS transistor P1 is applied to the back gate of the MOS transistor N2. That is, when the voltage Vin of the terminal 4 is applied to the back gate of the MOS transistor P1 which is turned on via the MOS transistor P5, the power supply voltage VDD is applied to the back gate of the MOS transistor N2 via the MOS transistor P3. . On the contrary, when the power supply voltage VDD is applied to the back gate of the MOS transistor P1 which is turned off via the MOS transistor P6, the ground potential (0 V) is applied to the back gate of the MOS transistor N2 via the MOS transistor N4. It is done.

  As a result, when the MOS transistor P1 is turned off, the potential of the back gate of the MOS transistor P1 changes from the input voltage Vin to the power supply voltage VDD by (VDD−Vin). On the other hand, the potential of the back gate of the MOS transistor N2 changes from the power supply voltage VDD to the ground potential 0V by -VDD. Since both voltages change in opposite directions, the action of raising the potential of the conduction path 9 through the capacitance CDB of the MOS transistor P1 and the action of lowering the potential of the conduction path 9 through the capacitance C (SD) B of the MOS transistor N2 cancel each other. Noise due to clock feedthrough can be reduced.

  Here, the source-back gate capacitance CSB and the drain-back gate capacitance CDB of the MOS transistor N2 are preferably ½ of the drain-back gate capacitance CDB of the MOS transistor P1, respectively. . According to this configuration, the capacitance CDB between the drain and the back gate of the MOS transistor P1 is equal to the capacitance C (SD) B between the source / drain and the back gate that are commonly connected to the MOS transistor N2. As a result, although it depends on the input voltage Vin, the effect of canceling potential fluctuation (noise) due to clock feedthrough through the capacitance CDB of the MOS transistor P1 can be enhanced.

  As described above, the analog switch 1 of the present embodiment performs the substrate bias control by switching the potential of the back gate of the MOS transistor P1 by the bias circuit 12, so that the internal resistance when the analog switch 1 is turned on decreases. Leakage current when cut off is reduced. In addition, the MOS transistor N2 is connected to the energization path 9 provided with the MOS transistor P1, and the potential of the back gate of the MOS transistor N2 is controlled by the bias circuit 11 in a phase opposite to that of the back gate of the MOS transistor P1. As a result, it is possible to reduce noise due to clock feedthrough that occurs with substrate bias control. Furthermore, since the MOS transistors P7 and N7 are provided, noise due to charge injection and clock feedthrough of the MOS transistors P1 and N1 can be reduced.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIG. In FIG. 2, the same parts as those in FIG. Contrary to the analog switch 1 shown in FIG. 1, the analog switch 21 adopts a simple configuration for the energization path 9 including the MOS transistor P1. Therefore, the MOS transistors N2, P3, N4, P5, and P6 are not provided, and the MOS transistors P2, N3, P4, N5, and N6 are provided instead.

  The second MOS transistor P2 and the second bias circuit 22 are provided in order to cancel the influence of clock feedthrough via the capacitor CDB between the drain and back gate of the MOS transistor N1. The source and drain of the MOS transistor P2 are both connected to the drain of the MOS transistor N1, and the gate is connected to the power supply line 2.

  The bias circuit 22 includes an N-channel third MOS transistor N3 and a P-channel fourth MOS transistor P4. The MOS transistor N3 is connected between the back gate of the MOS transistor P2 and the ground line 3, and uses the control signal S1 as a gate signal. The MOS transistor P4 is connected between the power supply line 2 and the back gate of the MOS transistor P2, and uses the control signal S1 as a gate signal.

  The first bias circuit 23 is provided for performing substrate bias control of the MOS transistor N1. The bias circuit 23 includes an N-channel fifth MOS transistor N5 and an N-channel sixth MOS transistor N6. The MOS transistor N5 is connected between the source and back gate of the MOS transistor N1, and uses the control signal S1 as a gate signal. The MOS transistor N6 is connected between the back gate of the MOS transistor N1 and the ground line 3, and uses the control signal S2 as a gate signal.

  The operation of this embodiment is substantially the same as that of the first embodiment. Therefore, only the main points will be described below. The bias circuit 23 performs substrate bias control by switching the potential of the back gate of the MOS transistor N1. When the MOS transistor N1 is on, the potential of the back gate is controlled to be equal to the source potential via the MOS transistor N5, and when it is off, the potential of the back gate is controlled to be equal to the ground potential via the MOS transistor N6. Thereby, the internal resistance at the time of conduction is lowered and the leakage current at the time of interruption is reduced.

  The MOS transistor P2 and the bias circuit 22 reduce noise due to clock feedthrough via the capacitance CDB between the back gate and the drain of the MOS transistor N1. When the MOS transistor N1 is turned off, a voltage change opposite to the voltage change of the back gate of the MOS transistor N1 is given to the back gate of the MOS transistor P2. That is, when the voltage Vin is applied to the back gate of the MOS transistor N1 that is turned on, the ground potential is applied to the back gate of the MOS transistor P2 via the MOS transistor N3. Conversely, when the ground potential is applied to the back gate of the MOS transistor N1 that is turned off, the power supply voltage VDD is applied to the back gate of the MOS transistor P2 via the MOS transistor P4.

  As a result, when the MOS transistor N1 is turned off, the action of lowering the potential of the conduction path 10 through the capacitance CDB of the MOS transistor N1 and the action of raising the potential of the conduction path 10 through the capacitance CDB of the MOS transistor P2 are offset. Noise due to through can be reduced. Also in this embodiment, it is preferable that the capacitances CSB and CDB of the MOS transistor P2 are each ½ of the capacitance CDB of the MOS transistor N1.

  According to the present embodiment, the substrate bias control of the MOS transistor N1 reduces the internal resistance when the analog switch 21 is turned on, and reduces the leakage current when cut off. Further, the MOS transistor P2 is connected to the energization path 10 provided with the MOS transistor N1, and the potential of the back gate is controlled to be opposite in phase to the potential of the back gate of the MOS transistor P1. As a result, it is possible to reduce noise due to clock feedthrough that occurs with substrate bias control.

(Third embodiment)
FIG. 3 shows a partial circuit configuration in which the analog switch 31 is applied to the A / D converter 32. The analog switch 31 used here has a configuration obtained by removing the circuits (MOS transistors N1 and N7) on the side of the energizing path 10 from the analog switch 1 described in the first embodiment. The reference voltage generation circuit 33 divides the power supply voltage VDD by resistors R1 and R2, and outputs the obtained reference voltage Vref through an operational amplifier 34 connected in the form of a voltage follower.

  The chopper comparator 35 compares the voltage of the common line 36 with the reference voltage Vref, and an A / D conversion code is determined based on the comparison result. The chopper comparator 35 has a configuration in which a plurality of differential amplifier circuits 37, 38,... Are connected in cascade through capacitors C1, C2, and the like. A switch 39 is connected between the input terminals of the second-stage differential amplifier circuit 38. The common line 36 is connected to terminals of capacitors CA1, CA2,... Constituting a capacitor array.

  The analog switch 31 is provided as a short switch for calibration between the output node of the reference voltage generation circuit 33 and the common line 36. When the analog switch 31 is turned on while the switch 39 is turned on, electric charges are accumulated in the capacitors C1 and C2 according to the offset voltage appearing at the differential output terminal of the differential amplifier circuit 37. Subsequently, when the analog switch 31 is turned off with the switch 39 turned off, the comparison error due to the offset voltage of the chopper comparator 35 can be reduced in the subsequent comparison operation. If the analog switch 31 is used, charge injection (noise) to the common line 36 can be reduced when switching from on to off, and an accurate A / D conversion code can be obtained.

(Other embodiments)
As mentioned above, although preferred embodiment of this invention was described, this invention is not limited to embodiment mentioned above, A various deformation | transformation and expansion | extension can be performed within the range which does not deviate from the summary of invention.

The MOS transistor included in the analog switch 1 of the first embodiment and the MOS transistor included in the analog switch 21 of the second embodiment may be provided.
A configuration in which the circuit (MOS transistors P1, P7) on the side of the energization path 9 is removed from the analog switch 21 of the second embodiment may be adopted.

  The MOS transistor N2 may be a P-channel type, and a constant voltage, for example, the power supply voltage VDD may be applied to the gate. Further, the gate of the N channel type or P channel type MOS transistor N2 may be connected to the drain of the MOS transistor P1, and a constant voltage may be applied to the commonly connected source and drain.

  The MOS transistor P2 may be an N-channel type, and a constant voltage such as a ground potential may be applied to the gate. Alternatively, the gate of the P-channel or N-channel MOS transistor P2 may be connected to the drain of the MOS transistor N1, and a constant voltage may be applied to the commonly connected source and drain.

  In the first embodiment, a constant voltage line having a constant voltage lower than the power supply voltage VDD may be prepared, and the MOS transistor N4 may be connected between the back gate of the MOS transistor N2 and the constant voltage line. Even in this case, when the MOS transistor P1 is turned off, the potential of the back gate of the MOS transistor N2 changes in the opposite direction to the potential of the back gate of the MOS transistor P1. Accordingly, noise due to clock feedthrough through the capacitor CDB of the MOS transistor P1 can be reduced.

  In the second embodiment, a constant voltage line having a constant voltage higher than the ground potential may be prepared, and the MOS transistor P4 may be connected between the constant voltage line and the back gate of the MOS transistor P2. Even in this case, when the MOS transistor N1 is turned off, the potential of the back gate of the MOS transistor P2 changes in the opposite direction to the potential of the back gate of the MOS transistor N1. Accordingly, noise due to clock feedthrough through the capacitor CDB of the MOS transistor N1 can be reduced.

  The gate of the MOS transistor P7 may be connected to the drain of the MOS transistor P1, and the control signal S1 may be applied to the commonly connected source and drain. The gate of the MOS transistor N7 may be connected to the drain of the MOS transistor N1, and the control signal S2 may be applied to the commonly connected source and drain.

The various analog switches described above can be used as the analog switch used in the third embodiment.
The various analog switches described above can be applied to a changeover switch included in an A / D converter, a changeover switch included in a multiplexer, or a changeover switch included in a switched capacitor filter. Thus, A / D conversion and analog signal switching can be performed with high accuracy.

  In the drawing, 1, 21 and 31 are analog switches, 2 is a power line (high potential side power line), 3 is a ground line (low potential side power line), 4 is a terminal (first terminal), and 5 is a terminal (first terminal). 2 terminals), 9, 10 are energization paths, 11, 22 are second bias circuits, 12, 23 are first bias circuits, 32 is an A / D converter, 35 is a chopper comparator, P1, N1 are first MOS transistors, P2, N2 are second MOS transistors, P3, N3 are third MOS transistors, P4, N4 are fourth MOS transistors, P5, N5 are fifth MOS transistors, P6, N6 are sixth MOS transistors, P7, N7 are seventh MOS transistors, S1, S2 is the first and second control signals.

Claims (10)

A power supply voltage is given by the high potential side power supply line and the low potential side power supply line, and the energization path between the first terminal and the second terminal is opened and closed according to the first control signal and the second control signal which is the inverted signal thereof. In analog switch to
A P-channel first MOS transistor (P1) having a source and a drain connected to the first terminal and the second terminal, respectively, and having the second control signal as a gate signal;
When the first MOS transistor is turned on, the potential of the back gate is controlled to be equal to the source potential, and when the first MOS transistor is driven to be turned off, the potential of the back gate is controlled to be equal to the power supply voltage. 1 bias circuit (12);
A second MOS transistor (N2) having a source and a drain connected in common, one of the commonly connected source, drain and gate connected to the drain of the first MOS transistor and a constant voltage applied to the other;
The potential of the back gate of the second MOS transistor is controlled to be equal to the power supply voltage when the first MOS transistor is driven on, and the potential of the back gate of the second MOS transistor when the first MOS transistor is driven off. And a second bias circuit (11) for controlling the voltage equal to a constant voltage lower than the power supply voltage. The second bias circuit (11)
A P-channel third MOS transistor (P3) connected between the high-potential-side power line and the back gate of the second MOS transistor, and using the second control signal as a gate signal;
An N-channel fourth MOS transistor (N4) connected between the back gate of the second MOS transistor and the low-potential-side power supply line and using the second control signal as a gate signal is provided. The analog switch according to claim 1. The first bias circuit (12)
A P-channel fifth MOS transistor (P5) connected between a source and a back gate of the first MOS transistor and having the second control signal as a gate signal;
A P-channel type sixth MOS transistor (P6) is connected between the high-potential-side power line and the back gate of the first MOS transistor, and uses the first control signal as a gate signal. The analog switch according to claim 1 or 2.   A P-channel seventh MOS transistor in which a source and a drain are connected in common, one of the commonly connected source, drain and gate is connected to the drain of the first MOS transistor, and the other is supplied with the first control signal The analog switch according to any one of claims 1 to 3, further comprising (P7). A power supply voltage is given by the high potential side power supply line and the low potential side power supply line, and the energization path between the first terminal and the second terminal is opened and closed according to the first control signal and the second control signal which is the inverted signal thereof. In analog switch to
An N-channel first MOS transistor (N1) having a source and a drain connected to the first terminal and the second terminal, respectively, and having the first control signal as a gate signal;
When the first MOS transistor is turned on, the potential of the back gate is controlled to be equal to the source potential, and when the first MOS transistor is driven to be turned off, the potential of the back gate is controlled to be equal to the ground potential. 1 bias circuit (23);
A second MOS transistor (P2) in which a source and a drain are connected in common, one of the commonly connected source, drain and gate is connected to the drain of the first MOS transistor and a constant voltage is applied to the other;
The back gate potential of the second MOS transistor is controlled to be equal to the ground potential when the first MOS transistor is driven on, and the back gate potential of the second MOS transistor is controlled when the first MOS transistor is driven off. And a second bias circuit (22) for controlling the voltage equal to a constant voltage higher than the ground potential. The second bias circuit (22)
An N-channel third MOS transistor (N3) connected between a back gate of the second MOS transistor and the low-potential-side power line, and using the first control signal as a gate signal;
A P-channel fourth MOS transistor (P4) connected between the high-potential-side power supply line and the back gate of the second MOS transistor and having the first control signal as a gate signal is provided. The analog switch according to claim 5. The first bias circuit (23)
An N-channel fifth MOS transistor (N5) connected between a source and a back gate of the first MOS transistor and using the first control signal as a gate signal;
An N-channel sixth MOS transistor (N6) connected between the back gate of the first MOS transistor and the low-potential-side power supply line and using the second control signal as a gate signal is provided. The analog switch according to claim 5 or 6.   An N-channel seventh MOS transistor in which a source and a drain are connected in common, one of the commonly connected source, drain and gate is connected to the drain of the first MOS transistor, and the other is supplied with the second control signal The analog switch according to any one of claims 5 to 7, further comprising (N7).   The capacitance between the source and the back gate of the second MOS transistor and the capacitance between the drain and the back gate are respectively ½ of the capacitance between the drain and the back gate of the first MOS transistor. An analog switch according to any one of claims 1 to 8.   10. The invention is applied to a short switch provided at an input part of a chopper comparator, a changeover switch provided in an A / D converter, a changeover switch provided in a multiplexer, or a changeover switch provided in a switched capacitor filter. An analog switch according to any one of the above.

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