JP2019036818A - Output circuit - Google Patents

Abstract

To provide an output circuit capable of restraining through current by simple configuration.SOLUTION: An output circuit 2 includes first through third transistors 21-23, and a resistive element 24. The first and second transistors 21, 22 are connected in series between a power supply 25 and a ground terminal 28. The resistive element 24 has one end connected with the power supply 25, and the other end connected with the gate G1 of the first transistor 21. The third transistor 23 is connected between the other end of the resistive element 24 and the ground terminal 28. A parasitic capacitance (capacitor 29) accompanies the first transistor 21. The parasitic capacitance and the resistive element 24 constitute a lowpass filter between the power supply 25 and the third transistor 23. Time constant of the lowpass filter constituted of the parasitic capacitance of the first transistor 21 and the resistive element 24 is larger than the switching time constant of the second transistor 22.SELECTED DRAWING: Figure 1

Description

  The technology disclosed in this specification relates to an output circuit. In particular, the present invention relates to an output circuit for converting a level of a low voltage pulse signal into a high voltage pulse signal.

  An output circuit in which the voltage at the output terminal is switched between a ground voltage and a power supply voltage is known. A typical output circuit includes two switching elements connected in series between a ground and a power supply, and the midpoint of the series connection is connected to the output terminal. Hereinafter, of the two switching elements whose middle points are connected to the output terminal, the switching element on the high potential side is referred to as the upper switching element, and the switching element on the low potential side is referred to as the lower switching element. When the upper switching element is switched to the on state and the lower switching element is switched to the off state, the output terminal is held at the power supply voltage. When the upper switching element is switched to the off state and the lower switching element is switched to the on state, the output terminal is switched to the ground voltage. A signal output from the output terminal is a pulse signal having a LOW level of the ground voltage and a HIGH level of the power supply voltage.

  In general, a p-channel switching element is used as the upper switching element, and an n-channel switching element is used as the lower switching element. In the p-channel type switching element, on / off is switched by a pulse signal having a voltage amplitude lower than the power supply voltage with reference to the potential on the high voltage side. In an n-channel type switching element, on and off are switched by an input pulse signal having a voltage amplitude lower than the power supply voltage with reference to the potential on the low voltage side. Therefore, when a low-voltage input pulse signal is supplied with reference to the ground, the on / off control of the lower switching element is possible by connecting the input pulse signal directly to the gate of the n-channel switching element. is there. On the other hand, in order to control the gate of the p-channel type switching device, a level conversion circuit (for example, Patent Document 1) is used to generate a signal in which the HIGH level of the input pulse signal is raised to the power supply voltage and It is necessary to control. The level conversion circuit requires a plurality of elements (the level conversion circuit disclosed in Patent Document 1 requires four transistors). A series connection in which a p-channel MOS (Metal-Oxide-Semiconductor) transistor is used as the upper switching element and an n-channel MOS transistor is used as the lower switching element is a CMOS (Complementary MOS) circuit or a complementary MOS circuit. It is called and widely used (for example, Patent Document 1).

  In an output circuit using a series connection of two switching elements on the output side, when the upper and lower switching elements are switched, a current flows directly from the power supply to the ground. Such a current is called a “through current”. If the through current is large, the circuit may be damaged. The output circuit disclosed in Patent Document 2 switches one switching element from on to off and then receives the turn-off signal to switch the other switching element from off to on. Thus, the occurrence of a period during which both switching elements are turned on is avoided, and the through current is suppressed.

JP 2006-94301 A JP 2014-27515 A

  The output circuit disclosed in Patent Document 2 is provided with a complicated circuit in front of the CMOS circuit to adjust the switching timing of the upper and lower switching elements so that the through current is reduced. The present specification provides an output circuit capable of suppressing a through current with a very simple circuit configuration.

  The output circuit disclosed in the present specification includes three n-channel switching elements (first to third switching elements), a resistance element, an output terminal, and an input terminal. The first and second switching elements are connected in series between the power supply and the ground. For convenience of explanation, of the two switching elements connected in series, the high potential side is referred to as a first switching element, and the low potential side is referred to as a second switching element. An output end is connected to the midpoint of the series connection of the first and second switching elements. The resistance element has one end connected to the power supply and the other end connected to the gate of the first switching element. A third switching element is connected between the other end of the resistance element and the ground. The input end is connected to the gate of the second switching element and the gate of the third switching element. A parasitic capacitance is associated with the first switching element. The parasitic capacitance and the resistance element constitute a low-pass filter between the power supply and the gate of the first switching element. In the output circuit disclosed in this specification, the time constant of the low-pass filter including the parasitic capacitance of the first switching element and the resistance element is larger than the switching time constant of the second switching element.

  In the above output circuit, the input pulse signal input to the input terminal is output from the output terminal after the HIGH level voltage is converted to the power supply voltage (the HIGH level voltage of the input pulse signal is the power supply voltage of the output circuit). May be lower). When the voltage at the input terminal is switched from HIGH level to LOW level, the second and third switching elements are immediately switched from ON to OFF. Since the third switching element is turned off, the gate of the first switching element (hereinafter referred to as the first gate) is disconnected from the ground, and current flows from the power source to the first gate through the resistance element. Since the time constant of the low-pass filter between the power source and the first gate is larger than the switching time constant of the second switching element, the voltage of the first gate rises to the ON voltage after the second switching element is turned off. Become. Accordingly, the through current is suppressed. When the voltage at the input terminal is switched from the LOW level to the HIGH level, the second and third switching elements are switched from OFF to ON. Only the third switching element is connected between the first gate and the ground, and the impedance between the first gate and the ground is generally smaller than the impedance of the load connected to the output terminal. For this reason, when the voltage at the input terminal is switched from the HIGH level to the LOW level, the first switching element is also turned off without delay. Therefore, also at this time, the through current is suppressed.

  Details and further improvements of the technology disclosed in this specification will be described in the following “DETAILED DESCRIPTION”.

It is a circuit diagram of the output circuit of an Example. It is a timing chart figure of each part of an output circuit.

  The output circuit of the embodiment will be described with reference to the drawings. FIG. 1 shows a circuit diagram of the output circuit 2. The output circuit 2 is a circuit that converts a voltage level and outputs a pulse signal (input pulse signal) input between the input terminal 26 and the ground terminal 28. In the circuit of FIG. 1, the output pulse signal is an inverted signal of the input pulse signal. In order to output a non-inverted signal, an inverter element may be added to the input terminal 26 or the output terminal 27.

  The output circuit 2 includes three transistors 21-23, a resistance element 24, a power supply 25, an input terminal 26, an output terminal 27, and a ground terminal 28. All of the three transistors 21-23 are N-channel type voltage driven elements. More specifically, the three transistors 21-23 are N-channel MOS transistors (Metal-Oxide-Semiconductor Transistors). The threshold voltage at which the n-channel MOS transistor switches from off to on is represented by the symbol “Vth”. For convenience of explanation, the three transistors are referred to as a first transistor 21, a second transistor 22, and a third transistor.

  The first transistor 21 and the second transistor 22 are connected in series between the power supply 25 and the ground terminal 28. The high-potential side transistor connected in series is the first transistor 21, and the low-potential side transistor is the second transistor 22. An output terminal 27 is connected to the midpoint of the series connection of the first transistor 21 and the second transistor 22. In the case of a circuit having the output point at the midpoint of the series connection of two switching elements, a connection called a complementary type in which a P-channel type switching element is arranged on the high potential side and an N-channel type switching element is arranged on the low potential side Is normal. However, the output circuit 2 of this embodiment is characterized in that both of them employ N-channel type switching elements (transistors). As will be described in detail later, a mechanism for suppressing the through current can be easily configured by adopting both N-channel switching elements.

  The resistance element 24 has one end connected to the power supply 25 and the other end connected to the gate of the first transistor 21. For convenience of explanation, the gate of the first transistor 21 may be referred to as a first gate G1 below. In addition, the source of the first transistor 21 may be referred to as a first source S1.

In FIG. 1, a capacitor 29 is connected between the first gate G1 and the first source S1. The capacitor 29 is not a single element but a parasitic capacitance of the first transistor 21. In order to represent the parasitic capacitance, the capacitor 29 is drawn by a broken line in FIG. Represents the capacitance of the capacitor 29 by the symbol _{C L,} represents the resistance value of the resistance element 24 by the symbol _{R L.} There are parasitic capacitances in the second transistor 22 and the third transistor 23, but they are ignored in this embodiment.

The resistance element 24 and the capacitor 29 constitute a low-pass filter between the power supply 25 and the first gate G1. The time constant is represented by R _L · C _L. In the output circuit 2 of the embodiment, the resistance value R _L is selected so that the time constant (R _L · C _L ) of the low-pass filter is larger than the switching time constant of the second transistor 22. Since the parasitic capacitance _CL is determined by selecting the first transistor 21, there is no room for adjustment.

  The third transistor 23 is connected between the other end (that is, the first gate G1) of the resistance element 24 and the ground end 28. The drain of the third transistor 23 is connected to the other end of the resistance element 24, and the source is connected to the ground terminal 28.

  The gate of the second transistor 22 and the gate of the third transistor 23 are connected to the input terminal 26.

  As described above, the output circuit 2 has a very simple structure. The output circuit 2 can suppress a through current with a simple structure. “Through current” refers to a high potential end (ie, power supply 25) to a low potential end (ie, ground end) when each of two transistors (first transistor 21 and second transistor 22) connected in series is switched. 28) is a current that flows directly. Hereinafter, a mechanism capable of suppressing the through current as well as the operation of the output circuit 2 will be described.

  FIG. 2 is a timing chart of each part of the output circuit 2. The operation of the output circuit 2 will be described with reference to FIG. 2 together with FIG. A graph Gr1 in FIG. 2 is a timing chart of the input pulse signal VIN applied to the input terminal 26. The graph Gr2 is a timing chart of the second transistor 22 and the third transistor 23. The symbol Tr2 in FIG. 2 represents the second transistor 22, and the symbol Tr3 represents the third transistor 23. Since the gates of the second transistor 22 and the third transistor 23 are both connected to the input terminal 26, the second transistor 22 and the third transistor 23 operate in synchronization.

  A graph Gr3 is a timing chart of the voltage VG of the first gate G1 (the gate of the first transistor 21). The graph Gr4 is a timing chart of the first transistor 21. A symbol Tr <b> 1 in FIG. 2 represents the first transistor 21. A graph Gr5 is a timing chart of a signal (output pulse signal VOUT) output from the output terminal 27. The voltage level “LOW” in FIG. 2 corresponds to the potential of the ground terminal 28 in FIG. The voltage level of “HIGH_1” in FIG. 2 represents the HIGH level of the input pulse signal. The HIGH level (HIGH_1) of the input pulse signal is lower than the power supply voltage VH of the output circuit 2.

  In the timing chart of FIG. 2, the input pulse signal VIN switches from the LOW level to the HIGH_1 level at time T1, and switches from the HIGH_1 level to the LOW level at time T2. The input pulse signal VIN switches from the LOW level to the HIGH_1 level again at time T3, and switches from the HIGH_1 level to the LOW level at time T4.

  When the input pulse signal VIN is at the LOW level, that is, when the voltage at the input terminal 26 is at the LOW level, the second transistor 22 and the third transistor 23 are in the off state (see time T1 before the graph Gr2). The drain of the third transistor 23 is cut off from the source, and the voltage VG of the gate (first gate G1) of the first transistor 21 is pulled up to the power supply voltage VH. As a result, the first transistor 21 is turned on (see graphs Gr3 and G4 before time T1). As described above, since the threshold voltage of the first transistor 21 which is an n-channel MOS transistor is the voltage Vth, the voltage of the source (first source S1) of the first transistor 21 is the voltage (VH−Vth). And is held (refer to time before time T1 in graph Gr5). This voltage (VH−Vth) corresponds to the HIGH level of the output terminal 27. Hereinafter, the voltage (VH−Vth) is expressed as “voltage VHO”.

  The input pulse signal VIN, that is, the voltage at the input terminal 26 switches from the LOW level to the HIGH_1 level at time T1 (see time T1 in the graph Gr1). The gate voltages of the second transistor 22 and the third transistor 23 become HIGH_1, and the second transistor 22 and the third transistor 23 are switched from off to on (see graph Gr2). When the third transistor 23 is turned on, the gate (first gate G1) of the first transistor 21 is connected to the ground terminal 28, the voltage VG falls to the ground level (LOW level), and the first transistor 21 is turned off from on. Switch to.

  At the timing of time T1, the first transistor 21 switches from on to off without delay. This is due to the following reason. Only the third transistor 23 is connected between the gate (first gate G 1) of the first transistor 21 and the ground terminal 28. The impedance between the first gate G1 and the ground end 28 is dominated by the drain / source impedance of the third transistor 23. On the other hand, a load 3 is connected to the output end 27. The load 3 includes a device that operates with electric power supplied from the output terminal 27. Generally, the impedance of a device included in a load is larger than the impedance of one transistor (third transistor 23). Since the impedance between the first gate G1 and the ground terminal 28 is smaller than the impedance of the load 3 connected to the output terminal 27, that is, the drain of the second transistor 22, the voltage VG of the first gate G1 is quickly increased. At the fall, the first transistor 21 is quickly turned off. When the second transistor 22 and the third transistor 23 are switched from OFF to ON at the time T1, the first transistor 21 is switched from ON to OFF without delay, so that a through current (via the first transistor 21 and the second transistor 22). Current flowing directly from the power supply 25 to the ground terminal 28) does not increase.

At time T2, the input pulse signal VIN, that is, the voltage at the input terminal 26 is switched from the HIGH_1 level to the LOW level. The second transistor 22 and the third transistor 23 are switched from on to off. When the third transistor 23 is switched off, the gate (first gate G1) of the first transistor 21 is disconnected from the ground terminal 28. A current flows from the power source 25 into the first gate G <b> 1 through the resistance element 24. Here, as described above, the parasitic capacitance (capacitor 29) of the first transistor 21 and the resistance element 24 constitute a low-pass filter. The time constant (R _L · C _L ) is larger than the switching time constant of the second transistor 22. Accordingly, the gate voltage VG of the first transistor 21 rises more slowly than the switching speed of the second transistor 22. That is, the timing at which the first transistor 21 switches from off to on is delayed with respect to the timing at which the second transistor 22 switches from on to off. As a result, the through current is suppressed. The time difference indicated by the symbol dT in FIG. 2 represents this delay. In FIG. 2, the timing chart is drawn on the assumption that the switching speed of the second transistor 22 is infinite. The time delay (that is, the switching time constant) of switching from on to off depending on the switching speed of the second transistor 22 is smaller than the time constant (R _L · C _L ) of the low-pass filter described above.

  At time T2, the second transistor 22 is switched from on to off, and the first transistor 21 is switched from off to on. As a result, the output terminal 27 is disconnected from the ground terminal 28, and rises from the LOW level to the HIGH level (voltage VHO) (see graph Gr5, time T2).

  At time T3, the voltage of the input pulse signal VIN (that is, the input terminal 26) switches from the LOW level to the HIGH_1 level again, and at time T4, the voltage switches from the HIGH_1 level to the LOW level again. The operations at times T3 and T4 are the same as the operations at times T1 and T2, respectively.

As described above, the output circuit 2 of the embodiment can suppress the through current. The points are the following two points. One is that two transistors (first transistor 21 and second transistor 22) whose midpoints are connected to the output terminal 27 are connected in series and both N-channel switching elements are employed. . The other is that the middle point of the third transistor 23 and the resistor 24 connected in series to the power supply 25 and the ground terminal 28 are connected to the gate of the first transistor 21 (first gate G1). Here, the time constant (R _L · C _L ) of the low-pass filter formed by the resistance value R _L of the resistance element 24 and the parasitic capacitance C _L of the first transistor 21 is larger than the switching time constant of the second transistor 22. Thus, the resistance value _RL is selected. The output circuit 2 can suppress a through current with a simple configuration due to the above-described characteristics.

  Points to be noted regarding the technology described in the embodiments will be described. The circuit diagram of FIG. 1 shows a minimum configuration. Passive elements such as resistors and capacitors for noise removal may be added to the configuration of FIG.

  The output circuit 2 of the embodiment employs three N channel type MOS transistors. The switching element of the output circuit disclosed in this specification is not limited to a MOS transistor. The switching element of the output circuit may be an N channel type and voltage driven type element.

  The first transistor 21, the second transistor 22, and the third transistor 23 in the example correspond to an example of a first switching element, a second switching element, and a third switching element, respectively.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Output circuit 3: Load 21: First transistor 22: Second transistor 23: Third transistor 24: Resistive element 25: Power supply 26: Input terminal 27: Output terminal 28: Ground terminal 29: Capacitor G1: First gate S1 : First source R _L : Resistance value C _L : Parasitic capacitance

Claims (1)

Two n-channel first and second switching elements connected in series between a power source and a ground;
An output terminal connected to a midpoint of series connection of the first and second switching elements;
A resistance element having one end connected to the power supply and the other end connected to the gate of a first switching element that is a high-potential side switching element;
An n-channel third switching element connected between the other end of the resistance element and the ground;
An input terminal connected to the gate of the second switching element and the gate of the third switching element, which are low-potential side switching elements;
With
An output circuit, wherein a time constant of a low-pass filter including the parasitic capacitance of the first switching element and the resistance element is larger than a switching time constant of the second switching element.

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