CN102590629B - A kind of high precision electro migrates early warning circuit - Google Patents
A kind of high precision electro migrates early warning circuit Download PDFInfo
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- CN102590629B CN102590629B CN201210029638.9A CN201210029638A CN102590629B CN 102590629 B CN102590629 B CN 102590629B CN 201210029638 A CN201210029638 A CN 201210029638A CN 102590629 B CN102590629 B CN 102590629B
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Abstract
The invention discloses a kind of high precision electro migration early warning circuit, it includes interconnection line test structure, two-stage low gain amplifier, high-gain comparator and output stage, the output end of interconnection line test structure is connected with the input of two-stage low gain amplifier, the output end of two-stage low gain amplifier is connected with the input of high-gain comparator, and the output end of high-gain comparator is connected with output stage.
Description
Technical field
The present invention relates to early warning circuit, more particularly to a kind of electromigration early warning circuit.
Background technology
Constantly reduce in characteristic size, under integrated level and chip area and the ever-increasing background of actual power loss, physics
Approaching for the limit strengthens the various failure mechanism effect susceptibilitys of influence IC reliability, needs to examine in design and processes
Consider and the factor of balance is greatly increased, reliability tolerance limit tends to disappearing, so that integrity problem faces huge challenge.All
In multiple ic integrity problem, the electromigration of metal interconnecting wires is the one of the main reasons of ic failure, electromigration
Open circuit and the short circuit of plain conductor are easily caused, causes the resistance value of interconnection line to change.Constantly diminish in the size of device
In the case of, the width of plain conductor constantly reduces, and current density is continuously increased, therefore ELECTROMIGRATION PHENOMENON is to the danger of integrated circuit
Evil is continuously increased.In addition, with the raising of circuit level, interconnecting the shortening of linear dimension, the hot carrier urgency that highfield is produced
Increase severely plus, device bias standard operating conditions time seldom, so using the existing extrapolated forecasting method life-span increasingly without
Effect.And, the method in outside forecast life-span needs to carry out extremely complex emulation, and the iterative to the emulation of degenerative circuit makes this
The cycle for planting method for designing is longer.Therefore, the research to ELECTROMIGRATION PHENOMENON is increasingly paid attention to.
Electronic failure predict and health control (Electronic Prognostics and Health Management,
EPHM) technology is a kind of emerging based on the physics of failure, for predicting and assessment electronics product (or system) is in actual rings
The technology of the reliability in border.Compared with traditional fault diagnosis technology, it the failure of electronic system can as early as possible be monitored and
Identification, and possess the health of electronic system is managed, the ability that state is predicted.EPHM technologies are in chip and component
The fail-safe analysis of level has progress with life prediction aspect, and the various life-span prediction methods based on EPHM technologies have started to should
For chip and device level electronic product.Because the problem of cost, the EPHM technical research for single-chip are less, permitted in recent years
Many research institutions just have pointed out the thought of design early warning circuit.
The early warning chip of the specific failure mechanism design in circuit can in time send pre- before chip failure
Alert signal.Electromigration early warning circuit that can be integrated belongs to an important branch of EPHM technologies, and it is using the reliability prison in piece
Visual organ, can send alarm signal, so as to reduce the dependence to Reliability modeling when device degradation is to specified boundary, it is to avoid
The critical failure of system.Design error failure predicting unit carries out the health pipe of IC circuit-levels to Mishra et al. on the same chip earliest
Reason, its design realizes business application in Ridgetop groups, and early warning chip is applied to 0.35,0.25 and 0.18 μm of CMOS technology
Initial failure early warning.Wherein, Ridgetop groups in the U.S. report a kind of electromigration early warning circuit scheme (Patent No.：
US7271608 B1), the early warning circuit employs a resistance difference identical resistance bridge formula structure, and with " threshold value
The comparator of thresholding ".After resistance occurs electromigration, a voltage difference can be produced between electric bridge, when voltage difference reaches setting threshold
During value, comparator output overturns, and then realizes electromigration warning function.But early warning circuit requirement is distinguished using resistance
Identical resistance bridge formula structure, but in actual process, resistance value has a sizable fluctuation range, resistance big in itself
It is small to be difficult in precise control, therefore practical application；Also, " the threshold value thresholding " of comparator in the early warning circuit
Size be using Differential Input pipe or load pipe size it is asymmetric obtain, in actual process, its size is difficult to accurately
Control；Additionally, the threshold value of comparator is in fact the offset voltage being artificially introduced in the early warning circuit, and draw for technique
The unnecessary imbalance for entering, traditional offset canceling cannot be eliminated.
The content of the invention
In view of the shortcomings of the prior art, it is an object of the invention to provide a kind of high precision electro migration early warning circuit, Neng Gou
Plain conductor electromigration provides early warning signal exactly when occurring to a certain extent.
To achieve these goals, the technical scheme is that：A kind of high precision electro migrates early warning circuit, and it includes mutual
Line test structure, two-stage low gain amplifier, high-gain comparator and output stage, the output end of interconnection line test structure and two
The input of level low gain amplifier is connected, and the output end of two-stage low gain amplifier connects with the input of high-gain comparator
Connect, the output end of high-gain comparator is connected with output stage.
Preferably, the interconnection line test structure includes plain conductor 15, plain conductor 16, polysilicon resistance 17, polycrystalline
Silicon resistor 18, stress current source 11, test current source 12, the NMOS tube 19 of diode connected mode, switch 13, switch 14.Institute
State plain conductor 15, the length of plain conductor 16, width all same, the polysilicon resistance 17, the resistance of polysilicon resistance 18
The ratio between size is 1: 1.2；The plain conductor 15, plain conductor 16 are gone here and there after connecting with polysilicon resistance 17, polysilicon resistance 18
It is in parallel after connection；The test stress current source 11 is connected to the series connection intersection point of plain conductor 15, plain conductor 16 by switch 13
Place, the plain conductor 16 is connected to ground with the intersection point of polysilicon resistance 18 by switch 13；The diode connected mode
The drain terminal of NMOS tube 19 is connected to the point of intersection of plain conductor 16 and polysilicon resistance 18, source ground connection；The test current source 12
The point of intersection of plain conductor 15 and polysilicon resistance 17 is connected to by switch 14；From the plain conductor 15, plain conductor 16
Point of intersection and polysilicon resistance 17, the point of intersection of polysilicon resistance 18 draw the output signal of interconnecting test structure respectively.
Preferably, the first order of the two-stage low gain amplifier is defeated with two of interconnection line test structure by switch 25
Go out to be respectively connected with.The output of first order amplifier is connected by electric capacity 26 with the input of second level amplifier, and the second level is amplified
The output connection electric capacity 26 of device, the opposite side of electric capacity 26 is the output of two-stage low gain amplifier module.Two stage gain is put
Every one-level of big device has a common-mode voltage to be connected with amplifier in by switch 24.The output end of this module also has
Same common-mode voltage is connected by switch 24 with output end.The switch 24 being connected with common-mode voltage is simultaneously turned on or closed
It is disconnected.When switch 24 is turned on, and switch 25 is turned off, the module is in from error state is eliminated, and the offset voltage of comparator is amplified
After store electric capacity 26；When switch 25 is closed, and switch 24 disconnects, comparator is in and compares state, the difference of previous stage input
Sub-signal is stored onto electric capacity with the offset voltage and amplified of comparator, electric charge on the electric capacity that now offset voltage causes
The offset voltage electric charge that causes of the change just with storage on electric capacity when error state is eliminated offset, therefore offset voltage
It is eliminated.The input of high-gain comparator is connected with the output end of described two-stage low gain amplifier, High-gain compared with
The gain of device is very big, can further amplify the differential signal that prime is input into.Output stage is defeated with described high-gain comparator
Go out connected.Output stage by the output of high-gain comparator by shaping outputting standard data signal.
This circuit is operated in two states：Stress state, test mode.In stress state, stress current flows through metal to be led
Line 16, makes wire that electromigration to occur, while low gain comparator circuit is in from error state is eliminated, switch 42 disconnects, switch
41 conductings, final output is high potential；In test mode, switch 42 is turned on, and switch 41 disconnects, and test electric current flows through plain conductor
The network constituted with polysilicon resistance, now comparator two plain conductor intermediate voltage values of detection and polysilicon resistance centre are electric
The size of pressure value, if plain conductor 16 changes not less than 20% due to the resistance that electromigration causes, in two plain conductors
Between magnitude of voltage less than two polysilicon resistances intermediate voltage values, now the output end of output stage is low potential；If conversely, metal
Wire 16 changes more than 20% because of the resistance that electromigration causes, then final output is high potential.
Compared with prior art, present invention employs non-equal resistance bridge formula structure, its resistance is R and 1.2R, although
The absolute error of resistance is difficult to control in actual process, but relative error is preferably controlled, between obtaining two resistance
Precise ratios, thus easily realize in actual applications；With general " zero crossing " comparator, thus solve conventional art
In " threshold value thresholding " bad precise control and the indelible problem of offset voltage.The present invention is by setting accounting for for input clock
The empty resistance caused than adjustable stress time and the ratio of detection time, the change reflection plain conductor electromigration of its output signal
Whether change is more than 20%；Using from error comparator is eliminated, the detection of plain conductor change in resistance can be reached very high
Precision, precision is within 1%；Using relative resistance mode, it is achieved that application easy to spread in actual process.
Brief description of the drawings
The present invention is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 is structured flowchart of the invention；
Fig. 2 is structured flowchart of the present invention in stress state；
Fig. 3 is structured flowchart of the present invention in test mode；
Fig. 4 be when the electromigration of the present invention is not up to 20% and electromigration more than 20% when output signal with clock signal
Situation of change；
Fig. 5 is the circuit diagram of two-stage low gain amplifier of the present invention；
Fig. 6 is the circuit diagram of high-gain comparator of the present invention.
Specific embodiment
Fig. 1 is referred to, high precision electro migration early warning circuit of the invention is mainly made up of four parts：Interconnection line test structure
1st, two-stage low gain amplifier 2, high-gain comparator 3, output stage 4.Interconnection line test structure is by plain conductor 15, plain conductor
16th, polysilicon resistance 17, polysilicon resistance 18, stress current source 11, test current source 12, the NMOS tube of diode connected mode
19th, switch 13, switch 14.The plain conductor 15, the length of plain conductor 16, width all same are the polysilicon resistance 17, more
The ratio between resistance size of crystal silicon resistance 18 is 1: 1.2.Plain conductor 15, plain conductor 16 connect after with polysilicon resistance 17, many
Crystal silicon resistance 18 is in parallel after connecting.Test stress current source 11 is connected to plain conductor 15, plain conductor 16 by switch 13
Series connection point of intersection, plain conductor 16 is connected to ground with the intersection point of polysilicon resistance 18 by switch 13.Diode connected mode
The drain terminal of NMOS tube 19 is connected to the point of intersection of plain conductor 16 and polysilicon resistance 18, source ground connection.Test current source 12 passes through
Switch 14 is connected to the point of intersection of plain conductor 15 and polysilicon resistance 17.From plain conductor 15, the point of intersection of plain conductor 16
And the point of intersection of polysilicon resistance 17, polysilicon resistance 18 draws the output signal of interconnecting test structure respectively.The low increasing of two-stage
The first order of beneficial amplifier is respectively connected with by switch 25 with two outputs of interconnection line test structure；First order amplifier 21
Output be connected with the output of second level amplifier 22 by electric capacity 26, the output of second level amplifier 22 connection electric capacity 26, electricity
It is the output of two-stage low gain amplifier module to hold 26 opposite side.Every one-level of the two-stage gain amplifier has one altogether
Mode voltage is connected by switch 24 with amplifier 21, the input of amplifier 212, and this six switches are simultaneously turned off or turned on, because
This can regard a switch as, and Uniform Name is 24；The output end of this module also have same common-mode voltage pass through switch 42 with
Output end is connected.The switch being connected with common-mode voltage is simultaneously turned on or turned off.When switch 24 is turned on, and switch 25 is turned off, the mould
Block is in from error state is eliminated, and the offset voltage of amplifier is amplified to be stored in electric capacity 26；When switch 25 is closed, switch
During 24 disconnection, comparator is in and compares state, and the differential signal of previous stage input is offset voltage and amplified with comparator
After store on electric capacity, on the electric capacity that now offset voltage causes the change of electric charge just with from eliminate error state when electric capacity on
The electric charge that the offset voltage of storage causes is offseted, therefore offset voltage is eliminated, and exact value is output as only.High-gain compared with
Device is double-width grinding Single-end output structure, and the output valve of two-stage low gain amplifier is amplified into VDD or GND current potentials.Output
Level is made up of two phase inverters and two switches 41, switches 42, and when circuit is in stress state, switch 41 is turned on, switch 42
Shut-off, output is biased in high potential；When circuit is in test mode, switch 41 is turned off, and switch 42 is turned on, high-gain comparator
Output by it is anti-phase twice, enhancing after export.
Electromigration early warning circuit of the invention is in switch 13, switch 14, the control for switching 24, switch 25, switching 41, switch 42
It is divided into two kinds of working conditions under system.Fig. 2 is referred to, is closed in switch 13, switch 24, switch 41, switch 12, switch 25, switch
During 42 shut-off, circuit is in stress state.Now, the stress current that stress current source 11 produces flows through metal by switch 13 to be led
Line 16, then by switch 13 flow into ground, due to polysilicon resistance 17, polysilicon resistance 18 resistance much larger than plain conductor 15,
The resistance of plain conductor 16, therefore approximately stress current can all flow through plain conductor 16.In this case, high current flows through
Plain conductor 16, makes plain conductor 16 that electromigration to occur, and resistance slowly changes.Now two-stage low gain amplifier is in and misses
Difference elimination stage, the input of two-stage low gain amplifier accesses common-mode voltage, the amplified storage of offset voltage of amplifier
In the electric capacity 26 that amplifier is connected below.Turned in the switch 41 of output stage, 42 shut-offs, the input of output stage connects high potential
VDD, output stage is output as high potential VDD.
Fig. 3 is referred to, switch 14, switch 25, switch 42 are turned on when circuit is in test mode, switch 13, switch 24, open
41 are closed to turn off.The test electric current that now test current source 12 is produced flows through plain conductor 15, plain conductor 16, and polysilicon electricity
Resistance 17, polysilicon resistance 18.Due to the resistance of the resistance much larger than plain conductor of polysilicon resistance, therefore electricity can be approximately considered
Stream all flows through plain conductor 15, plain conductor 16.Because switch 13 is turned off, therefore electric current is by diode connected mode
NMOS tube 19 flows to ground, due to the presence of the NMOS tube 19 of diode connected mode, plain conductor 15, the intersection point of plain conductor 16
Place and polysilicon resistance 17, the common-mode voltage of the point of intersection of polysilicon resistance 18 are about VDD/2, in two-stage low gain ratio below
Within the scope of the common mode input of device.Imbalance electricity of the differential input signal of two-stage low gain amplifier with amplifier in itself
Pressure is amplified to be stored in the electric capacity 26 behind amplifier, wherein the offset voltage signal after amplifying amplifies with stress state
Offset voltage signal afterwards is offseted, so as to eliminate the influence of offset voltage.The differential mode that high-gain comparator will tentatively amplify
Signal further amplifies and for differential signal to be changed into single-end output signal, eventually passes the number that output signal is changed into output stage standard
Word output signal.
Fig. 4 is referred to, (a) therein is partly the signal waveforms of input clock, and circuit is in stress shape during high level
State, circuit is in test mode during low level；The change in resistance of b plain conductor 16 that () partly causes for electromigration is not up to
Output signal when 20% changes with time；When () partly causes the change in resistance of plain conductor 16 more than 20% for electromigration c
Output signal changes with time.
Fig. 5 is referred to, low gain amplifier includes 7 metal-oxide-semiconductors：(a) the 7th metal-oxide-semiconductor 57 be NMOS tube, its source ground,
Grid meets bias voltage BIAS；B () the 5th metal-oxide-semiconductor 55, the 6th metal-oxide-semiconductor 56 are NMOS tube, their source electrode with the 7th metal-oxide-semiconductor
57 drain electrode is connected, and grid is respectively two inputs IN+, IN- of the first or second low gain amplifier, and drain electrode is respectively
Two output ends OUT-, OUT+ of the first or second low gain amplifier；(c) first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd
Metal-oxide-semiconductor, the 4th metal-oxide-semiconductor are PMOS, and their source electrode is connected with power vd D；The grid of the first metal-oxide-semiconductor 51, drain electrode are short
Connect and the drain electrode with the second metal-oxide-semiconductor 52, the drain electrode of the grid and the 5th metal-oxide-semiconductor 55 of the 3rd metal-oxide-semiconductor 53 are connected；4th MOS
The grid of pipe 54, drain electrode short circuit, and drain electrode, the grid and the 6th metal-oxide-semiconductor 56 of the second metal-oxide-semiconductor 52 with the 3rd metal-oxide-semiconductor 53
Drain electrode be connected.The amplifier architecture that the embodiment is used is simple, and circuit symmetry is good, and gain stabilization, offset voltage is low.
Fig. 6 is referred to, high-gain comparator includes 11 metal-oxide-semiconductors：A () the 11st metal-oxide-semiconductor 611 is NMOS tube, its source electrode
Ground connection, grid meets bias voltage BIAS1；B () the 6th metal-oxide-semiconductor 606, the 7th metal-oxide-semiconductor 607 are NMOS tube, their source electrode and the
The drain electrode of 11 metal-oxide-semiconductors 611 is connected, and grid is respectively positive-negative input end VIN+, VIN- of amplifier；(c) first metal-oxide-semiconductor 601,
Second metal-oxide-semiconductor 602, the 3rd metal-oxide-semiconductor 603, the 4th metal-oxide-semiconductor 604 are PMOS, their source electrode with supply voltage VDD phases
Even.The grid of the second metal-oxide-semiconductor 602, drain electrode short circuit, and the drain electrode with the 6th metal-oxide-semiconductor 606 and the grid phase of the first metal-oxide-semiconductor 601
Even.The grid of the 3rd metal-oxide-semiconductor 603, drain electrode short circuit, and drain electrode, the grid phase of the 4th metal-oxide-semiconductor 604 with the 7th metal-oxide-semiconductor 607
Even；D () the 8th metal-oxide-semiconductor 608, the 9th metal-oxide-semiconductor 609 are NMOS tube, their source grounding.The grid of the 8th metal-oxide-semiconductor 608
Pole, drain electrode short circuit, and drain electrode with the first metal-oxide-semiconductor 601, the grid of the 9th metal-oxide-semiconductor 609 are connected.The leakage of the 9th metal-oxide-semiconductor 609
Pole is connected with the drain electrode of the 4th metal-oxide-semiconductor 604；E () the tenth metal-oxide-semiconductor 610 is NMOS tube, the leakage of its grid and the 4th metal-oxide-semiconductor 604
Pole, the drain electrode of the 9th metal-oxide-semiconductor 609 are connected, and the drain electrode of the tenth metal-oxide-semiconductor 610 is the output end OUT of high-gain comparator；(f) the 5th
Metal-oxide-semiconductor 605 is PMOS, and its source electrode meets supply voltage VDD, and grid meets bias voltage BIAS2, and drain electrode connects high-gain comparator
Output OUT.High-gain comparator can realize two functions：To the further amplification of signal；Differential signal is converted into single-ended letter
Number.
Claims (7)
1. a kind of high precision electro migrates early warning circuit, it is characterised in that it includes that interconnection line test structure, two-stage low gain amplify
Device, high-gain comparator and output stage, the output end of interconnection line test structure are connected with the input of two-stage low gain amplifier,
The output end of two-stage low gain amplifier is connected with the input of high-gain comparator, output end and the output of high-gain comparator
Level connection；The interconnection line test structure includes the first plain conductor (15), the second plain conductor (16), the first polysilicon resistance
(17), the second polysilicon resistance (18), stress current source (11), test current source (12), the NMOS tube of diode connected mode
(19), first switch (13), second switch (14)；Length, the width of the first plain conductor (15) and the second plain conductor (16)
The ratio between all same, the first polysilicon resistance (17), resistance size of the second polysilicon resistance (18) are 1：1.2；First metal is led
After being connected with the first polysilicon resistance (17), the second polysilicon resistance (18) after line (15), the second plain conductor (16) series connection simultaneously
Connection, stress current source (11) are connected to the string of the first plain conductor (15), the second plain conductor (16) by first switch (13)
Connection point of intersection, the second plain conductor (16) is connected to ground with the intersection point of the second polysilicon resistance (18) by first switch (13),
The drain terminal of the NMOS tube (19) of diode connected mode is connected to the friendship of the second plain conductor (16) and the second polysilicon resistance (18)
At point, source ground connection, test current source (12) is connected to the first plain conductor (15) and the first polycrystalline by second switch (14)
The point of intersection of silicon resistor (17), from the first plain conductor (15), the point of intersection of the second plain conductor (16) and the first polysilicon
Resistance (17), the point of intersection of the second polysilicon resistance (18) draw the output signal of interconnection line test structure respectively.
2. high precision electro according to claim 1 migrates early warning circuit, it is characterised in that the two-stage low gain amplifier
The first order by the 4th switch (25) be respectively connected with two output ends of interconnection line test structure；First order amplifier
Output end is connected by the first electric capacity (26) with the input of second level amplifier, the output end connection second of second level amplifier
Electric capacity (26), the opposite side of the second electric capacity (26) is the output of two-stage low gain amplifier；The two-stage low gain amplifier
A common-mode voltage is designed with per one-level by the 3rd switch (24) and first order amplifier (21), second level amplifier (22)
Input is connected, the output end of the two-stage low gain amplifier also have same common-mode voltage by the 3rd switch (24) with
Output end is connected, and the switch being connected with common-mode voltage is simultaneously turned on or turned off；When the 3rd switch (24) conducting, the 4th switch
(25) when turning off, the two-stage low gain amplifier is in from elimination error state, the amplified storage of offset voltage of comparator
To in electric capacity；When switch (25) closure, when switch (24) disconnects, high-gain comparator is in and compares state, previous stage input
Differential signal is stored onto electric capacity with the offset voltage and amplified of high-gain comparator.
3. high precision electro according to claim 1 migrates early warning circuit, it is characterised in that the high-gain comparator is double
End input Single-end output structure, VDD or GND current potentials are amplified to by the output valve of two-stage low gain amplifier.
4. high precision electro according to claim 1 migrates early warning circuit, it is characterised in that the output stage is main by two
Phase inverter and two the 5th switches (41), the 6th switches (42) are constituted, and when circuit is in stress state, the 5th switch (41) is led
Logical, the 6th switch (42) shut-off, output is biased in high potential；When circuit is in test mode, the 5th switch (41) is turned off, the
Six switch (42) conductings, the output of high-gain comparator is exported after anti-phase twice, enhancing.
5. high precision electro according to claim 4 migrates early warning circuit, it is characterised in that it can be operated in by clock control
Stress state or test mode；In stress state, stress current flows through the second plain conductor (16), makes the second plain conductor (16)
Generation electromigration, while two-stage low gain amplifier circuit is in from error state is eliminated, now the 6th switch (42) disconnects, the
Five switch (41) conductings, final output is high potential；In test mode, the 6th switch (42) conducting, the 5th switch (41) disconnects,
Test electric current flows through the network of plain conductor and polysilicon resistance composition, comparator detect two plain conductor intermediate voltage values with
The size of polysilicon resistance intermediate voltage value, if due to the second plain conductor (16) because the resistance change that electromigration causes does not surpass
20% is crossed, then two intermediate voltage values of plain conductor are less than two intermediate voltage values of polysilicon resistance, now output stage
Output end is output as low potential, if conversely, the resistance that the second plain conductor (16) causes by electromigration changes more than 20%,
Final output is high potential.
6. high precision electro according to claim 1 migrates early warning circuit, it is characterised in that the two-stage low gain amplifier
Every first stage amplifier include 7 metal-oxide-semiconductors；7th metal-oxide-semiconductor (57) is NMOS tube, and its source ground, grid connects bias voltage
BIAS；5th metal-oxide-semiconductor (55), the 6th metal-oxide-semiconductor (56) are NMOS tube, their source electrode with the drain electrode phase of the 7th metal-oxide-semiconductor (57)
Even, grid is respectively two inputs IN+, IN- of the first or second low gain amplifier, and drain electrode is respectively first or the
Two output ends OUT-, OUT+ of two low gain amplifiers；First metal-oxide-semiconductor (51), the second metal-oxide-semiconductor (52), the 3rd metal-oxide-semiconductor
(53), the 4th metal-oxide-semiconductor (54) is PMOS, and their source electrode is connected with power vd D；The grid of the first metal-oxide-semiconductor (51), leakage
It is extremely short connect and the drain electrode with the second metal-oxide-semiconductor (52), the grid of the 3rd metal-oxide-semiconductor (53) and the 5th metal-oxide-semiconductor (55) drain electrode phase
Even；The grid of the 4th metal-oxide-semiconductor (54), drain electrode short circuit, and drain electrode, the grid of the second metal-oxide-semiconductor (52) with the 3rd metal-oxide-semiconductor (53)
And the 6th metal-oxide-semiconductor (56) drain electrode be connected.
7. high precision electro according to claim 1 migrates early warning circuit, it is characterised in that the high-gain comparator includes
11 metal-oxide-semiconductors；11st metal-oxide-semiconductor (611) is NMOS tube, and its source ground, grid meets bias voltage BIAS1；6th metal-oxide-semiconductor
(606), the 7th metal-oxide-semiconductor (607) is NMOS tube, and their source electrode is connected with the drain electrode of the 11st metal-oxide-semiconductor (611), grid difference
It is positive-negative input end VIN+, VIN- of amplifier；First metal-oxide-semiconductor (601), the second metal-oxide-semiconductor (602), the 3rd metal-oxide-semiconductor (603),
Four metal-oxide-semiconductors (604) are PMOS, and their source electrode is connected with supply voltage VDD；The grid of the second metal-oxide-semiconductor (602), leakage
It is extremely short to connect, and drain electrode with the 6th metal-oxide-semiconductor (606) and the grid of the first metal-oxide-semiconductor (601) be connected；3rd metal-oxide-semiconductor (603)
Grid, drain electrode short circuit, and drain electrode with the 7th metal-oxide-semiconductor (607), the grid of the 4th metal-oxide-semiconductor (604) be connected；8th metal-oxide-semiconductor
(608), the 9th metal-oxide-semiconductor (609) is NMOS tube, their source grounding；The grid of the 8th metal-oxide-semiconductor (608), drain electrode are short
Connect, and drain electrode with the first metal-oxide-semiconductor (601), the grid of the 9th metal-oxide-semiconductor (609) are connected, the drain electrode of the 9th metal-oxide-semiconductor (609) with
The drain electrode of the 4th metal-oxide-semiconductor (604) is connected；Tenth metal-oxide-semiconductor (610) is NMOS tube, the leakage of its grid and the 4th metal-oxide-semiconductor (604)
Pole, the drain electrode of the 9th metal-oxide-semiconductor (609) are connected；The drain electrode of the tenth metal-oxide-semiconductor (610) is the output end OUT of high-gain comparator；The
Five metal-oxide-semiconductors (605) are PMOS, and its source electrode meets supply voltage VDD, and grid meets bias voltage BIAS2, and drain electrode connects amplifier
Output OUT.
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| CN201210029638.9A CN102590629B (en) | 2012-02-10 | 2012-02-10 | A kind of high precision electro migrates early warning circuit |
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| CN201210029638.9A CN102590629B (en) | 2012-02-10 | 2012-02-10 | A kind of high precision electro migrates early warning circuit |
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| CN102590629B true CN102590629B (en) | 2017-06-06 |
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| US10732216B2 (en) | 2012-10-30 | 2020-08-04 | Fifth Electronics Research Institute Of Ministry Of Industry And Information Technology | Method and device of remaining life prediction for electromigration failure |
| CN102955121B (en) | 2012-10-30 | 2014-11-19 | 工业和信息化部电子第五研究所 | Residual life predication method and device for electromigration failure |
| CN103033740B (en) | 2012-12-20 | 2015-08-26 | 工业和信息化部电子第五研究所 | The electromigration early warning circuit of integrated circuit |
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Address after: No. 78, Zhucun Avenue West, Zhucun street, Zengcheng District, Guangzhou, Guangdong 511300 Patentee after: CHINA ELECTRONIC PRODUCT RELIABILITY AND ENVIRONMENTAL TESTING Research Institute (THE FIFTH ELECTRONIC Research Institute OF MIIT)(CEPREI LABORATORY)) Address before: 510610 No. 110 Zhuang Road, Tianhe District, Guangdong, Guangzhou, Dongguan Patentee before: Fifth Electronics Research Institute of Ministry of Industry and Information Technology |