CN103217615A - Output short-circuit detection circuit - Google Patents
Output short-circuit detection circuit Download PDFInfo
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- CN103217615A CN103217615A CN2013101007874A CN201310100787A CN103217615A CN 103217615 A CN103217615 A CN 103217615A CN 2013101007874 A CN2013101007874 A CN 2013101007874A CN 201310100787 A CN201310100787 A CN 201310100787A CN 103217615 A CN103217615 A CN 103217615A
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- nmos pipe
- pipe
- drain electrode
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- detection
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Abstract
The invention discloses an output short-circuit detection circuit in the field of an integrated circuit, which comprises a detection module and a comparison module. The detection module is formed by connecting a detection resistor R1, a third NMOS (N-channel metal oxide semiconductor) pipe N3 and a feedback resistor R2 in series, wherein the detection resistor R1 and the third NMOS pipe N3 are connected with a power supply end VDD (Voltage Drain Drain) and the feedback resistor R2 is connected with a source electrode of a first NMOS pipe N1; a source electrode of the third NMOS pipe N3 is connected with the feedback resistor R2; a drain electrode of the third NMOS pipe N3 is connected with the detection resistor R1; the comparison module is connected with the drain electrode of the third NMOS pipe N3 and receives a detection signal Vsen output by the detection module; the comparison module also receives a reference voltage signal Vref; and when the potential of the detection signal Vsen is lower than that of the reference volage signal Vref, the comparison module outputs a high-level indicating signal Vsc. The output short-circuit detection circuit has the technical effect that the output short-circuit detection circuit can carry out short-circuit detection on a driving circuit without generating detection failure when the driving circuit is in a saturation region driving mode.
Description
Technical field
The present invention relates to a kind of output short-circuit testing circuit of integrated circuit fields.
Background technology
As everyone knows, the driving circuit of driving power load, it is usually by a pull-up device, promptly a NMOS manages N1 and a pull-down, promptly the 2nd NMOS pipe N2 constitutes, and two driving elements need an output short-circuit testing circuit separately, burn device to prevent output short-circuit.Drive efficient for improving, pull-up device and pull-down often all adopt the lower NMOS pipe of internal resistance.The one NMOS pipe N1 is because its special circuit structure can be operated in two kinds of drive patterns of saturation region drive pattern and linear zone drive pattern.
For NMOS pipe N1, traditional short-circuit detecting circuit often causes detecting under its saturation region drive pattern and lost efficacy merely at designing under its linear zone drive pattern.Therefore, existing output short-circuit testing circuit more and more can not satisfy user's needs.
Summary of the invention
The objective of the invention is in order to overcome the deficiencies in the prior art, a kind of output short-circuit testing circuit is provided, it can not only carry out short-circuit detecting to driving circuit when driving circuit is in the linear zone drive pattern, can also carry out short-circuit detecting to driving circuit when driving circuit is in the saturation region drive pattern.
The technical scheme that realizes above-mentioned purpose is: a kind of output short-circuit testing circuit, comprise detection module and comparison module, be used for the output short-circuit of driving circuit is detected, this driving circuit meets the NMOS pipe N1 of power end VDD by drain electrode and the 2nd NMOS pipe N2 that source electrode meets earth terminal VSS is in series output drive output signal V
Drv
Described detection module is managed N3 by the detection resistance R 1, the 3rd NMOS that connect power end VDD, and the feedback resistance R2 that is connected with the source electrode of described NMOS pipe N1 is in series; The source electrode of described the 3rd NMOS pipe N3 meets described feedback resistance R2, and drain electrode connects described detection resistance R 1, and the grid of described the 3rd NMOS pipe N3 connects the grid of described NMOS pipe N1, draws gate voltage signal Vhs in the reception;
When described NMOS pipe N1 is in the saturation region drive pattern, described drive output signal V
DrvDividing potential drop on described feedback resistance R2 is feedback voltage signal V
De, described drive output signal V
DrvDividing potential drop on described detection resistance R 1 is detection signal V
Sen;
Described comparison module connects the drain electrode of described the 3rd NMOS pipe N3, receives described detection signal V
SenDescribed comparison module receives reference voltage signal V
RefAs described detection signal V
SenCurrent potential be lower than described reference voltage signal V
RefCurrent potential the time, the indicator signal V of described comparison module output high level
Sc
Further, described comparison module comprises: a PMOS pipe P1, the 2nd PMOS pipe P2, the 4th NMOS pipe N4, the 5th NMOS pipe N5, biasing resistor R3;
The termination power end VDD of described biasing resistor R3, the source electrode of the described PMOS pipe of another termination P1, the source electrode of described the 4th NMOS pipe N4 meets earth terminal VSS, and drain electrode connects the drain electrode of described PMOS pipe P1;
The source electrode of described the 2nd PMOS pipe P2 is connected with the drain electrode of described the 3rd NMOS pipe N3, receives described detection signal V
Sen, the source electrode of described the 5th NMOS pipe N5 meets earth terminal VSS, and drain electrode connects the drain electrode of described the 2nd PMOS pipe P2;
The grid of described the 4th NMOS pipe N4 is connected with the grid of described the 5th NMOS pipe N5, receives bias voltage V
Bias, the grid of described PMOS pipe P1 connects grid and the drain electrode of described the 2nd PMOS pipe P2, makes described PMOS pipe P1 and described the 2nd PMOS pipe P2 constitute the common grid differential pair of source electrode input, described biasing resistor R3 is gone up generate reference voltage signal V
Ref
As described detection signal V
SenCurrent potential be lower than described reference voltage signal V
RefCurrent potential the time, the indicator signal V of the drain electrode output high level of described the 4th NMOS pipe N4
Sc
Further, described comparison module also comprises capacitor C 1, one termination power end VDD of described capacitor C 1, the other end connects the grid of described PMOS pipe P1 simultaneously, the grid of described the 2nd PMOS pipe P2, and the drain electrode of described the 2nd PMOS pipe P2, the charging signals V of described capacitor C 1 by exporting by the drain electrode of described the 2nd PMOS pipe P2
ChCharge.
Owing to adopted a kind of technical scheme that drives the output short-circuit testing circuit of the present invention, promptly in detection module, increase by one and manage the technical scheme of the feedback resistance R2 that the N3 source electrode is connected with NMOS pipe N1 source electrode and the 3rd NMOS.Its technique effect of the present invention is: feedback resistance R2 plays local degenerative effect, and when described NMOS pipe N1 was in the saturation region drive pattern, described feedback resistance R2 went up and generates a feedback voltage signal V
DeDescribed feedback resistance R2 is gone up produce pressure drop, and then the gate source voltage of the 3rd NMOS pipe N3 is descended, prevented detection signal V
SenThe reduction of current potential, so a kind of output short-circuit testing circuit of the present invention, can not only when driving circuit is in the linear zone drive pattern, carry out short-circuit detecting, can also be when driving circuit is in the saturation region drive pattern carries out short-circuit detecting to driving circuit and do not take place to detect and lost efficacy driving circuit.
Description of drawings
Fig. 1 is the circuit diagram of the most preferred embodiment of a kind of output short-circuit testing circuit of the present invention.
Embodiment
See also Fig. 1, the present inventor be in order to understand technical scheme of the present invention better, below by embodiment particularly, and is described in detail in conjunction with the accompanying drawings:
As shown in Figure 1, in the present embodiment, be used for the driving circuit of driving power load in the integrated circuit, comprise the NMOS pipe N1 and the 2nd NMOS pipe N2 of mutual series connection.The drain electrode of the one NMOS pipe N1 meets power end VDD, and the drain electrode of the 2nd NMOS pipe N2 connects the source electrode of NMOS pipe N1, and the source electrode of the 2nd NMOS pipe N2 meets earth terminal VSS.Wherein NMOS pipe N1 is a pull-up device, and the 2nd NMOS pipe N2 is a pull-down, the drive output signal V of this driving circuit output
DrvExport with the driving power load from the source electrode of NMOS pipe N1 or the drain electrode of the 2nd NMOS pipe N2.
A kind of driving output short-circuit testing circuit of the present invention comprises detection module 101 and comparison module 102, wherein,
Detection module 101 is and pull-up device, i.e. NMOS pipe N1 parallel connection, comprise detection resistance R 1, the three NMOS pipe N3 and the feedback resistance R2 of series connection successively.An end that detects resistance R 1 connects power end VDD, detects the drain electrode of another termination the 3rd NMOS pipe N3 of resistance R 1.The source electrode of a termination the 3rd NMOS pipe N3 of feedback resistance R2, the other end of feedback resistance R2 connects the source electrode of NMOS pipe N1.
The grid of the 3rd NMOS pipe N3 connects the grid of NMOS pipe N1.
Comparison module 102 comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 4th NMOS pipe N4, the 5th NMOS pipe N5, biasing resistor R3, capacitor C 1.
The end of biasing resistor R3 connects power end VDD, and the other end connects the source electrode of PMOS pipe P1, and the drain electrode of the 4th NMOS pipe N4 connects the drain electrode of PMOS pipe P1, and the source electrode of the 4th NMOS pipe N4 connects earth terminal VSS.
The source electrode of the 2nd PMOS pipe P2 connects the drain electrode of the 3rd NMOS pipe N3, and the drain electrode of the 2nd PMOS pipe P2 connects the drain electrode of the 5th NMOS pipe N5, and the source electrode of the 5th NMOS pipe N5 meets earth terminal VSS.
One termination power end VDD of capacitor C 1, the other end connect the grid of PMOS pipe P1 simultaneously, the grid of the 2nd PMOS pipe P2, and the drain electrode of the 2nd PMOS pipe P2.
The input end of external control circuit (not shown) connects the drain electrode of PMOS pipe P1 or the drain electrode of the 4th NMOS pipe, receives the indicator signal V of PMOS pipe P1 output
Sc, the output terminal of described external control circuit connects the grid of NMOS pipe N1, and draws gate voltage signal Vhs in the grid output of NMOS pipe N1, controls the break-make of NMOS pipe N1.
Principle of work of the present invention is as follows:
The one NMOS pipe N1 and the 2nd NMOS pipe N2 are logical at the last control lower whorl conductance of gate voltage signal Vhs and drop-down gate voltage signal Vls that draws respectively, drive the source electrode of NMOS pipe N1 or the drain electrode output drive output signal V of the 2nd NMOS pipe N2
Drv, with driving power load (not shown).At drive output signal V
DrvEffect under, generate drive current in this power termination.At this moment, because the inductance effect of this power termination, drive current can not suddenly change.If the 2nd NMOS pipe N2 conducting, drive current come from the electric current that the source electrode of the 2nd NMOS pipe N2 flows to drain electrode fully, this moment, the absolute value of drive current reduced gradually.When NMOS pipe N1 conducting, because the coupling effect of parasitic diode between the drain electrode of the 2nd NMOS pipe N2 and substrate, drive current in this power termination is divided into two parts: a part still comes from the electric current that is flowed to drain electrode by the source electrode of the 2nd NMOS pipe N2, and this part electric current absolute value reduces gradually; The drain electrode that another part comes from NMOS pipe N1 flows to the electric current of source electrode, and this part electric current absolute value increases gradually.This moment drive output signal V
DrvCurrent potential than the low diode forward conduction voltage drop of the current potential of earth terminal VSS, therefore NMOS pipe N1 is in the saturation region drive pattern.When the absolute value that flows to the electric current of drain electrode when the source electrode by the 2nd NMOS pipe N2 was reduced to zero, drive current all came from the electric current that is flowed to source electrode by the drain electrode of NMOS pipe N1, the drive output signal V of this driving circuit output
DrvCurrent potential rise gradually, finally near the current potential of power end VDD, this moment, the one NMOS pipe N1 was in the linear zone drive pattern.
When NMOS pipe N1 is in the linear zone drive pattern, NMOS pipe N1 by on draw gate voltage signal Vhs to detect the 3rd NMOS pipe N3 whether conducting, drive output signal V simultaneously
DrvProduce a dividing potential drop on the resistance R 1 detecting, this dividing potential drop is and is used to detect the whether detection signal V of output short-circuit of driving circuit
Sen
The source electrode of the 2nd PMOS pipe P2 in the comparison module 102 is accepted this detection signal V
Sen, the source electrode of PMOS pipe P1 is accepted reference voltage signal V
Ref, because the 2nd PMOS holds the grid of P2 and the grid of PMOS pipe P1 to be connected, so comparison module 102 can pass through comparison reference voltage signal V
RefCurrent potential and detection signal V
SenCurrent potential, judge detection signal V
SenCurrent potential whether be lower than design threshold, and then judge drive output signal V
DrvCurrent potential whether be lower than threshold value.If drive output signal V output short-circuit appears, in driving circuit
DrvCurrent potential can be lower than design threshold, detection signal V correspondingly
SenCurrent potential be lower than reference voltage signal V
RefCurrent potential.When comparison module 102 detects detection signal V
SenThe absolute value of current potential be lower than reference voltage signal V
RefThe absolute value of current potential the time, from the indicator signal V of the drain electrode output of P1 drain electrode of PMOS pipe or the 4th NMOS pipe N4
ScBe high level, indication makes a low level signal of described external control circuit output, closes NMOS pipe N1.
When NMOS pipe N1 is operated in the linear zone drive pattern, the electric current that flows through the 3rd NMOS pipe N3 is mainly by the resistance decision that detects resistance R 1 and feedback resistance R2, the breadth length ratio of the 3rd NMOS pipe N3 can design enough greatly, makes the conducting resistance of the 3rd NMOS pipe N3 enough low, to guarantee detection signal V
SenCurrent potential accurately reflect drive output signal V
DrvCurrent potential.Detection signal V
SenCurrent potential and drive output signal V
DrvCurrent potential be the linear relation that increases.
When NMOS pipe N1 is operated in the saturation region drive pattern, the electric current that flows through the 3rd NMOS pipe N3 can be managed the electric current that the N1 drain electrode flows to source electrode from a NMOS by mirror image, and the electric current that promptly flows through the 3rd NMOS pipe N3 is proportional to the electric current that flows to source electrode from NMOS pipe N1 drain electrode.Because the breadth length ratio of the 3rd NMOS pipe N3 is bigger usually, the image current that flows through the 3rd NMOS pipe N3 can be far longer than the electric current that flows through the 3rd NMOS pipe N3 when NMOS pipe N1 is operated in the linear zone drive pattern.The electric current that flows through the 3rd NMOS pipe N3 can make detection signal V when electric current flows through detection resistance R 1
SenPresent the low level of not expecting.Yet feedback resistance R2 plays local degenerative effect, and the electric current that flows through feedback resistance R2 equals to flow through the electric current of the 3rd NMOS pipe N3, and makes feedback resistance R2 go up feedback voltage signal V of generation
DeIf it is excessive to flow through the electric current of feedback resistance R2, feedback resistance R2 goes up the pressure drop that produces, and the gate source voltage of the 3rd NMOS pipe N3 is descended, thereby the image current that flows through the 3rd NMOS pipe N3 is significantly descended, and has prevented detection signal V
SenThe reduction of current potential.
Because the grid of the 2nd PMOS pipe P2 links to each other with the grid of PMOS pipe P1, the 2nd PMOS pipe P2 and PMOS pipe P1 constitute the common grid differential pair of source electrode input, receive detection signal V
SenWith reference voltage signal V
Ref, as detection signal V
SenCurrent potential when reducing, the charging signals V that capacitor C 1 is charged
ChCurrent potential decrease indicator signal V
ScCurrent potential increase.
The 5th NMOS pipe N5 and the 4th NMOS pipe N4 constitute the current source of two-way fixed proportion, and corresponding load as PMOS pipe P1 and the 2nd PMOS pipe P2 provides dc point and small-signal gain.Simultaneously, the electric current that flows through the 4th NMOS pipe N4 flows through biasing resistor R3 and produces reference voltage signal V
RefThat is to say that the 4th NMOS pipe N4 produces reference voltage signal V with biasing resistor R3 on the one hand
Ref, as the load of PMOS pipe P1, receive this reference voltage signal V on the other hand
RefCompare.Realized the function of relative complex with the structure of simplifying relatively.
As detection signal V
SenCurrent potential when reducing, the electric current of the 5th NMOS pipe N5 flows through capacitor C 1, and capacitor C 1 is charged, the current value of capacitor C 1 and capacitance have determined charging signals V
ChFall off rate.Capacitor C 1 can stop of short duration detection signal V
SenBe delivered on the 4th NMOS pipe N4, produce indicator signal V
ScOutput, optimize the total system response.
Below embodiment has been described in detail the present invention in conjunction with the accompanying drawings, and those of ordinary skills can make many variations to the present invention according to the above description.Thereby some details among the embodiment should not constitute limitation of the invention, and the scope that the present invention will define with appended claims is as protection scope of the present invention.
Claims (3)
1. output short-circuit testing circuit, comprise detection module (101) and comparison module (102), be used for the output short-circuit of driving circuit is detected, this driving circuit connects the NMOS pipe (N1) of power end (VDD) by drain electrode and the 2nd NMOS pipe (N2) that source electrode connects earth terminal (VSS) is in series, and exports drive output signal (V
Drv), it is characterized in that:
Described detection module (101) is managed (N3) by the detection resistance (R1), the 3rd NMOS that connect power end (VDD), and the feedback resistance (R2) that is connected with the source electrode of described NMOS pipe (N1) is in series; The source electrode of described the 3rd NMOS pipe (N3) connects described feedback resistance (R2), and drain electrode connects described detection resistance (R1), and the grid of described the 3rd NMOS pipe (N3) connects the grid of described NMOS pipe (N1), draws gate voltage signal (Vhs) in the reception;
When described NMOS pipe (N1) is in the saturation region drive pattern, described drive output signal (V
Drv) dividing potential drop on described feedback resistance (R2) is feedback voltage signal (V
De), described drive output signal (V
Drv) dividing potential drop on described detection resistance (R1) is detection signal (V
Sen);
Described comparison module (102) connects the drain electrode of described the 3rd NMOS pipe (N3), receives described detection signal (V
Sen); Described comparison module (102) receives reference voltage signal (V
Ref); As described detection signal (V
Sen) current potential be lower than described reference voltage signal (V
Ref) current potential the time, the indicator signal (V of described comparison module (102) output high level
Sc).
2. a kind of output short-circuit testing circuit according to claim 1 is characterized in that: described comparison module (102) comprising: PMOS pipe (P1), the 2nd PMOS pipe (P2), the 4th NMOS pipe (N4), the 5th NMOS manage (N5), biasing resistor (R3);
One termination power end (VDD) of described biasing resistor (R3), the source electrode of the described PMOS pipe of another termination (P1), the source electrode of described the 4th NMOS pipe (N4) connects earth terminal (VSS), and drain electrode connects the drain electrode of described PMOS pipe (P1);
The source electrode of described the 2nd PMOS pipe (P2) is connected with the drain electrode that described the 3rd NMOS manages (N3), receives described detection signal (V
Sen), the source electrode of described the 5th NMOS pipe (N5) connects earth terminal (VSS), and drain electrode connects the drain electrode of described the 2nd PMOS pipe (P2);
The grid of described the 4th NMOS pipe (N4) is connected with the grid that described the 5th NMOS manages (N5), receive bias voltage (Vbias), the grid of described PMOS pipe (P1) connects the grid and the drain electrode of described the 2nd PMOS pipe (P2), make described PMOS pipe (P1) and described the 2nd PMOS pipe (P2) constitute the common grid differential pair of source electrode input, described biasing resistor (R3) is gone up generated reference voltage signal (V
Ref);
As described detection signal (V
Sen) current potential be lower than described reference voltage signal (V
Ref) current potential the time, the indicator signal (V of the drain electrode output high level of described the 4th NMOS pipe (N4)
Sc).
3. a kind of output short-circuit testing circuit according to claim 2, it is characterized in that: described comparison module (102) also comprises electric capacity (C1), one termination power end (VDD) of described electric capacity (C1), the other end connects the grid of described PMOS pipe (P1) simultaneously, the grid of described the 2nd PMOS pipe (P2), and the drain electrode of described the 2nd PMOS pipe (P2), the charging signals (V of described electric capacity (C1) by exporting by the drain electrode of described the 2nd PMOS pipe (P2)
Ch) charge.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310100787.4A CN103217615B (en) | 2013-03-27 | 2013-03-27 | Output short-circuit detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310100787.4A CN103217615B (en) | 2013-03-27 | 2013-03-27 | Output short-circuit detection circuit |
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| CN103217615A true CN103217615A (en) | 2013-07-24 |
| CN103217615B CN103217615B (en) | 2015-03-25 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105572522A (en) * | 2014-10-09 | 2016-05-11 | 台达电子工业股份有限公司 | Grounding detection device and method thereof, relay operation detection device and method thereof |
| CN105891653A (en) * | 2015-02-16 | 2016-08-24 | 德尔福技术有限公司 | Electrical load controller with fault detection |
| CN107907777A (en) * | 2017-10-27 | 2018-04-13 | 广东美的厨房电器制造有限公司 | A kind of short-circuit detecting circuit and method, control circuit |
| CN111796976A (en) * | 2020-07-08 | 2020-10-20 | 湖南国科微电子股份有限公司 | Detection circuit of USB interface and port detection device |
| CN113759270A (en) * | 2021-09-07 | 2021-12-07 | 上海集成电路研发中心有限公司 | Power supply detection circuit and integrated circuit chip |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105572522A (en) * | 2014-10-09 | 2016-05-11 | 台达电子工业股份有限公司 | Grounding detection device and method thereof, relay operation detection device and method thereof |
| CN105572522B (en) * | 2014-10-09 | 2018-09-04 | 台达电子工业股份有限公司 | Ground detection device and its method, actuating of relay detection device and its method |
| CN105891653A (en) * | 2015-02-16 | 2016-08-24 | 德尔福技术有限公司 | Electrical load controller with fault detection |
| CN107907777A (en) * | 2017-10-27 | 2018-04-13 | 广东美的厨房电器制造有限公司 | A kind of short-circuit detecting circuit and method, control circuit |
| CN107907777B (en) * | 2017-10-27 | 2020-07-31 | 广东美的厨房电器制造有限公司 | Short circuit detection circuit and method and control circuit |
| CN111796976A (en) * | 2020-07-08 | 2020-10-20 | 湖南国科微电子股份有限公司 | Detection circuit of USB interface and port detection device |
| CN111796976B (en) * | 2020-07-08 | 2023-06-09 | 湖南国科微电子股份有限公司 | Detection circuit of USB interface and port detection device |
| CN113759270A (en) * | 2021-09-07 | 2021-12-07 | 上海集成电路研发中心有限公司 | Power supply detection circuit and integrated circuit chip |
| CN113759270B (en) * | 2021-09-07 | 2023-12-29 | 上海集成电路研发中心有限公司 | Power supply detection circuit and integrated circuit chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103217615B (en) | 2015-03-25 |
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