CN111796976A - Detection circuit of USB interface and port detection device - Google Patents
Detection circuit of USB interface and port detection device Download PDFInfo
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- CN111796976A CN111796976A CN202010651846.7A CN202010651846A CN111796976A CN 111796976 A CN111796976 A CN 111796976A CN 202010651846 A CN202010651846 A CN 202010651846A CN 111796976 A CN111796976 A CN 111796976A
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Abstract
The application discloses detection circuitry of USB interface, no matter detect USB2.0 interface through this detection circuitry, still detect USB3.0 interface, all can directly utilize a detection circuitry to come to detect host computer end and USB2.0 interface or the connection condition of host computer end and USB3.0 interface, and need not additionally to set up two detection circuitry and detect host computer end and USB2.0 interface or the connection condition of USB3.0 interface, just so can show the detection cost that reduces when detecting the USB interface. Correspondingly, the port detection device disclosed by the application also has the beneficial effects.
Description
Technical Field
The present invention relates to the field of port detection technologies, and in particular, to a detection circuit for a USB interface and a port detection apparatus.
Background
In practical applications, when the USB interface is used for data transmission, a detection circuit is usually required to detect whether the host end is connected to the USB interface, so as to perform subsequent data transmission. The process of detecting whether the USB interface is connected with the host end is called terminal detection, and a circuit for realizing the detection process is called a terminal detection circuit.
At present, the USB interfaces frequently used include a USB2.0 interface and a USBs3.0 interface, please refer to fig. 1 and fig. 2, fig. 1 is a structure diagram of a terminal characteristic of the USB2.0, and fig. 2 is a structure diagram of a terminal characteristic of the USB 3.0. As can be seen from comparing fig. 1 and fig. 2, the terminal characteristic structure of the USB2.0 can be equivalent to a resistor, so that it can be determined whether the output USB2.0 interface is connected to the host by detecting the voltage value at the detection point of the host, but since the capacitor in the terminal characteristic structure diagram of the USB3.0 has the function of isolating the dc voltage, the host cannot determine whether the USB3.0 interface is connected to the host by the dc voltage at the detection point. Therefore, in the prior art, two different detection circuits are usually used to detect the connection between the host and the USB2.0 interface and the USB3.0 interface. Obviously, such a detection method would greatly increase the design cost of the USB interface detection circuit. For this technical problem, no effective solution is available at present.
Therefore, how to reduce the detection cost when detecting the USB interface is a technical problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a detection circuit for USB interface and a port detection apparatus, so as to reduce the detection cost when detecting the USB interface. The specific scheme is as follows:
a detection circuit for a USB interface, comprising: the device comprises a first phase inverter, a second phase inverter, a third phase inverter, a first resistor, a first capacitor, a first transmission gate, a second transmission gate, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a bias voltage generating unit;
wherein, the input end of the first phase inverter is connected with the first switch tube interface of the first transmission gate, the output end of the first phase inverter is respectively connected with the second switch tube interface of the first transmission gate and the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is respectively connected with the first signal interface of the first transmission gate and the first end of the first capacitor, the second signal interface of the first transmission gate is connected with the first end of the first resistor, the second end of the first resistor is connected with VDD, the second end of the first capacitor is connected with the target USB interface, the first end of the first capacitor is further connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is respectively connected with the source electrode of the second PMOS tube and the drain electrode of the third PMOS tube, and the source electrode of the third PMOS tube is connected with VDD, the drain electrode of the first PMOS tube and the drain electrode of the second PMOS tube are respectively connected with the drain electrode of the second NMOS tube and the drain electrode of the third NMOS tube, the grid electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are respectively grounded, the drain electrode of the first PMOS tube is also connected with the grid electrode of the second NMOS tube, the drain electrode of the third NMOS tube is also connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the input end of the third phase inverter; the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, the source of the fourth PMOS transistor is connected to VDD, the drain of the fourth PMOS transistor is connected to the first end of the bias voltage generating unit, the second end of the bias voltage generating unit is grounded, the second end of the bias voltage generating unit is further connected to the first signal interface of the second transmission gate, the second signal interface of the second transmission gate is connected to the gate of the second PMOS transistor, the first switch transistor interface of the second transmission gate is configured to receive the output end signal of the third inverter, and the second switch transistor interface of the second transmission gate is configured to receive the input end signal of the third inverter.
Preferably, the first transmission gate and/or the second transmission gate is/are NMOS transmission gates.
Preferably, the first transmission gate and/or the second transmission gate are/is a CMOS transmission gate.
Preferably, the CMOS transmission gate includes a fourth NMOS transistor and a fifth PMOS transistor;
the source electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the fourth NMOS tube;
correspondingly, the gate of the fifth PMOS transistor is the first switch transistor interface of the CMOS transmission gate, the gate of the fourth NMOS transistor is the second switch transistor interface of the CMOS transmission gate, the source of the fifth PMOS transistor is the first signal interface of the CMOS transmission gate, and the drain of the fifth PMOS transistor is the second signal interface of the CMOS transmission gate.
Preferably, the resistance value of the first resistor is specifically kilo-ohm magnitude, and the capacitance value of the first capacitor is specifically picofarad magnitude.
Preferably, the bias voltage generating unit includes a second resistor, a third resistor, and a fourth resistor;
the second end of the second resistor is connected with the first end of the third resistor, and the second end of the third resistor is connected with the first end of the fourth resistor;
correspondingly, the first end of the second resistor is connected with the drain electrode of the fourth PMOS transistor, and the second end of the second resistor is connected with the second signal interface of the second transmission gate.
Preferably, the method further comprises the following steps: a third transmission gate;
the first signal interface of the third transmission gate is connected to the gate of the second PMOS transistor, the second signal interface of the third transmission gate is connected to the second end of the third resistor, the first switch transistor interface of the third transmission gate is configured to receive an input signal of the third inverter, and the second switch transistor interface of the third transmission gate is configured to receive an output signal of the third inverter.
Correspondingly, the invention also discloses a port detection device which comprises the detection circuit of the USB interface.
In the present invention, it can be seen that, when the target USB port needs to be detected, the input terminal of the first inverter is set to high level, and the time when the input terminal of the first inverter jumps from low level to high level is t0, when the lower pole plate of the first capacitor is connected with the USB2.0 port, the lower pole plate of the first capacitor is equivalent to a power supply path and is no longer in a floating state, the voltage of the upper pole plate of the first capacitor can be slowly increased under the action of the current flowing through the first resistor, when the voltage of the upper plate of the first capacitor rises to the bias voltage generated by the bias voltage generating unit, the drain voltage of the third NMOS transistor will rise, causing the output voltage of the third inverter to be pulled high, in this case, the time when the third inverter outputs high is marked as t1, and t1 and t0 must have a certain time interval. When the lower plate of the first capacitor is connected with the USB3.0 port, the lower plate of the first capacitor is equivalent to a series structure of a capacitor and a resistor, and the capacitance value of the first capacitor is much larger than the capacitance value of the first capacitor lower plate in series with the capacitor, so the lower plate of the first capacitor is directly equivalent to be connected to the ground through the resistor, in this case, the third inverter also outputs a high level, the time when the third inverter outputs the high level is marked as t1, and at this time, a certain time interval is provided between t1 and t 0. Therefore, no matter the lower plate of the first capacitor is connected with the USB2.0 port or the USB3.0 port, the time when the third inverter outputs high level and the time when the input end of the first inverter changes from low level to high level have a certain time interval, so that whether the host end is successfully connected with the USB2.0 port or the USB3.0 port can be judged by utilizing the attribute characteristic of the detection circuit. Obviously, in the detection circuit provided by the invention, when the USB2.0 port or the USB3.0 port is detected, the connection condition between the host end and the USB2.0 port or the USB3.0 port can be detected without arranging two detection circuits, so that the detection cost when the USB port is detected can be obviously reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a diagram of a terminal characteristic structure of USB 2.0;
FIG. 2 is a diagram of the structure of the terminal characteristics of USB 3.0;
fig. 3 is a structural diagram of a detection circuit of a USB interface according to an embodiment of the present invention;
fig. 4 is a structural diagram of another detection circuit of a USB interface according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 3, fig. 3 is a structural diagram of a detection circuit of a USB interface according to an embodiment of the present invention, where the detection circuit includes: the circuit comprises a first inverter INV1, a second inverter INV2, a third inverter INV3, a first resistor R1, a first capacitor C1, a first transmission gate G1, a second transmission gate G2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4 and a bias voltage generating unit;
wherein, the input end of the first inverter INV1 is connected to the first switch interface of the first transmission gate G1, the output end of the first inverter INV1 is connected to the second switch interface of the first transmission gate G1 and the gate of the first NMOS transistor N1, respectively, the source of the first NMOS transistor N1 is grounded, the drain of the first NMOS transistor N1 is connected to the first signal interface of the first transmission gate G1 and the first end of the first capacitor C1, respectively, the second signal interface of the first transmission gate G1 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to VDD, the second end of the first capacitor C1 is connected to the target USB interface, the first end of the first capacitor C1 is further connected to the gate of the first PMOS transistor P1, the source of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P5 and the drain of the third PMOS transistor P3, the source of the third PMOS transistor P3 is connected to the drain of the first PMOS transistor P1, the first PMOS transistor P599 and the drain of the second PMOS transistor N2 are connected to the drain of the second PMOS transistor N599, the grid electrode of the second NMOS tube N2 is connected with the grid electrode of the third NMOS tube N3, the source electrode of the second NMOS tube N2 and the source electrode of the third NMOS tube N3 are grounded respectively, the drain electrode of the first PMOS tube P1 is also connected with the grid electrode of the second NMOS tube N2, the drain electrode of the third NMOS tube N3 is also connected with the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected with the input end of the third inverter INV 3; the gate of the third PMOS transistor P3 is connected to the gate of the fourth PMOS transistor P4, the source of the fourth PMOS transistor P4 is connected to VDD, the drain of the fourth PMOS transistor P4 is connected to the first end of the bias voltage generation unit, the second end of the bias voltage generation unit is grounded, the second end of the bias voltage generation unit is further connected to the first signal interface of the second transmission gate G2, the second signal interface of the second transmission gate G2 is connected to the gate of the second PMOS transistor P2, the first switch interface of the second transmission gate G2 is configured to receive the output signal of the third inverter INV3, and the second switch interface of the second transmission gate G2 is configured to receive the input signal of the third inverter INV 3.
In this embodiment, a detection circuit for a USB interface is provided, by which the design cost of the detection circuit for the USB interface can be significantly reduced. In order to make the implementation principle of the detection circuit of the USB interface more clearly understood by those skilled in the art, the present embodiment specifically describes the operation principle of the detection circuit. Assuming that the input port of the first inverter is EN _ DET, when the detection circuit does not need to detect the USB interface, EN _ DET is low, the output node Vg1 of the first inverter INV1 is high, the first transfer gate G1 is in an off state, the gate of the first NMOS transistor N1 is high, and is in an on state, the voltage of the upper plate of the first capacitor C1 is connected to ground through the first NMOS transistor, and the voltage value is zero, at this time, the current flowing through the fourth PMOS transistor P4 is I1, and then I1 satisfies the following relation:
in the formula, Vgs is a gate-source voltage of the fourth PMOS transistor, and R is a resistance value of the bias voltage generating unit.
The third PMOS transistor P3 and the fourth PMOS transistor P4 have the same size and form a current mirror structure, in which case the current flowing through the third PMOS transistor P3 is equal to the current flowing through the fourth PMOS transistor P4. The second NMOS transistor N2 and the third NMOS transistor N3 have the same size, and at this time, the second NMOS transistor N2 and the third NMOS transistor N3 also form a current mirror structure. Since the first PMOS transistor P1 and the second NMOS transistor N2 are connected in series, the current flowing through the third NMOS transistor N3 is equal to the current flowing through the second NMOS transistor N2, which is also equal to the current flowing through the first PMOS transistor. Nodes TDN and TD are input and output terminals of the third inverter INV3, respectively, and therefore, level values of TDN and TD are opposite. Assuming that TDN is high, TD is low, the second transmission gate G2 is turned on, the third transmission gate G3 is turned off, and the gate of the second PMOS transistor P2 is connected to the node Vx 1. since the gate voltage of the first PMOS transistor P1 is zero, the conduction capability of the second PMOS transistor P2 is greater than that of the third PMOS transistor P3, and therefore, the current flowing through the second PMOS transistor P2 is greater than that flowing through the third PMOS transistor P3, so that the current flowing through the third NMOS transistor N3 is greater than that flowing through the second PMOS transistor P2. Since the third NMOS transistor N3 and the second PMOS transistor P2 are connected in series, but the current of the third NMOS transistor N3 is larger than the current of the second PMOS transistor P2, the drain voltage of the third NMOS transistor N3 is pulled down to ground, so that the current of the third NMOS transistor N3 is reduced to the same current as the second PMOS transistor P2. Since the drain voltage of the third NMOS transistor N3 is zero, TDN is maintained at a high level, and TD is maintained at a low level, when the detection circuit does not detect the target USB interface, the third inverter INV3 outputs a low level, that is, when EN _ DET is a low level, TD is a high level.
When the target USB port needs to be tested, the input end EN _ DET of the first inverter INV1 is set to high level, and assuming that the time when the input end of the first inverter INV1 jumps from low level to high level is t0, at this time, the first transmission gate G1 is turned on, the upper plate of the first capacitor C1 is charged by the current flowing through the first resistor R1, the lower plate of the first capacitor C1 is connected to the target USB interface, if the target USB interface is not connected, the lower plate of the first capacitor C1 is floated, the equivalent value of the first capacitor C1 is zero, the upper plate of the first capacitor C1 is pulled up to VDD instantaneously, so that the gate of the first PMOS transistor P1 also becomes VDD, and thus the output of the third inverter INV3 is also high level, and the time when the INV3 outputs high level is marked as t 1. It can be understood that when the lower plate of the first capacitor C1 is not connected to the target USB interface, the voltage of the upper plate of the first capacitor C1 is pulled high instantaneously, in which case the time difference between t1 and t0 is substantially zero.
When the lower plate of the first capacitor C1 is connected to the USB2.0 port, the lower plate of the first capacitor C1 is equivalent to a power supply path and is no longer in a floating state, and the upper plate of the first capacitor C1 is under the action of the current flowing through the first resistor R1, the voltage of the upper plate of the first capacitor C1 will rise slowly, and when the voltage of the upper plate of the first capacitor C1 rises to the bias voltage generated by the bias voltage generating unit, the drain voltage of the third NMOS transistor N3 will rise, so that the output terminal voltage of the third inverter INV3 will also be pulled high, in this case, the time when the third inverter INV3 outputs a high level is marked as t1, and at this time, a certain time interval must exist between t1 and t 0.
When the lower plate of the first capacitor C1 is connected to the USB3.0 port, because the lower plate of the first capacitor C1 is equivalent to a series structure of a capacitor and a resistor, and because the capacitance of the first capacitor C1 is much larger than the capacitance of the series capacitor of the lower plate of the first capacitor C1, the lower plate of the first capacitor C1 is directly equivalent to be connected to the ground through a resistor, in this case, the third inverter INV3 outputs a high level, and the time when the third inverter INV3 outputs a high level is marked as t1, at this time, a certain time interval must exist between t1 and t 0.
Therefore, no matter the lower plate of the first capacitor is connected with the USB2.0 port or the USB3.0 port, the time when the third inverter outputs high level and the time when the input end of the first inverter changes from low level to high level have a certain time interval, so that whether the host end is successfully connected with the USB2.0 port or the USB3.0 port can be judged by utilizing the attribute characteristic of the detection circuit. Obviously, in the detection circuit provided in this embodiment, when detecting a USB2.0 port or a USB3.0 port, the connection between the host and the USB2.0 port or the USB3.0 port can be detected without providing two detection circuits, so that the detection cost when detecting the USB port can be significantly reduced.
In this embodiment, it can be seen that, when the target USB port needs to be detected, the input terminal of the first inverter is set to high level, and the time when the input terminal of the first inverter jumps from low level to high level is t0, when the lower pole plate of the first capacitor is connected with the USB2.0 port, the lower pole plate of the first capacitor is equivalent to a power supply path and is no longer in a floating state, the voltage of the upper pole plate of the first capacitor can be slowly increased under the action of the current flowing through the first resistor, when the voltage of the upper plate of the first capacitor rises to the bias voltage generated by the bias voltage generating unit, the drain voltage of the third NMOS transistor will rise, causing the output voltage of the third inverter to be pulled high, in this case, the time when the third inverter outputs high is marked as t1, and t1 and t0 must have a certain time interval. When the lower plate of the first capacitor is connected with the USB3.0 port, the lower plate of the first capacitor is equivalent to a series structure of a capacitor and a resistor, and the capacitance value of the first capacitor is much larger than the capacitance value of the first capacitor lower plate in series with the capacitor, so the lower plate of the first capacitor is directly equivalent to be connected to the ground through the resistor, in this case, the third inverter also outputs a high level, the time when the third inverter outputs the high level is marked as t1, and at this time, a certain time interval is provided between t1 and t 0. Therefore, no matter the lower plate of the first capacitor is connected with the USB2.0 port or the USB3.0 port, the time when the third inverter outputs high level and the time when the input end of the first inverter changes from low level to high level have a certain time interval, so that whether the host end is successfully connected with the USB2.0 port or the USB3.0 port can be judged by utilizing the attribute characteristic of the detection circuit. Obviously, in the detection circuit provided in this embodiment, when detecting a USB2.0 port or a USB3.0 port, the connection between the host and the USB2.0 port or the USB3.0 port can be detected without providing two detection circuits, so that the detection cost when detecting the USB port can be significantly reduced.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the first transmission gate G1 and/or the second transmission gate G2 are/is specifically NMOS transmission gates.
In this embodiment, the first transmission gate G1 and/or the second transmission gate G2 are/is configured as NMOS transmission gates, and since the NMOS transmission gates have the advantages of simple design structure and low cost, when the first transmission gate G1 and/or the second transmission gate G2 are/is configured as NMOS transmission gates, the overall cost required by the detection circuit can be relatively reduced.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the first transmission gate G1 and/or the second transmission gate G2 are specifically CMOS transmission gates.
In practical applications, the first transmission gate G1 and/or the second transmission gate G2 may also be configured as a CMOS transmission gate, because the CMOS transmission gate has a very low on-resistance and a high off-resistance, and therefore, the safety and reliability of the detection circuit during use can be further improved by using the advantage of the CMOS transmission gate.
Referring to fig. 4, fig. 4 is a structural diagram of another detection circuit of a USB interface according to an embodiment of the present invention. As a preferred embodiment, the CMOS transmission gate includes a fourth NMOS transistor N4 and a fifth PMOS transistor P5;
the source electrode of the fifth PMOS tube P5 is connected with the drain electrode of the fourth NMOS tube N4, and the drain electrode of the fifth PMOS tube P5 is connected with the source electrode of the fourth NMOS tube N4;
correspondingly, the gate of the fifth PMOS transistor P5 is the first switch-transistor interface of the CMOS transmission gate, the gate of the fourth NMOS transistor N4 is the second switch-transistor interface of the CMOS transmission gate, the source of the fifth PMOS transistor P5 is the first signal interface of the CMOS transmission gate, and the drain of the fifth PMOS transistor P5 is the second signal interface of the CMOS transmission gate.
Specifically, in this embodiment, a specific setting manner of the CMOS transmission gate is provided, that is, the fifth PMOS transistor and the fourth NMOS transistor are used to form the CMOS transmission gate, and obviously, by such a setting manner, the implementability and feasibility of the CMOS transmission gate in the construction process can be ensured.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the resistance of the first resistor R1 is specifically in kilo-ohm order, and the capacitance of the first capacitor C1 is specifically in picofarad order.
Through a large number of practical operations, it is found that when the resistance value of the first resistor R1 is set to be in the kilo-ohm order and the capacitance value of the first capacitor C1 is set to be in the picofarad order, the time interval between the time t1 when the third inverter INV3 outputs the high level and the time t0 when the input end of the first inverter jumps from the low level to the high level is most obvious. Therefore, the technical method provided by the embodiment can relatively improve the overall usability of the detection circuit in the use process.
Specifically, in practical applications, the resistance of the first resistor R1 may be set to 100 kohms, and the capacitance of the first capacitor C1 may be set to 100 picofarads. At this time, when the lower plate of the first capacitor C1 is connected to the USB2.0 interface, the voltage of the upper plate of the first capacitor C1 will rise slowly under the action of the charging current, and when the voltage of the first capacitor C1 rises to Vx1, the time t1 when the third inverter INV3 outputs high level will satisfy the following relation, that is:
in the formula, I1 is the charging current of the first capacitor C1, C1 is the capacitance of the first capacitor C1, and K is a constant proportionality.
When R1 is 100K Ω, C1 is 100pF, Vx is 0.5VDD, and K is 0.5, t is1＝10us。
When the lower plate of the first capacitor C1 is connected to the USB3.0 interface, the lower plate of the first capacitor C1 is equivalent to the capacitor Ct of 100nF and the resistor Rt of 50 Ω, and at this time, when viewed from the upper plate of the first capacitor C1, the equivalent capacitor of the USB3.0 is a series structure of the capacitor Ct and the first capacitor C1, and since the capacitance value of the first capacitor C1 is much larger than that of the capacitor Ct, the capacitor Ct can be substantially ignored. Therefore, under the action of the charging current, the time t1 when the third inverter INV3 outputs the high level of the upper plate of the first capacitor C1 satisfies the following relation, that is:
likewise, t110 us. Obviously, the detection circuit can detect the USB2.0 interface or the USB3.0 interface by using the attribute feature, so that the detection cost for detecting the USB port can be significantly reduced. Of course, the values of the first resistor R1 and the first capacitor C1 may be adaptively adjusted according to actual situations, and are not described in detail herein.
Based on the above embodiments, the present embodiment further describes and optimizes the technical solution, please refer to fig. 4, and fig. 4 is a structural diagram of another detection circuit of a USB interface according to the embodiment of the present invention. As a preferred embodiment, the bias voltage generating unit includes a second resistor R2, a third resistor R3, and a fourth resistor R4;
the second end of the second resistor R2 is connected with the first end of the third resistor R3, and the second end of the third resistor R3 is connected with the first end of the fourth resistor R4;
correspondingly, a first end of the second resistor R2 is connected to the drain of the fourth PMOS transistor P4, and a second end of the second resistor R2 is connected to the second signal interface of the second transmission gate G2.
In the present embodiment, a specific arrangement of the bias voltage generating unit is provided, that is, the bias voltage generating unit is constructed by using the second resistor R2, the third resistor R3 and the fourth resistor R4, and it is conceivable that when the bias voltage generating unit is configured in such a structure, the difficulty of constructing the bias voltage generating unit can be further reduced.
Based on the above embodiments, the present embodiment further describes and optimizes the technical solution, please refer to fig. 4, and fig. 4 is a structural diagram of another detection circuit of a USB interface according to the embodiment of the present invention. As a preferred embodiment, the detection circuit of the USB interface further includes: a third transmission gate G3;
the first signal interface of the third transmission gate G3 is connected to the gate of the second PMOS transistor P2, the second signal interface of the third transmission gate G3 is connected to the second end of the third resistor R3, the first switch interface of the third transmission gate G3 is configured to receive the input signal of the third inverter INV3, and the second switch interface of the third transmission gate G3 is configured to receive the output signal of the third inverter INV 3.
It can be understood that when the voltage of the upper plate of the first capacitor C1 rises to Vx1, TDN jumps to low, TD jumps to high, the second transfer gate G2 is turned off, the third transfer gate G3 is turned on, and the gate voltage of the second PMOS transistor P2 is connected to Vx2, and Vx2 is smaller than Vx1, so that the gate voltage of the second PMOS transistor P2 is lower than the gate voltage of the first PMOS transistor P1, and therefore, the possibility of logic error due to noise interference can be avoided. Obviously, the technical scheme provided by the embodiment can further improve the overall reliability of the detection circuit in the use process.
Correspondingly, the embodiment of the invention also discloses a port detection device which comprises the detection circuit of the USB interface.
The port detection device disclosed by the embodiment of the invention has the beneficial effects of the detection circuit of the USB interface disclosed by the embodiment of the invention.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above detailed description of the detection circuit of a USB interface and the port detection apparatus provided in the present invention is provided, and a specific example is applied in this document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A detection circuit for a USB interface, comprising: the device comprises a first phase inverter, a second phase inverter, a third phase inverter, a first resistor, a first capacitor, a first transmission gate, a second transmission gate, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a bias voltage generating unit;
wherein, the input end of the first phase inverter is connected with the first switch tube interface of the first transmission gate, the output end of the first phase inverter is respectively connected with the second switch tube interface of the first transmission gate and the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is respectively connected with the first signal interface of the first transmission gate and the first end of the first capacitor, the second signal interface of the first transmission gate is connected with the first end of the first resistor, the second end of the first resistor is connected with VDD, the second end of the first capacitor is connected with the target USB interface, the first end of the first capacitor is further connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is respectively connected with the source electrode of the second PMOS tube and the drain electrode of the third PMOS tube, and the source electrode of the third PMOS tube is connected with VDD, the drain electrode of the first PMOS tube and the drain electrode of the second PMOS tube are respectively connected with the drain electrode of the second NMOS tube and the drain electrode of the third NMOS tube, the grid electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are respectively grounded, the drain electrode of the first PMOS tube is also connected with the grid electrode of the second NMOS tube, the drain electrode of the third NMOS tube is also connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the input end of the third phase inverter; the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, the source of the fourth PMOS transistor is connected to VDD, the drain of the fourth PMOS transistor is connected to the first end of the bias voltage generating unit, the second end of the bias voltage generating unit is grounded, the second end of the bias voltage generating unit is further connected to the first signal interface of the second transmission gate, the second signal interface of the second transmission gate is connected to the gate of the second PMOS transistor, the first switch transistor interface of the second transmission gate is configured to receive the output end signal of the third inverter, and the second switch transistor interface of the second transmission gate is configured to receive the input end signal of the third inverter.
2. The detection circuit according to claim 1, wherein the first transmission gate and/or the second transmission gate is in particular an NMOS transmission gate.
3. The detection circuit according to claim 1, wherein the first and/or second transmission gate is in particular a CMOS transmission gate.
4. The detection circuit of claim 3, wherein the CMOS transmission gate comprises a fourth NMOS transistor and a fifth PMOS transistor;
the source electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the fourth NMOS tube;
correspondingly, the gate of the fifth PMOS transistor is the first switch transistor interface of the CMOS transmission gate, the gate of the fourth NMOS transistor is the second switch transistor interface of the CMOS transmission gate, the source of the fifth PMOS transistor is the first signal interface of the CMOS transmission gate, and the drain of the fifth PMOS transistor is the second signal interface of the CMOS transmission gate.
5. The detection circuit according to claim 1, wherein the resistance of the first resistor is in particular of the order of kilohms and the capacitance of the first capacitor is in particular of the order of picofarads.
6. The detection circuit according to any one of claims 1 to 5, wherein the bias voltage generation unit includes a second resistor, a third resistor, and a fourth resistor;
the second end of the second resistor is connected with the first end of the third resistor, and the second end of the third resistor is connected with the first end of the fourth resistor;
correspondingly, the first end of the second resistor is connected with the drain electrode of the fourth PMOS transistor, and the second end of the second resistor is connected with the second signal interface of the second transmission gate.
7. The detection circuit of claim 6, further comprising: a third transmission gate;
the first signal interface of the third transmission gate is connected to the gate of the second PMOS transistor, the second signal interface of the third transmission gate is connected to the second end of the third resistor, the first switch transistor interface of the third transmission gate is configured to receive an input signal of the third inverter, and the second switch transistor interface of the third transmission gate is configured to receive an output signal of the third inverter.
8. A port detection device comprising a detection circuit of a USB interface according to any one of claims 1 to 7.
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| CN202010651846.7A CN111796976B (en) | 2020-07-08 | 2020-07-08 | Detection circuit of USB interface and port detection device |
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| CN116028284A (en) * | 2022-08-18 | 2023-04-28 | 荣耀终端有限公司 | Electronic equipment |
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| CN111796976B (en) | 2023-06-09 |
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