JP2004080518A - Signal voltage detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal voltage detection circuit capable of preventing malfunctions due to power supply noise. <P>SOLUTION: The signal voltage detection circuit is provided with a differential amplifier having first and second driver transistors to which a reference voltage and a signal voltage to be detected are respectively inputted, a current mirror circuit for taking out an output current corresponding to the detection output of the differential amplifier, a current/voltage conversion circuit for converting the change of the output current of the current mirror circuit to a voltage and outputting it, a latch circuit where the output of the current/voltage conversion circuit is transferred and held, and a capacitive load element connected to the input node of the current/voltage conversion circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a differential amplifier for detecting an input signal voltage and a signal voltage detection circuit having a latch circuit for holding the detection result.
[0002]
[Prior art]
In a driver IC for driving a power switching element such as a MOS transistor or an IGBT (Insulated Gate Bipolar Transistor), for example, a signal voltage detection circuit for detecting an error or the like is used.
[0003]
FIG. 13 shows a configuration example of such a conventional signal voltage detection circuit 10. The differential amplifier 11 has driver transistor pairs N1 and N2 to which the reference voltage Vref and the signal voltage Vin to be detected are input. A current mirror circuit 12 is provided to extract an output current corresponding to the detection output of the differential amplifier 11. The change in the output current of the current mirror circuit 12 is detected by a current-voltage conversion circuit 13 including a resistor R1 and a transistor MN1 for detecting the terminal voltage of the resistor R1. The output of the current-voltage conversion circuit 13 is transferred to the latch circuit 14 via the inverter X1 and held.
[0004]
FIG. 14 is an operation timing chart of the signal voltage detection circuit 10. When the input signal voltage Vin becomes higher than the reference voltage Vref (t0), the collector current of the driver transistor N2 of the differential amplifier 11 switches from zero to a constant current. In response to the detection output of the differential amplifier 11, a drain current flows through the p-channel MOS transistors MP1 and MP2 constituting the current mirror circuit 12. Upon receiving the output current of the MOS transistor MP2, a voltage is generated across the resistor R1, and the n-channel MOS transistor MN1 is turned on. Therefore, the input level of the inverter X1 becomes L, an H pulse is input to the latch circuit 14, and the latch output of Vout = L is held.
Even if the signal voltage Vin falls below the reference voltage Vref (t1), the data held in the latch circuit 14 does not change. The data held in the latch circuit 14 is reset when the reset signal RST goes high (t2).
[0005]
FIG. 15 shows another signal voltage detection circuit 20. In this circuit, the differential amplifier 21 has an npn transistor N1 to which the reference voltage Vref is input, and npn transistors N21 and N22 provided together to which two signal voltages Vin1 and Vin2 are input. The loads on these driver transistors are active loads. That is, the load pnp transistors P1 and P2 constitute a current mirror circuit. The detection output of the differential amplifier 21 is amplified by the voltage amplifying unit 22 that operates with a large amplitude, transferred to the latch circuit 23 via the inverters X1 and X2, and held.
[0006]
FIG. 16 is an operation timing chart of the signal voltage detection circuit 20. When one of the input signal voltages Vin1 and Vin2 becomes higher than the reference voltage Vref (t0), the collector current of the corresponding driver transistor N21 or N22 of the differential amplifier 21 switches from zero to a constant current. In response to this change, the pnp transistor P3 turns on and a collector current flows, and an H pulse is obtained at the terminal of the resistor R1. As a result, the latch circuit 23 latches Vout = L.
Even if the signal voltage Vin falls below the reference voltage Vref (t1), the data held in the latch circuit 23 does not change. The data held in the latch circuit 23 is reset when the reset signal RST becomes H (t2).
[0007]
Both the signal voltage detection circuits 10 and 20 shown in FIGS. 13 and 15 may malfunction due to the influence of power supply noise. FIGS. 17 and 18 show timing charts when such malfunctions occur in the signal voltage detection circuits 10 and 20 of FIGS. 13 and 15, respectively.
[0008]
First, in the signal voltage detection circuit 10 of FIG. 13, it is assumed that the power supply voltage Vcc has dropped by a certain level ΔV at time t10 as shown in FIG. In response, the current of the current source I1 of the differential amplifier 11 also decreases. When the power supply voltage starts to recover at time t11, a displacement current flows through the large collector capacitance of the driver transistor N2, so that a drain current flows through the p-channel MOS transistors MP1 and MP2 of the current mirror circuit 12. When the terminal voltage of the resistor R1 rises due to the current of the MOS transistor MP2 and exceeds the threshold value of the NMOS transistor MN1, the MOS transistor MN1 is turned on, and Vout = L of the latch circuit 14 is latched.
[0009]
In the signal voltage detection circuit 20 of FIG. 15, as shown in FIG. 18, when the power supply voltage Vcc decreases by a certain level ΔV at time t10, the current of the current source I1 of the differential amplifier 21 also decreases. At the same time, of the pnp transistors P1 and P2 constituting the current mirror, the collector current of the transistor P1 through which a steady current flows is also reduced. When the power supply voltage returns from time t11, the collector current of one load transistor P1 returns to a steady current including a displacement current that charges the collector capacitance of driver transistor N1. In the other load transistor P2, a collector current flows as a displacement current for charging the large collector capacitance of the driver transistors N21 and N22, whereby the base current of the transistor P3 is extracted. In response to this, an H pulse is generated at the terminal of the resistor R1 and supplied to the latch circuit 23, so that the latch circuit 23 latches Vout = L.
[0010]
[Problems to be solved by the invention]
As described above, the signal voltage detection circuit in FIG. 13 or FIG. 15 may malfunction due to power supply noise due to the collector capacitance of the driver transistor. The collector capacitance of the driver transistor has no effect on the normal signal detection operation. However, after the power supply voltage drops momentarily due to external noise or the like, when the power supply returns to the normal power supply voltage, the differential amplifier charges the collector capacitance according to the change in the power supply voltage even though there is no input. The flow of the displacement current causes a malfunction.
[0011]
More specifically, the circuit of FIG. 13 has a problem of imbalance of the parasitic capacitances associated with the drain sides of the p-channel MOS transistors MP1 and MP2 constituting the current mirror circuit 12. The drain of the MOS transistor MP1 has a large collector capacitance of the driver transistor N2, whereas the drain of the MOS transistor MP2 has a small parasitic capacitance. For this reason, the displacement current of the driver transistor N2 at the time of power return causes a malfunction.
[0012]
On the other hand, in the circuit of FIG. 15, there is a problem of the imbalance of the parasitic capacitances associated with the drain sides of the pnp transistors P1 and P2 constituting the current mirror load of the differential amplifier 21. That is, with respect to one driver transistor N1 to which the reference voltage Vref is input, the signal voltage is input to the drain side of the load transistor P1 because the two driver transistors N21 and N22 are provided in parallel. The parasitic capacitance associated with the drain side of the load transistor P2 is larger than the parasitic capacitance. Therefore, when the power supply voltage is restored, the total displacement current flowing through the other driver transistors N21 and N22 is larger than the displacement current flowing through the other driver transistor N1, that is, the differential amplifier 21 detects the input signal. Such an operation causes a malfunction.
[0013]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal voltage detection circuit capable of preventing malfunction due to power supply noise.
[0014]
[Means for Solving the Problems]
A signal voltage detection circuit according to the present invention includes a differential amplifier having first and second driver transistors to which a reference voltage and a signal voltage to be detected are respectively input, and an output corresponding to a detection output of the differential amplifier. A current mirror circuit for extracting a current, a current-voltage conversion circuit for converting a change in an output current of the current mirror circuit into a voltage and outputting the voltage, and a latch circuit for transferring and holding an output of the current-voltage conversion circuit. , And a capacitive load element connected to an input node of the current-voltage conversion circuit.
[0015]
According to the present invention, by connecting the capacitive load element to the input node of the current-voltage conversion circuit, a malfunction caused by a displacement current flowing in the driver transistor of the differential amplifier when power supply noise occurs is prevented.
[0016]
The first and second driver transistors of the differential amplifier are constituted by, for example, bipolar transistors whose emitters are commonly connected to a current source. In this case, the capacitive load element has the same structure and dimensions as the driver transistor used in the differential amplifier, and can be constituted by a bipolar transistor whose base and emitter are connected in common. Alternatively, the capacitive load element can be constituted by a capacitor having a capacitance substantially equal to the collector capacitance of the driver transistor of the differential amplifier.
[0017]
The first and second driver transistors of the differential amplifier may be constituted by MOS transistors whose sources are commonly connected to a current source. In this case, the capacitive load element has the same structure and dimensions as the driver transistor used in the differential amplifier, and can be constituted by a MOS transistor having a gate and a source commonly connected.
In the case where the differential amplifier has n (n ≧ 2) second driver transistors provided to which different signal voltages are input, the capacitive load element is a driver transistor used in the differential amplifier. And n transistors connected in parallel having the same structure and dimensions.
[0018]
The signal voltage detection circuit according to the present invention is further provided with a first driver transistor connected to a first output node to which a reference voltage is input, and a signal voltage to be detected which is connected in parallel to a second output node and is different from each other. (N ≧ 2) of second driver transistors to which the first load transistor is connected between the first output node and the power supply terminal, and a current mirror with the first load transistor A differential amplifier having a second load transistor connected between the second output node and a power supply terminal, and a latch for transferring and holding a detection output of a second output node of the differential amplifier And a capacitive load element connected to a first output node of the differential amplifier.
[0019]
According to the present invention, the capacitive load element balances the capacitance of the two output nodes of the differential amplifier, thereby preventing a malfunction caused by a displacement current flowing through the driver transistor of the differential amplifier when power supply noise occurs. Is done.
[0020]
When the first and second driver transistors of the differential amplifier are bipolar transistors whose emitters are commonly connected to a current source, the capacitive load element has the same structure as the driver transistor used in the differential amplifier. It can be composed of (n-1) bipolar transistors which have dimensions and are commonly connected to the base and the emitter and connected in parallel. Alternatively, the capacitive load element may be constituted by a capacitor having a capacitance substantially equal to the collector capacitance of (n-1) driver transistors of the differential amplifier.
[0021]
When the first and second driver transistors of the differential amplifier are MOS transistors whose sources are commonly connected to a current source, the capacitive load element is the same as the driver transistor used in the differential amplifier. It has a structure and dimensions, and can be constituted by (n-1) MOS transistors connected in parallel with their gates and sources connected in common.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Embodiment 1]
FIG. 1 shows a signal voltage detection circuit 10a according to an embodiment of the present invention, in which the signal voltage generation circuit 10 of FIG. 13 is improved. The differential amplifier 11 has a pair of npn driver transistors N1 and N2 whose emitters are commonly connected to a current source I1. The transistor N1 has a base to which the reference voltage Vref is input and a collector connected to the power supply Vcc. The other transistor N2 has a base to which a signal voltage Vin to be detected is input, and a collector connected to a power supply Vcc via a p-channel MOS transistor MP1.
[0023]
The gate and the drain of the p-channel MOS transistor MP1 are connected. The MOS transistor MP1 and a p-channel MOS transistor MP2 having a gate connected to the MOS transistor MP1 constitute a current mirror circuit 12 for extracting a detection output of the differential amplifier 11 as a current.
[0024]
As a current-voltage conversion circuit 13 for converting the output current of the current mirror circuit 12 into a voltage, a resistor R1 connected between the drain of the MOS transistor MP2 and the ground Vss, and a gate connected to a node Nb of the resistor R1. It has an n-channel MOS transistor for sensing MN1. The current source I2 is connected to the drain of the MOS transistor MN1. The change in the drain voltage of the MOS transistor MN1, which is the detection output of the current-voltage conversion circuit 13, is transferred to the latch circuit 14 via the inverter X1. The latch circuit 14 includes NOR gates G1 and G2.
[0025]
In the signal voltage detection circuit 10a of this embodiment, unlike the conventional circuit of FIG. 13, the capacitive load element 15 is connected to the output node Nb of the current mirror circuit 12 (therefore, the input node of the current-voltage conversion circuit 13). Have been. The capacitive load element 15 balances the parasitic capacitances of the drain nodes Na and Nb of the MOS transistors MP1 and MP2 of the current mirror circuit 12 so as to be substantially equal. When the dimensions of the MOS transistors MP1 and MP2 are the same, an npn transistor N3 having the same structure and dimensions as the driver transistors N1 and N2 of the differential amplifier 11 is used as the capacitive load element 15. The transistor N3 has a base and an emitter connected to Vss, and a collector connected to the node Nb. As a result, the transistor N3 is kept off, and the collector capacitance is added to the node Nb.
[0026]
The operation of the signal voltage detection circuit 10a is the same as that of the conventional example described with reference to FIG. When the signal voltage Vin exceeds the reference voltage Vref, this is detected by the differential amplifier 11, and an output current corresponding to the detected output is taken out by the current mirror circuit 12. When the output current flows to the resistor R1 and the voltage of the node Nb exceeds the threshold value of the MOS transistor MN1, the MOS transistor MN1 turns on. As a result, the H pulse is input to the latch circuit 14, and the latch circuit 14 holds the detection result of Vout = L.
[0027]
The manner in which a malfunction due to power supply noise is prevented by this embodiment will be described with reference to the timing chart of FIG. This timing chart corresponds to FIG. 17 of the conventional example. Assuming that power supply voltage Vcc has decreased by a certain level ΔV at time t10, the current of current source I1 of differential amplifier 11 also decreases accordingly. Then, when the power supply voltage starts to return at time 11, a drain current due to a displacement current that charges the parasitic capacitance of the nodes Na and Nb flows through the p-channel MOS transistors MP1 and MP2 of the current mirror circuit 12.
[0028]
The parasitic capacitances of the nodes Na and Nb are capacitances between the collectors and the grounds of the transistors N2 and N3, respectively, and are substantially equal. Therefore, the drain current of the MOS transistor MP2 is used for charging the collector capacitance of the transistor N3, and hardly flows through the resistor R1. As a result, the terminal voltage of the resistor R1 (the voltage of the node Nb) does not increase even when the power is restored. Even if the terminal voltage slightly rises, if it is equal to or lower than the threshold value of the MOS transistor MN1, the MOS transistor MN1 does not turn on and the drain current keeps Id = 0. Therefore, the input node of the inverter X1, which has been lowered due to the power supply voltage drop, returns to H when the power supply voltage returns at the time t12, and the inverter X1 cannot obtain the H pulse output. That is, the latch circuit 14 keeps the original Vout = H state upon power recovery, and does not erroneously hold Vout = L.
[0029]
[Embodiment 2]
FIG. 3 shows a signal voltage detection circuit 10b according to an embodiment in which the circuit of FIG. 1 is modified. The difference from FIG. 1 is that a capacitor C having a capacitance substantially equal to the collector capacitance of the driver transistor N2 is used as the capacitive load element 15. This similarly prevents malfunctions due to power supply noise.
[0030]
[Embodiment 3]
FIG. 4 shows a signal voltage detection circuit 10c according to another embodiment in which the circuit of FIG. 1 is modified. The differential amplifier 11 has driver transistors N21 and N22 provided in parallel to receive two input signal voltages Vin1 and Vin2. In this case, also as the capacitive load element 15, two npn transistors N31 and N32 having the same collector capacitance as the driver transistors N21 and N22 are provided at the node Nb. Thereby, malfunction due to power supply noise can be prevented.
More generally, when n driver transistors (n> 1) into which an input signal voltage is input are provided, n transistors having the same shape and dimensions as the driver transistors are provided as the capacitive load element 15 at the node Nb. The same effect can be obtained by adding them together.
[0031]
[Embodiment 4]
FIG. 5 shows a signal voltage detection circuit 20a according to another embodiment in which the signal voltage generation circuit 20 of FIG. 15 is improved. The differential amplifier 21 has a driver npn transistor N1 to which the reference voltage Vref is input, and two driver npn transistors N21 and N22 to which the signal voltages Vin1 and Vin2 are input. The emitters of these transistors are commonly connected to a current source I1.
[0032]
Collector node Nc of driver transistor N1 is connected to power supply Vcc via load pnp transistor P1, and collector nodes Na of driver transistors N21 and N22 are connected to power supply Vcc via load pnp transistor P2. The gates of the transistors P1 and P2 are commonly connected, and the gates thereof are connected to the node Nc to form a current mirror load.
[0033]
A voltage amplifying unit 22 is provided to extract a detection output from the node Na of the differential amplifier 21. The voltage amplifier 22 includes a pnp transistor P3 whose base is connected to the node Na and whose emitter is connected to Vcc, and a resistor R1 connected between its collector and the ground Vss. The latch circuit 23 receives an H pulse obtained at the node Nb of the resistor R1 at the time of signal detection via the inverters X1 and X2.
[0034]
In this embodiment, in order to maintain the capacitance balance between the nodes Nc and Na of the differential amplifier 21, an npn transistor N11 having the same structure and the same dimensions as the driver transistor N1 on the reference side is used as the capacitive load element 24 in parallel. Has been added. The base and the emitter of the transistor N11 are commonly connected to the current source I1, and the collector is connected to the node Nc. Therefore, the transistor N11 is kept off, and a capacitive load is added to the node Nc.
[0035]
The operation of this signal voltage generation circuit 20a is basically the same as that described with reference to FIG. When the signal voltage Vin exceeds the reference voltage Vref, this is detected by the differential amplifier 21. That is, the potential of the node Na decreases, and the base current flows to turn on the npn transistor P3, and the collector current flows. As a result, an H pulse is obtained at the node Nb, and the latch circuit 14 holds the detection result of Vout = L.
[0036]
The manner in which a malfunction due to power supply noise is prevented by this embodiment will be described with reference to the timing chart of FIG. This timing chart corresponds to FIG. 18 of the conventional example. Assuming that the power supply voltage Vcc has decreased by a certain level ΔV at time t10, the current of the current source I1 of the differential amplifier 21 also decreases and a steady current flows among the transistors P1 and P2 constituting the active load. The current of the transistor P1 is also reduced. Then, when the power supply voltage starts to be restored at time t11, a drain current due to a displacement current that charges the parasitic capacitance of the nodes Nc and Na flows through the transistors P1 and P2, respectively.
[0037]
The parasitic capacitances of the nodes Nc and Na are the capacitances between the collectors and the grounds of the transistors (N1, N11) and (N21, N22), respectively, and are substantially equal. Therefore, the drain current due to the displacement current flowing through the transistors P1 and P2 when the power supply voltage returns is almost equal, and the potential of the node Na does not change. Therefore, the transistor P3 does not turn on due to the base current being pulled out, and no current flows through the resistor R1. As a result, the inverters X1 and X2 do not output the H pulse when the power is restored, and the latch circuit 23 returns to the original Vout = H state.
[0038]
[Embodiment 5]
FIG. 7 shows a signal voltage detection circuit 20b according to an embodiment obtained by modifying the circuit of the embodiment shown in FIG. The differential amplifier 21 is different from FIG. 5 in that npn driver transistors N21, N22, and N23 to which three signal voltages Vin1, Vin2, and Vin3 are input are provided in parallel. In this case, two npn transistors N11 and N12 are provided at the node Nc as the capacitive load element 24. As a result, the parasitic capacitances of the nodes Nc and Na become substantially equal, and malfunction due to power supply noise is prevented.
More generally, when n (n ≧ 2) driver transistors whose input signal voltage is input to the node Na are provided in parallel, the node Nc is provided as the capacitive load element 15 with (n) having the same size as the driver transistor. The same effect can be obtained by providing -1) transistors.
[0039]
[Other embodiments]
In the embodiments described above, a bipolar transistor is used as the driver transistor of the differential amplifier. However, the present invention can be similarly applied to a case where a MOS transistor is used.
The signal voltage detection circuit 10d of FIG. 8 is an example in which n-channel MOS transistors MN2 and MN3 are used instead of the driver npn transistors N1 and N2 of the differential amplifier 11 in the signal voltage detection circuit 10a of FIG. With this change, an n-channel MOS transistor MN4 having the same shape and dimensions as the MOS transistors MN2 and MN3 and having a gate and a source connected is also used as the capacitive load element 15.
[0040]
9 uses n-channel MOS transistors MN2 and MN3 in place of the driver npn transistors N1 and N2 of the differential amplifier 11 in the signal voltage detection circuit 10a of FIG. The capacitor C is used as the capacitive load element 15.
The signal voltage detection circuit 10f in FIG. 10 uses n-channel MOS transistors MN2, MN31, and MN32 in place of the driver npn transistors N1, N21, and N22 of the differential amplifier 11 in the signal voltage detection circuit 10c in FIG. It is. With this change, n-channel MOS transistors MN41 and MN42 having the same structure and dimensions as the MOS transistors MN2, MN31 and MN32 are used as the capacitive load element 15 with the gate and source connected.
[0041]
11 is an example in which n-channel MOS transistors MN2, MN31, and N32 are used instead of the driver npn transistors N1, N21, and N22 of the differential amplifier 21 in the signal voltage detection circuit 20a in FIG. is there. With this change, an n-channel MOS transistor MN21 having a gate and a source connected is also used as the capacitive load element 24. P-channel MOS transistors MP11, MP12, and MP13 are also used for the pnp transistors P1, P2, and P3 in FIG.
[0042]
The signal voltage detection circuit 20d of FIG. 12 is an example in which n-channel MOS transistors MN2, MN31-MN33 are used in place of the driver npn transistors N1, N21-N23 of the differential amplifier 21 in the signal voltage detection circuit 20b of FIG. is there. With this change, as the capacitive load element 24, n-channel MOS transistors MN21 and MN22 having the same structure and dimensions as the MOS transistors MN2 and MN31 to MN33, which have their gates and sources connected, are used. P-channel MOS transistors MP11, MP12, and MP13 are also used for the pnp transistors P1, P2, and P3 in FIG.
[0043]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a signal voltage detection circuit capable of preventing malfunction due to power supply noise.
[Brief description of the drawings]
FIG. 1 is a diagram showing a signal voltage detection circuit according to an embodiment of the present invention.
FIG. 2 is an operation timing chart when the power supply noise occurs in the signal voltage detection circuit.
FIG. 3 is a diagram illustrating a signal voltage detection circuit according to another embodiment.
FIG. 4 is a diagram illustrating a signal voltage detection circuit according to another embodiment.
FIG. 5 is a diagram illustrating a signal voltage detection circuit according to another embodiment.
FIG. 6 is an operation timing chart when the power supply noise occurs in the signal voltage detection circuit.
FIG. 7 is a diagram illustrating a signal voltage detection circuit according to another embodiment.
FIG. 8 is a diagram illustrating a signal voltage detection circuit according to another embodiment.
FIG. 9 is a diagram illustrating a signal voltage detection circuit according to another embodiment.
FIG. 10 is a diagram illustrating a signal voltage detection circuit according to another embodiment.
FIG. 11 is a diagram illustrating a signal voltage detection circuit according to another embodiment.
FIG. 12 is a diagram illustrating a signal voltage detection circuit according to another embodiment.
FIG. 13 is a diagram illustrating a conventional signal voltage detection circuit.
FIG. 14 is an operation timing chart of the signal voltage detection circuit.
FIG. 15 is a diagram showing another conventional signal voltage detection circuit.
FIG. 16 is an operation timing chart of the signal voltage detection circuit.
FIG. 17 is an operation timing chart when power supply noise occurs in the circuit of FIG. 13;
18 is an operation timing chart when power supply noise occurs in the circuit of FIG.
[Explanation of symbols]
10a to 10f, 20a to 20d: signal voltage detection circuit, 11: differential amplifier, 12: current mirror circuit, 13: current-voltage conversion circuit, 14: latch circuit, 15: capacitive load element, 21: differential amplifier , 22 ... voltage amplifying unit, 23 ... latch circuit, 24 ... capacitive load element.

Claims (9)

A differential amplifier having first and second driver transistors to which a reference voltage and a signal voltage to be detected are respectively input;
A current mirror circuit for extracting an output current corresponding to a detection output of the differential amplifier;
A current-voltage conversion circuit that converts a change in the output current of the current mirror circuit into a voltage and outputs the voltage;
A latch circuit to which an output of the current-voltage conversion circuit is transferred and held;
A capacitive load element connected to an input node of the current-voltage conversion circuit;
A signal voltage detection circuit comprising: The first and second driver transistors of the differential amplifier are bipolar transistors whose emitters are commonly connected to a current source,
2. The signal according to claim 1, wherein the capacitive load element has the same structure and dimensions as a driver transistor used in the differential amplifier, and is a bipolar transistor having a base and an emitter commonly connected. Voltage detection circuit. The first and second driver transistors of the differential amplifier are bipolar transistors whose emitters are commonly connected to a current source,
2. The signal voltage detection circuit according to claim 1, wherein said capacitive load element is a capacitor having a capacitance substantially equal to a collector capacitance of a driver transistor of said differential amplifier. The first and second driver transistors of the differential amplifier are MOS transistors whose sources are commonly connected to a current source,
2. The signal according to claim 1, wherein the capacitive load element has the same structure and dimensions as a driver transistor used in the differential amplifier, and is a MOS transistor having a gate and a source commonly connected. Voltage detection circuit. The differential amplifier has n (n ≧ 2) second driver transistors connected to each other to which different signal voltages are input,
2. The signal voltage according to claim 1, wherein the capacitive load element is configured by n parallel-connected transistors having the same structure and dimensions as a driver transistor used in the differential amplifier. Detection circuit. A first driver transistor connected to a first output node and receiving a reference voltage, and n transistors (n ≧ 2) connected in parallel to a second output node and receiving different signal voltages to be detected. A second driver transistor, a first load transistor connected between the first output node and a power supply terminal, and a current mirror configured with the first load transistor and the second output node and a power supply terminal. A differential amplifier having a second load transistor connected between
A latch circuit to which a detection output of a second output node of the differential amplifier is transferred and held;
A capacitive load element connected to a first output node of the differential amplifier;
A signal voltage detection circuit comprising: The first and second driver transistors of the differential amplifier are bipolar transistors whose emitters are commonly connected to a current source,
The capacitive load element has the same structure and dimensions as a driver transistor used in the differential amplifier, and is a base transistor and an emitter commonly connected, and (n-1) bipolar transistors are connected in parallel. 7. The signal voltage detection circuit according to claim 6, wherein: The first and second driver transistors of the differential amplifier are bipolar transistors whose emitters are commonly connected to a current source,
7. The signal voltage detection circuit according to claim 6, wherein the capacitive load element is a capacitor having a capacitance substantially equal to (n-1) collector capacitances of the driver transistors of the differential amplifier. The first and second driver transistors of the differential amplifier are MOS transistors whose sources are commonly connected to a current source,
The capacitive load element is a MOS transistor having the same structure and dimensions as a driver transistor used in the differential amplifier, and (n-1) MOS transistors having a gate and a source connected in common and connected in parallel. The signal voltage detection circuit according to claim 6, wherein:

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