JP2005057627A - Peak detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a peak detection circuit which is highly accurately operated at ultra high speed. <P>SOLUTION: The peak detection circuit is provided with; a transistor 2 having the gate connected to an input terminal 1; a first capacity 3 connected to the source of the transistor; a first switch 4 connected in parallel to the first capacity 3; a buffer circuit to which a voltage held in the first capacity 3 is inputted; a second capacity 6 connected between the output of the buffer circuit 5 and an output terminal 8; and a second switch 7 connected between an input terminal 1 and the output terminal 8. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a peak detection circuit used in a burst mode optical communication system or the like.

  In an optical receiving circuit used in an optical communication system, an optical signal from an optical fiber is converted into a current by a photodiode, and then converted into a voltage signal by a transimpedance amplifier. Since it is very small in the vicinity, it needs to be amplified by an amplifier.

  However, since the output signal of the transimpedance amplifier is a single output, it is necessary to generate a reference voltage for the signal in order to amplify with a normal differential amplifier. Especially in burst mode transmission, it is necessary to recover data in a very short time after receiving an input signal, so this reference voltage must be generated instantaneously. Circuits are indispensable.

A conventional peak detection circuit includes a voltage / current conversion unit, a unidirectional conducting element such as a diode, a storage capacitor, a buffer circuit, and the like (see FIG. 7 of Non-Patent Document 1). In the operation of this peak detection circuit, the input voltage and the output voltage are first compared by the voltage / current converter, and when the input voltage is higher than the output voltage, the holding capacitor is charged through the unidirectional conducting element to raise the output voltage. . When the input voltage and the output voltage become equal, charging is terminated, and the maximum value of the input signal is detected and held.
M. Nakamura et al., "An Instantaneous Response CMOS Optical Receiver IC with Wide Dynamic Range and Extremely High Sensitivity Using Feed-Forward Auto-Bias Adjustment", IEEE Journal of Solid-State Circuits, Vol. 30, No. 9, pp 991-997, September 1995

  However, the configuration of the conventional peak detection circuit has a problem that high-speed operation is difficult. The reason is that the response of the voltage / current converter is slow. That is, the voltage / current conversion unit is configured by a current mirror circuit composed of a differential pair transistor biased by a current source and a transistor having a polarity opposite to that of the transistor, but due to a response delay of the current mirror circuit, The difference current between the currents flowing through the two transistors of the differential transistor pair cannot be generated and output instantaneously, and the storage capacitor cannot be charged with a current according to the exact difference voltage between the input voltage and the output voltage. For this reason, the ultra-high speed operation has a problem that charging is terminated before the output voltage reaches the peak of the input voltage, resulting in a large offset.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a peak detection circuit capable of high-precision and ultrahigh-speed operation.

  In order to achieve the above object, a first peak detection circuit according to the present invention includes a transistor having a gate connected to an input terminal, a first capacitor connected to a source of the transistor, and the first peak detection circuit. A first switch connected in parallel to the capacitor; a buffer circuit to which a voltage held in the first capacitor is input; and a second capacitor connected between an output and an output terminal of the buffer circuit And a second switch connected between the input terminal and the output terminal.

  The second peak detection circuit according to the present invention includes a first transistor whose gate is connected to the input terminal, a capacitor connected to the source of the first transistor, and a capacitor connected in parallel to the capacitor. A switch, an operational amplifier in which the voltage held in the capacitor is input to a non-inverting input terminal, a second transistor having an output terminal of the operational amplifier connected to a gate, and an inverting input terminal connected to a source; And a bias circuit connected to the source of the second transistor.

  The third peak detection circuit according to the present invention includes a comparator having two inputs, a switch whose opening / closing is controlled according to the output of the comparator, and a current source connected in cascade to the switch. And a plurality of current output circuits whose output currents are controlled according to the comparison result of the comparator, and a level shift circuit having a capacity, one input, and a plurality of outputs having different level shift amounts. And one input of each comparator of the plurality of current output circuits is connected to an input terminal of the peak detection circuit, an output of each current output circuit is connected to the capacitor, and a voltage held in the capacitor is Input to the level shift circuit, and a plurality of outputs of the level shift circuit are respectively connected to the other input of each comparator of the plurality of current output circuits Than it is.

  A fourth peak detection circuit according to the present invention includes a plurality of switch control current sources each including a comparator having two inputs, a differential switch, and current sources connected to the inputs of the differential switch. The differential switch includes two transistors whose sources are coupled to each other, the source serving as an input terminal, and the gate of one of the transistors serving as a control terminal A predetermined voltage is applied to the gate of the other transistor, the switch having the drain of one of the transistors as an output terminal, and the input terminal of the peak detection circuit is connected to one input of the comparator, The output of the comparator is connected to the control terminal of each differential switch of the plurality of switch control current sources, and the plurality of switch control currents Are connected to the capacitor, the voltage held in the capacitor is input to the buffer circuit, the output of the buffer circuit is connected to the other input of the comparator, and the plurality of switch control current sources Each differential switch is configured to be given a different predetermined voltage.

  The fifth peak detection circuit according to the present invention includes a comparator having two inputs, a switch control current source including a differential switch and a current source connected to the input of the differential switch, and a capacitor. And the buffer circuit, wherein the differential switch includes two transistors whose sources are coupled to each other, the source serving as an input terminal, the gate of one transistor serving as a control terminal, and the other A predetermined voltage is applied to the gate of the transistor, and the drain of one of the transistors is an output terminal. The input terminal of the peak detection circuit is connected to one input of the comparator. The output is connected to the control terminal of the differential switch of the switch control current source, and the output of the switch control current source is connected to the capacitor. The voltage held in the capacitor is input to the buffer circuit, the output of the buffer circuit is connected to the other input of the comparator, and the predetermined voltage supplied to the differential switch of the switch control current source is the capacitor It is configured to change according to the voltage held in the circuit.

  According to the first peak detection circuit of the present invention, it is possible to detect a peak at high speed and low power consumption.

  Also, according to the second peak detection circuit of the present invention, the same effect as the first peak detection circuit can be realized with one capacitor and one switch.

  Moreover, according to the third peak detection circuit of the present invention, a high-speed and highly accurate peak detection operation can be realized.

  Further, according to the fourth peak detection circuit of the present invention, the same effect as the third peak detection circuit can be realized with one comparator.

  Moreover, according to the fifth peak detection circuit of the present invention, a highly accurate peak detection operation can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 shows a peak detection circuit according to Embodiment 1 of the present invention. Here, the maximum value detection circuit is taken as an example. 1, the input terminal 1 is connected to the gate of the NMOS transistor 2, the high-potential power supply Vdd is connected to the drain, and the source and the low-potential power supply Vss are connected to each other. 1 capacitor 3 and first switch 4 are connected. The voltage Vc held in the first capacitor 3 is given to the input terminal of the buffer circuit 5 by the source follower constituted by the PMOS transistor 5a and the bias current source 5b, that is, the gate of the PMOS transistor 5a. A second capacitor 6 is connected between the output terminal of the buffer circuit 5 (the source of the PMOS transistor 5a) and the output terminal 8, and a second capacitor 6 is connected between the input terminal 1 and the output terminal 8. A switch 7 is connected. In the following description, the voltage of the input terminal 1, that is, the input terminal voltage is Vin, and the voltage of the output terminal 8, that is, the output terminal voltage is Vout. Further, the threshold voltage of the NMOS transistor 2 is set to Vth.

  The operation of the first embodiment will be described with reference to FIG. First, when the input is no signal, the first switch 4 is closed to discharge the first capacitor 3. When the first switch 4 is opened after the discharge is completed, the first capacitor 3 is rapidly charged by the NMOS transistor 2, but the voltage difference between the voltage at the input terminal 1 and the voltage Vc held in the first capacitor 3. Reaches the threshold voltage Vth of the NMOS transistor 2, the NMOS transistor 2 is cut off and charging is terminated.

  Next, when the second switch 7 is closed, the input terminal 1 and the output terminal 8 are short-circuited, so that the difference voltage between the output voltage of the buffer circuit 5 (source voltage of the PMOS transistor 5a) and the voltage of the input terminal 1 is reached. Is added to the second capacitor 6 and the difference voltage, that is, the offset voltage is held in the second capacitor 6 when the second switch 7 is opened.

  When an input signal is input, the holding voltage Vc of the first capacitor 3 changes in accordance with the maximum value of the voltage Vin at the input terminal 1, but this holding voltage Vc is always held in the second capacitor 6. Since the offset voltage is added and output, the voltage Vout at the output terminal 8 is always an accurate maximum value of the input terminal voltage Vin.

  As described above, in the first embodiment, unlike the conventional peak detection circuit, the first capacitor is rapidly used by the drain current of the transistor 2 to which the input signal is applied to the gate without using the voltage / current conversion circuit. 3, and the offset voltage between the input and output is canceled by the second capacitor 6, so that high-precision and high-speed peak detection is possible.

  Although the source follower is used as the buffer circuit 5 in the first embodiment, a voltage follower using an operational amplifier may be used. In this case, a more accurate operation can be realized.

  Further, although the first embodiment is configured based on the maximum value detection circuit, a circuit based on the minimum value detection circuit can be easily configured. In that case, the polarity of all the transistors in FIG. 1 may be switched and the power supplies Vdd and Vss may be reversed.

(Embodiment 2)
FIG. 3 shows a peak detection circuit according to the second embodiment of the present invention. Here, as in the case of the first embodiment, the maximum value detection circuit is taken as an example. The configuration will be described with reference to FIG. 3. The input terminal 1 is connected to the gate of the first NMOS transistor 2, and the capacitor 3 and the reset switch 4 are connected between the source and the low-potential side power supply Vss. ing. The non-inverting input terminal of the operational amplifier 9 is supplied with the holding voltage Vc of the capacitor 3, the source of the second NMOS transistor 10 is connected to the inverting input terminal of the operational amplifier 9, and the output terminal of the operational amplifier 9 is connected to the second terminal. The gates of the two NMOS transistors 10 and the output terminal 8 are connected to each other. A constant current source as a bias circuit 11 is connected to the source of the second NMOS transistor 10. The drains of the first NMOS transistor 2 and the second NMOS transistor 10 are both connected to the high potential side power supply Vdd.

  Here, if the transistor sizes and layouts of the first NMOS transistor 2 and the second NMOS transistor 10 are the same, and the current value of the constant current source of the bias circuit 11 is set to be small, The gate-source voltage of the NMOS transistor 10 becomes equal to the threshold voltage of the first NMOS transistor 2. In addition, because of the operation of the operational amplifier 9, the voltages at the inverting input terminal and the non-inverting input terminal are equal to each other. The voltage is higher by the gate-source voltage. As a result, the output terminal voltage Vout is always the maximum value of the input terminal voltage Vin.

  As described above, in the second embodiment, unlike the first embodiment, it can be configured by one capacitor 3 and one switch 4, so that only one switch control signal is required, and a simpler control signal. An effect equivalent to that of the first embodiment can be obtained by the generation circuit.

  Although the second embodiment is configured based on the maximum value detection circuit, a circuit based on the minimum value detection circuit can be easily configured. In that case, the polarity of all the transistors in FIG. 3 may be switched and the power supplies Vdd and Vss may be reversed.

(Embodiment 3)
FIG. 4 shows a peak detection circuit according to Embodiment 3 of the present invention. Here, the case of having two current output circuits is shown by taking the maximum value detection circuit as an example. The configuration will be described with reference to FIG. 4. A comparator 22 having two inputs, a differential switch 24 to which an output signal of the comparator 22 is supplied to a control terminal, and a current source connected to the input terminal of the differential switch 24. 23 constitutes a first current output circuit 25. Here, the differential switch 24 and the current source 23 constitute a first switch control current source. Similarly, the differential switch 28 and the current source 27 constitute a second switch control current source, and the second switch control current source and the comparator 26 constitute a second current output circuit 29. The output terminals of the differential switches 24 and 28 are connected to the capacitor 30 and the reset switch 31, and the other ends of the capacitor 30 and the reset switch 31 are connected to the low potential side power source Vss. The voltage Vc held in the capacitor 30 is input to the input terminals of the level shift circuit 32 and the buffer circuit 33. The level shift circuit 32 includes a cascade connection of a constant current source, a resistor, and a PMOS transistor. The gate of the PMOS transistor is used as an input terminal, and both ends of the resistor are used as two output terminals. Further, the buffer circuit 33 connected to the output terminal 34 has a configuration in which the resistor is removed from the level shift circuit 32. The lower voltage of the two output voltages of the level shift circuit 32 is connected to one input of the comparator 22 in the first current output circuit 25, and the higher voltage is connected to the comparator in the second current output circuit 29. The other input of each of the comparators 22 and 26 is connected to the input terminal 21. Here, it is assumed that the current value I2 of the constant current source 27 in the second current output circuit 29 is set larger than the current value I1 of the constant current source 23 in the first current output circuit 25. A voltage V1 is applied to the differential switch 24 in the first current output circuit 25, and a voltage V2 is applied to the differential switch 28 in the second current output circuit 29. In the following description, the voltage of the input terminal 21, that is, the input terminal voltage is Vin, and the voltage of the output terminal 34, that is, the output terminal voltage is Vout.

  The operation of the third embodiment will be described with reference to FIG. First, the lower voltage of the level shift circuit 32 is equal to Vout. Therefore, the first current output circuit 25 compares Vin and Vout, and continues to charge the capacitor 30 by outputting a current until Vout becomes equal to Vin.

  On the other hand, the second current output circuit 29 compares Vin with a voltage (Vout + VR) that is higher than Vout by VR, where VR is the voltage across the resistors of the level shift circuit 32, and when Vin is higher. Since a current is output, the capacitor 30 is charged by outputting a current until Vout becomes equal to a voltage (Vin−VR) lower than Vin by VR.

  That is, in the period T1 from time t1 to time t2 in FIG. 5, both the first and second current output circuits 25 and 29 operate to charge the capacitor 30 rapidly. On the other hand, in the period T2 from time t2 to t3 in FIG. 5, only the first current output circuit 25 operates to charge the capacitor 30 gently.

  Accordingly, first, the capacitor 30 is rapidly charged by the large current of the current source 27 in the second current output circuit 29, and Vout rises rapidly, but at time t2, Vout is a voltage (Vin−VR) lower than Vin by VR. ), The charging by the second current output circuit 29 is finished, and the capacitor 30 is charged only by the output current of the first current output circuit 25 in the period T2. As a result, voltage offset due to overcharging, which becomes a problem in the case of rapid charging with a large current, can be suppressed, and peak detection with high speed and high accuracy is possible.

  In the third embodiment, the case where there are two current output circuits has been described. Even in the case where there are three or more current output circuits, by increasing the number of resistors of the level shift circuit 32, the same as in the third embodiment. The peak detection circuit can be easily configured.

(Embodiment 4)
FIG. 6 shows a peak detection circuit according to the fourth embodiment of the present invention. Here, the case of having two switch control current sources is shown taking the maximum value detection circuit as an example. The configuration will be described with reference to FIG. 6. The first switch control current source 36 is configured by the differential switch 24 and the current source 23 connected to the input terminal of the differential switch 24. Similarly, the differential switch 28 and the current source 27 constitute a second switch control current source 37. The output terminals of the differential switches 24 and 28 are connected to the capacitor 30 and the reset switch 31, and the other ends of the capacitor 30 and the reset switch 31 are connected to the low potential side power source Vss. The voltage Vc held in the capacitor 30 is input to the input terminal of the buffer circuit 35. The output of the buffer circuit 35 is connected to the output terminal 34 and to one input of the comparator 22, and the other input of the comparator 22 is connected to the input terminal 21. The output of the comparator 22 is connected to the control terminal of each of the differential switches 24 and 28. Here, the current value I2 of the constant current source 27 in the second switch control current source 37 is set larger than the current value I1 of the constant current source 23 in the first switch control current source 36, and the second switch It is assumed that the voltage V2 applied to the differential switch 28 in the control current source 37 is set lower than the voltage V1 applied to the differential switch 24 in the first switch control current source 36.

  The control terminal voltage at which current starts to be output from each differential switch 24, 28 becomes lower as the voltages V1, V2 applied to the differential switches 24, 28 are lower. In other words, the lower the voltages V1 and V2 applied to the differential switches 24 and 28, the earlier the switch is turned off with respect to the increase in the control terminal voltage, and no current output can be obtained.

  Therefore, as the input terminal voltage Vin rises, first, the capacitor 30 is rapidly charged by a large current value from the second switch control current source 37, and the output terminal voltage Vout rises rapidly, but Vout becomes Vin. Before reaching, the differential switch 28 in the second switch control current source 37 is turned off, and charging is performed only by the current from the first switch control current source 36. With the above operation, as in the third embodiment, voltage offset due to overcharging, which becomes a problem in the case of rapid charging with a large current, can be suppressed, and peak detection with high speed and high accuracy is possible.

  Although the case where there are two switch control current sources has been described in the fourth embodiment, a peak detection circuit similar to that of the fourth embodiment can be easily configured even when there are three or more switch control current sources.

(Embodiment 5)
FIG. 7 shows a peak detection circuit according to the fifth embodiment of the present invention. Here, another embodiment based on the configuration of the third embodiment (see FIG. 4) is shown. In the fifth embodiment, a differential switch reference voltage generation circuit 38 is added so that the voltage Vsw applied to the differential switches 24 and 28 changes according to the voltage Vc held in the capacitor 30. ing.

  The differential switch reference voltage generation circuit 38 according to the fifth embodiment includes a source coupled transistor pair of PMOS transistors biased by a constant current source, and compares the voltage Vc held in the capacitor 30 with a predetermined voltage Vref. As the voltage Vc held in the capacitor 30 increases, the current input to the current mirror circuit configured by the NMOS transistor decreases, and the voltage Vsw applied to the differential switches 24 and 28 increases. ing.

  On the other hand, in the case of the maximum value detection circuit, the comparators 22 and 26 each having two inputs are usually configured by a source coupled NMOS transistor pair biased by a constant current source and an active load by a PMOS transistor. In general, in this configuration, as the input voltage increases, a larger output amplitude cannot be obtained. Therefore, an error occurs in the peak detected voltage as the input voltage increases.

  However, in the fifth embodiment, the differential switch reference voltage generation circuit 38 increases the voltage Vsw applied to the differential switches 24 and 28 as the voltage Vc held in the capacitor 30 increases, so that the differential switch 24 and 28 are easily turned on, so that the decrease in the output currents of the first and second current output circuits 25 and 29 due to the output amplitude reduction of the comparators 22 and 26 that occurs as the input terminal voltage Vin increases is compensated. It is possible to suppress the occurrence of errors.

  As described above, in the fifth embodiment, the comparators 22 and 26 are configured such that the predetermined voltage applied to the differential switches 24 and 28 changes according to the voltage Vc held in the capacitor 30. Malfunction caused by a change in response characteristics due to the input voltage level can be suppressed.

  In addition, although the structure based on Embodiment 3 was shown here, it can comprise similarly about Embodiment 4, and the same effect can be acquired.

  As described above, the peak detection circuit according to the present invention is capable of high-precision and ultrahigh-speed operation, and is useful in optical communication systems and the like.

It is a circuit diagram showing the peak detection circuit which concerns on Embodiment 1 of this invention. FIG. 2 is a timing diagram illustrating an operation of the peak detection circuit of FIG. 1. It is a circuit diagram showing the peak detection circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram showing the peak detection circuit which concerns on Embodiment 3 of this invention. FIG. 5 is a timing diagram illustrating an operation of the peak detection circuit of FIG. 4. It is a circuit diagram showing the peak detection circuit which concerns on Embodiment 4 of this invention. It is a circuit diagram showing the peak detection circuit which concerns on Embodiment 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input terminal 2,10 NMOS transistor 3,6 Capacity | capacitance 4,7 Switch 5 Buffer circuit 5a PMOS transistor 5b Bias current source 8 Output terminal 9 Operational amplifier 11 Bias circuit 21 Input terminals 22, 26 Comparator 23, 27 Current sources 24, 28 Switches 25, 29 Current output circuit 30 Capacitor 31 Reset switch 32 Level shift circuit 33, 35 Buffer circuit 34 Output terminal 36, 37 Switch control current source 38 Reference voltage generation circuit for differential switch

Claims (9)

A transistor whose gate is connected to the input terminal;
A first capacitor connected to a source of the transistor;
A first switch connected in parallel to the first capacitor;
A buffer circuit to which a voltage held in the first capacitor is input;
A second capacitor connected between the output of the buffer circuit and an output terminal;
A peak detection circuit comprising a second switch connected between the input terminal and the output terminal. The peak detection circuit according to claim 1,
The peak detection circuit, wherein the buffer circuit is a source follower. The peak detection circuit according to claim 1,
The peak detection circuit, wherein the buffer circuit is a voltage follower. A first transistor having a gate connected to the input terminal;
A capacitor connected to a source of the first transistor;
A switch connected in parallel to the capacitor;
An operational amplifier in which the voltage held in the capacitor is input to the non-inverting input terminal;
A second transistor having an output terminal of the operational amplifier connected to a gate and an inverting input terminal of the operational amplifier connected to a source;
A peak detection circuit comprising: a bias circuit connected to a source of the second transistor. Comprising a comparator having two inputs each, a switch whose opening and closing is controlled according to the output of the comparator, and a current source cascaded to the switch, the output current is controlled according to the comparison result of the comparator A plurality of current output circuits,
Capacity,
A peak detection circuit comprising a level shift circuit having one input and a plurality of outputs having different level shift amounts,
One input of each comparator of the plurality of current output circuits is connected to the input terminal of the peak detection circuit, the output of each current output circuit is connected to the capacitor, and the voltage held in the capacitor is the level shift circuit And a plurality of outputs of the level shift circuit are connected to the other inputs of the comparators of the plurality of current output circuits, respectively. The peak detection circuit according to claim 5, wherein
The switch has two transistors whose sources are coupled to each other, the source is an input terminal, the gate of one transistor is a control terminal, and a predetermined voltage is applied to the gate of the other transistor. A peak detection circuit comprising a differential switch having a drain of one transistor as an output terminal. In the peak detection circuit according to claim 5 or 6,
2. The peak detection circuit according to claim 1, wherein the level shift circuit includes a cascade connection of a constant current source, one or more resistors, and a transistor. A comparator having two inputs;
A plurality of switch control current sources each comprising a differential switch and a current source connected to the input of the differential switch;
Capacity,
A peak detection circuit comprising a buffer circuit,
The differential switch includes two transistors whose sources are coupled to each other, the source as an input terminal, the gate of one transistor as a control terminal, and a predetermined voltage applied to the gate of the other transistor, A switch having the drain of one of the transistors as an output terminal,
An input terminal of the peak detection circuit is connected to one input of the comparator, an output of the comparator is connected to a control terminal of each differential switch of the plurality of switch control current sources, and the plurality of switch control current sources Are connected to the capacitor, the voltage held in the capacitor is input to the buffer circuit, the output of the buffer circuit is connected to the other input of the comparator, and the plurality of switch control current sources A peak detection circuit, wherein each differential switch is given a different predetermined voltage. A comparator having two inputs;
A switch control current source comprised of a differential switch and a current source connected to the input of the differential switch;
Capacity,
A peak detection circuit comprising a buffer circuit,
The differential switch includes two transistors whose sources are coupled to each other, the source as an input terminal, the gate of one transistor as a control terminal, and a predetermined voltage applied to the gate of the other transistor, A switch having the drain of one of the transistors as an output terminal,
An input terminal of the peak detection circuit is connected to one input of the comparator, an output of the comparator is connected to a control terminal of a differential switch of the switch control current source, and an output of the switch control current source is connected to the capacitor A voltage that is connected and held in the capacitor is input to the buffer circuit, an output of the buffer circuit is connected to the other input of the comparator, and is applied to a differential switch of the switch control current source Is configured to change according to the voltage held in the capacitor.

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