CN117544140B - Along with the change of power supply voltage Stable time delay circuit and chip - Google Patents

Along with the change of power supply voltage Stable time delay circuit and chip Download PDF

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CN117544140B
CN117544140B CN202410030314.XA CN202410030314A CN117544140B CN 117544140 B CN117544140 B CN 117544140B CN 202410030314 A CN202410030314 A CN 202410030314A CN 117544140 B CN117544140 B CN 117544140B
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inverter
delay
stage
clock signal
unit
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CN117544140A (en
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杨宏
高俊君
黄海
程飞
吴清源
吕尧明
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Hangzhou Mixin Microelectronic Co ltd
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Hangzhou Mixin Microelectronic Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)

Abstract

The invention relates to the technical field of delay circuits, and provides a delay circuit and a chip which are stable along with the change of power supply voltage.

Description

Delay circuit and chip stable along with power supply voltage change
Technical Field
The invention relates to the technical field of delay circuits, in particular to a delay circuit and a chip which are stable along with the change of power supply voltage.
Background
In the chip design, the delay circuit is a very important unit, so that the delay module is not separated from any integrated circuit. For example, the timing design is one of the most important links in the chip design, and without accurate timing design, the digital circuit cannot work normally, and in the timing design, different delay modules are needed to be inserted according to the needs to meet the needs of the scene. For another example, the clock is an indispensable signal for the chip to work, and the clock is mainly generated by an oscillator, wherein the ring oscillator is composed of a delay module and an inverter.
In many situations where a delay circuit is needed, the delay time stability of the delay module is an important index, for example, a ring oscillator, if the delay time is greatly changed, this means that the frequency is greatly changed, for example, many calculation circuits, if the delay is greatly changed, insufficient time sequence may occur, and the operation is finished if not completed, and so on. In some of the above-mentioned delay circuits, except that the delay circuit participated by the clock is determined by the clock performance, most of other delay modules have great changes in delay along with the power supply voltage, for example, the delay formed by cascading of inverters, under a certain CMOS process, the maximum delay can be about 5 times of the minimum delay, and the different processes have different ranges, but the same result has great changes, and the trouble is brought to chip design in many scenes.
Disclosure of Invention
The invention aims to solve the problem of inaccurate time delay caused by the change of the power supply voltage of the traditional time delay circuit, and provides a time delay circuit and a chip which are stable along with the change of the power supply voltage.
In order to achieve the above object, the present invention provides a delay circuit that is stable with a change in a power supply voltage, including a first delay module and a second delay module; the first delay module is used for receiving the first clock signal for delay, obtaining a second clock signal and outputting the second clock signal to the second delay module; the second delay module is used for receiving the second clock signal to delay, obtaining a third clock signal and outputting the third clock signal;
the delay time of the first delay module is increased along with the increase of the power supply voltage, the delay time of the second delay module is reduced along with the increase of the power supply voltage, and the delay increasing ratio of the first delay module is consistent with the delay decreasing ratio of the second delay module.
As an implementation manner, the first delay module comprises a first charge-discharge unit and a first trigger unit;
the first charge and discharge unit is used for receiving the constant current output by the first clock signal and the current source, and obtaining a low current reference after limiting the constant current, and carrying out charge and discharge based on the power supply voltage and the low current reference to realize time delay of the first clock signal;
the first trigger unit is used for forming hysteresis, and when the voltage value achieved by charging and discharging reaches the trigger threshold value of the first trigger unit, the first trigger unit is started, and the first trigger unit outputs a second clock signal to the second delay module; wherein, as the power supply voltage increases, the trigger threshold of the first trigger unit becomes larger so that the delay time increases.
As an implementation manner, the first charge-discharge unit includes a first current limiting unit, a second current limiting unit, a first inverter and a first capacitor corresponding to the first inverter, and a first clock signal input terminal is connected to a first input terminal of the first inverter; the first current limiting unit and the second current limiting unit are used for limiting the input current source so as to respectively provide a low current reference for the second input end and the third input end of the corresponding first inverter, and the output end of the first inverter is connected with the corresponding first capacitor so as to realize time delay by charging and discharging the corresponding first capacitor based on the low current reference.
As an implementation manner, the first current limiting unit includes a third PMOS tube PM3, the second current limiting unit includes a third NMOS tube NM3, the first inverter includes a fourth PMs tube PM4 and a fourth NOMS tube NM4, a source electrode of the third PMOS tube PM3 is connected to a first current source terminal, a gate electrode of the third PMOS tube PM3 is connected to a second current source terminal and VDD, a drain electrode of the third PMOS tube PM3 is connected to a source electrode of the fourth PMOS tube PM4, a gate electrode of the fourth PMOS tube PM4 and a gate electrode of the fourth NMOS tube NM4 are used as input terminals of the first inverter, a gate electrode of the fourth PMOS tube PM4 is connected to VDD, a gate electrode of the fourth NMOS tube NM4 is connected to VSS, a source electrode of the fourth PMOS tube PM4 is connected to a drain electrode of the third NMOS tube NM3, one end of the first capacitor C1 and an output terminal of the first inverter, a gate electrode of the third NOMS tube PM3 is connected to a third NMOS terminal and VSS, and a source electrode of the fourth NMOS tube NM3 is connected to a fourth current source terminal of the fourth NMOS tube NM 3; the other end of the first capacitor C1 is connected with VSS or VDD.
As a kind of cocoa in an embodiment of the present invention, the second delay module comprises a second charge-discharge unit and a second trigger unit;
the second charge-discharge unit is used for receiving the second clock signal and constant current output by the current source, charging and discharging are carried out based on the power supply voltage and constant current to realize time delay of the second clock signal;
the second trigger unit is used for forming hysteresis, and when the voltage value achieved by charging and discharging reaches the trigger threshold value of the second trigger unit, the second trigger unit is started, and the second trigger unit outputs a third clock signal;
the resistance of the second charging and discharging unit is reduced to reduce the delay time along with the increase of the power supply voltage, the trigger threshold of the second trigger unit is increased to increase the delay time, and the delay reduction ratio of the second charging and discharging unit is larger than the delay increase ratio of the second trigger unit.
As an implementation manner, the second charge-discharge unit includes at least one stage of second inverter and a corresponding second capacitor in cascade; the input end of the second clock signal is connected with the input end of the first-stage second inverter, the input end of the second trigger unit is connected with the output end of the last-stage second inverter, and the output end of the previous-stage second inverter is connected with the input end of the next-stage second inverter; the output end of the first inverter is connected with a corresponding first capacitor, so that the corresponding second capacitor is charged and discharged based on constant current to realize time delay; wherein the second inverter is an inverted-ratio tube inverter.
As an implementation manner, the second charge-discharge unit includes a first stage second inverter, a second stage second inverter and second capacitors respectively corresponding to the first stage second inverter and the second stage second inverter, where the first stage second inverter includes an eighth PMOS pipe PM8 and an eighth NMOS pipe NM8, a gate of the eighth PMOS pipe PM8 and a gate of the eighth NMOS pipe NM8 are used as input ends of the first stage second inverter, a gate of the eighth PMOS pipe PM8 is connected to VDD, a gate of the eighth NMOS pipe NM8 is connected to VSS, a source of the eighth PMOS pipe PM8 is connected to a first current source end, a source of the eighth NMOS pipe NM8 is connected to a fourth current source end, a gate of the eighth PMOS pipe PM8 is connected to VDD, a drain of the eighth PMOS pipe PM8 is connected to VSS, one end of the corresponding first stage second capacitor C2 and an input end of the second stage second inverter, and a drain of the eighth PMOS pipe PM8 is connected to VDD or another end of the second stage capacitor C2;
the second-stage second inverter comprises a ninth PMOS tube PM9 and a ninth NMOS tube NM9, wherein a source electrode of the ninth PMOS tube PM9 is connected with a first power supply source end, a source electrode of the ninth NMOS tube NM9 is connected with a fourth power supply source end, a grid electrode of the ninth PMOS tube PM9 and a grid electrode of the ninth NMOS tube NM9 serve as input ends of the second-stage second inverter, a grid electrode of the ninth PMOS tube PM9 is connected with VDD, a grid electrode of the ninth NMOS tube NM9 is connected with VSS, a drain electrode of the ninth PMOS tube PM9 is connected with a drain electrode of the ninth NMOS tube NM9, one end of a second-stage second capacitor C3 and an output end of the second-stage second inverter, and the other end of the second-stage second capacitor C3 is connected with VSS or VDD.
As an embodiment, the apparatus further includes a low current reference generating unit; the low current reference generating unit is used for generating a current source which is stable along with the change of the power supply voltage and outputting the current source to the first delay module and the second delay module.
As an embodiment, further comprising: an output driving unit; the output driving unit is used for receiving the third clock signal and improving the driving capability of the third clock signal so as to drive an external load.
Correspondingly, the invention also provides a chip comprising the delay circuit which is stable along with the change of the power supply voltage.
The invention has the beneficial effects that: the invention provides a delay circuit and a chip which are stable along with the change of power supply voltage.
Drawings
Fig. 1 is a schematic diagram of a delay circuit that is stable with power supply voltage according to some embodiments of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In addition to the problem of the delay varying with the supply voltage greatly mentioned in the background art, the delay circuit also has a requirement of low power consumption, for example, in the fields of hand-held and battery powered, the low power consumption is also important for the delay modules, because in the chip, the delay modules are many, sometimes a relatively large delay is required, many gates are required to be cascaded in a common design, and many gates participate in the flip at one flip, so that a relatively large current is generated. Therefore, low power design of the delay circuit is also one of important design methods.
In addition, various delay circuits exist at present, some delay circuits realize longer delay through combining a clock with a counter, the precision of the delay is related to the precision of the clock, the delay circuits can be designed to be more accurate, and the disadvantage is that an additional clock is needed. In many timing designs, standard cascaded inverters are directly inserted, and the method is very simple in design, has the defect that the required delay is relatively large, and a plurality of inverter circuits are required to be inserted, so that the method has large area and power consumption, and can only be used in a delay scene requiring a relatively short time. Accordingly, the present invention, in some embodiments, also improves upon the need for low power consumption.
With reference to figure 1 of the drawings, some embodiments of the invention provide a delay circuit that is stable with supply voltage variations, the system is characterized by comprising a first delay module 200 and a second delay module 300;
the first delay module 200 is configured to receive the first clock signal I1 for delay, obtain a second clock signal I2, and output the second clock signal I2 to the second delay module 300; the second delay module 300 is configured to receive the second clock signal I2, delay the second clock signal to obtain a third clock signal I3, and output the third clock signal I3;
the delay time of the first delay module 200 increases with the increase of the power supply voltage, the delay time of the second delay module 300 decreases with the increase of the power supply voltage, and the delay increasing ratio of the first delay module 200 is consistent with the delay decreasing ratio of the second delay module 300.
By designing, the delay time of the first delay module 200 increases with the increase of the power supply voltage, the delay time of the second delay module 300 decreases with the increase of the power supply voltage, and the delay increasing ratio of the first delay module 200 is consistent with the delay decreasing ratio of the second delay module 300, so that the two modules are complementary to each other, and finally, the delay stable with the change of the power supply voltage is formed.
In some embodiments, the delay increase ratio of the first delay module 200 and the delay decrease ratio of the second delay module 300 may be approximately equal or completely equal.
In some embodiments, the first delay module 200 includes a first charge-discharge unit 210 and a first trigger unit 220; the first charge-discharge unit 210 is configured to receive the first clock signal V1 and a constant current output by a current source, obtain a low current reference after limiting the current source, and implement delay of the first clock signal by performing charge-discharge based on a power supply voltage and the low current reference; the first trigger unit 220 is configured to form hysteresis, and when a voltage value achieved by charging and discharging reaches a trigger threshold of the first trigger unit 220, the first trigger unit is turned on, and the first trigger unit 210 outputs a second clock signal I2 to the second delay module 220; wherein, as the power supply voltage increases, the trigger threshold of the first trigger unit 220 becomes larger so that the delay time increases.
In some embodiments, the Current Source is broadly called a Current Source (Current Source) and a Current Sink (Current Sink), which are used to charge and discharge the capacitor, respectively, according to the Current direction.
Some embodiments of the present invention implement low power consumption by limiting the current source that turns on the first charge/discharge unit 210, and implement charge/discharge with the low current reference, thereby generating delay, and thus implementing the same delay with lower power consumption. And the triggering threshold of the first triggering unit 220 is changed along with the power supply voltage, the larger the power supply voltage is, the larger the triggering threshold is, so that the delay time can be increased through the first triggering unit 220.
In some embodiments, the first charge-discharge unit 210 includes a first current limiting unit, a second current limiting unit, a first inverter, and a first capacitor corresponding to the first inverter, and a first clock signal input terminal is connected to a first input terminal of the first inverter; the first current limiting unit and the second current limiting unit are used for limiting the input current source so as to respectively provide a low current reference for the second input end and the third input end of the corresponding first inverter, the output end of the first inverter is connected with the corresponding first capacitor, so that the corresponding first capacitor is charged and discharged based on a low-current reference to realize time delay.
In some embodiments, the first current limiting unit and the second current limiting unit are used for limiting current, so that the low current reference is controllable, the control of the delay time can be realized by adjusting the low current reference and the load capacitor, and further, longer delay can be realized by single stage or a small number of stages. In some embodiments, when the delay is achieved by adjusting the number of cascaded first inverters, the first charge-discharge unit 210 includes at least one first inverter and a first capacitor corresponding to each first inverter, the first clock signal input terminal is connected to the first input terminal of the first inverter, the input terminal of the first trigger unit is connected to the output terminal of the last first inverter, and the output terminal of the first inverter of the previous stage is connected to the first input terminal of the first inverter of the next stage.
In some embodiments, when there is a first inverter with multiple stages, the first inverter with each stage may be limited by the same first current limiting unit and the second current limiting unit; specifically, a first end of the first current limiting unit is connected with a first current source end, a second end of the first current limiting unit is connected with a second current source end, and a third end of the first current limiting unit is connected with a second input end of each stage of the first inverter; the first end of the second current limiting unit is connected with a third current source end, the second end of the second current limiting unit is connected with a fourth current source end, the third end of the second current limiting unit is connected with the third input end of each stage of the first inverter, the output end of the first inverter is connected with one end of the corresponding first capacitor, and the other end of the first capacitor is connected with VSS; the first current source terminal, the second current source terminal, the third current source terminal and the fourth current source terminal are configured to receive a current source. However, in other embodiments, the first inverter of each stage may be separately limited by different first current limiting units and second current limiting units.
In some embodiments, the first current limiting unit includes a third PMOS tube PM3, the second current limiting unit includes a third NMOS tube NM3, the first inverter includes a fourth PMs tube PM4 and a fourth NOMS tube NM4, a source of the third PMOS tube PM3 is connected to a first current source terminal, a gate of the third PMOS tube PM3 is connected to a second current source terminal and VDD, a drain of the third PMOS tube PM3 is connected to a source of the fourth PMOS tube PM4, a gate of the fourth PMOS tube PM4 and a gate of the fourth NMOS tube NM4 are used as input terminals of the first inverter, a gate of the fourth PMOS tube PM4 is connected to VDD, a gate of the fourth NMOS tube NM4 is connected to VSS, a source of the fourth PMOS tube PM4 is connected to a drain of the third NMOS tube PM3, one terminal of the first capacitor C1 and an output terminal of the first inverter, a gate of the third NOMS tube PM3 is connected to a third terminal and VSS, and a source of the fourth current source of the third NMOS tube NM3 is connected to a fourth current source terminal of the fourth NMOS tube NM 3; the other end of the first capacitor C1 is connected with VSS or VDD.
In some implementations, the first inverter in the CMOS process is formed by serially connecting PMOS and NMOS, the inverter consumes no power at ordinary times, and only when the inverter turns over, current will occur to consume power, and the input signal of the inverter is a square wave signal, or turns over from 0 to 1 or from 1 to 0. For the former, the PMOS transitions from on state to off state, the NMOS transitions from off state to on state, eventually causing the output to complete a corresponding flip, and for the latter, the opposite is true. It should be noted that the inversion is a process in which the consumed current mainly has two parts, one part is to charge and discharge the load capacitor, the other part is current leakage caused by simultaneous conduction of the PMOS and the NMOS, and the other part is short-circuit current, which is an undesirable current. The mirror current of the current mirror is used for obtaining a low current reference, and the peak current of the short circuit current is limited, so that the components of the short circuit current are reduced, and low power consumption is realized.
In some embodiments, since the first charge-discharge unit 210 is charged and discharged by a small current, the rising or falling speed of the charge-discharge point is relatively slow, and because of the existence of noise and interference, an undesirable short pulse is easy to occur, and the first trigger unit 220 is added at the rear stage, so that hysteresis can be formed, and the influence of noise and interference is resisted. In an embodiment, the first trigger unit 220 may be a schmitt trigger. In some embodiments, the first trigger unit includes a fifth PMOS pipe PM5, a sixth PMOS pipe PM6, a seventh PMOS pipe PM7, a fifth NMOS pipe NM5, a sixth NMOS pipe NM6, and a seventh NMOS pipe NM7; the gate of the fifth PMOS PM5, the gate of the sixth PMOS PM6, the gate of the fifth NMOS PM5, and the gate of the sixth NMOS NM6 are connected to the input end of the first trigger unit 220, the source of the fifth PMOS PM5 and the gate of the fifth PMOS PM5 are connected to VDD, and the source of the fifth NMOS NM5 and the gate of the fifth NMOS NM5 are connected to VSS; the drain electrode of the fifth PMOS pipe PM5 is connected to the source electrode of the sixth PMOS pipe PM6 and the source electrode of the seventh PMOS pipe PM7, the gate electrode of the sixth PMOS pipe PM6 and the gate electrode of the seventh PMOS pipe PM7 are connected to VDD, the drain electrode of the seventh PMOS pipe PM7 is connected to VSS, the drain electrode of the sixth PMOS pipe PM6 is connected to the drain electrode of the sixth NMOS pipe NM6, the source electrode of the sixth NMOS pipe NM6 is connected to the drain electrode of the fifth NMOS pipe NM5 and the source electrode of the seventh NMOS pipe NM7, the gate electrode of the sixth NMOS pipe NM6 and the gate electrode of the seventh NMOS pipe NM7 are connected to VSS, the drain electrode of the seventh NMOS pipe NM7 is connected to VDD, and the drain electrode of the sixth PMOS pipe PM6, the gate electrode of the seventh PMOS pipe PM7 and the gate electrode of the seventh NMOS pipe NM7 are all connected to the output end of the first trigger unit for outputting the second clock signal I2.
In some embodiments, since the charge-discharge speed of the first charge-discharge unit 210 is determined by the current and the capacitance, the charge-discharge speed does not change with the power voltage, and the resistance change of the first inverter in the first charge-discharge unit 210 is small, the generated delay change is negligible. However, the trigger threshold of the latter first offending unit is linearly proportional to the power supply voltage, so that the delay time generated by the first charge and discharge unit 200 increases as the power supply voltage increases.
In some embodiments, the second delay module 300 includes a second charge and discharge unit 310 and a second trigger unit 320; the second charge-discharge unit 310 is configured to receive the second clock signal I2 and a constant current output by the current source, and perform charge-discharge based on a power supply voltage and the constant current to implement delay of the second clock signal I2; the second trigger unit 320 is configured to form hysteresis, and when a voltage value achieved by charging and discharging reaches a trigger threshold of the second trigger unit 320, the second trigger unit 320 is turned on, and the second trigger unit 320 outputs a third clock signal; wherein, as the power supply voltage increases, the resistance of the second charge and discharge unit 310 becomes smaller so that the delay time is reduced, the trigger threshold of the second trigger unit 320 becomes larger so that the delay time is increased, and the delay reduction ratio of the second charge and discharge unit 310 is greater than the delay increase ratio of the second trigger unit 320, so that the delay time of the second delay module 300 can be reduced as the power supply voltage increases.
In some embodiments, the second charge-discharge unit 310 includes at least one stage of second inverters and corresponding second capacitors in cascade; the input end of the second clock signal is connected with the input end of the first-stage second inverter, the input end of the second trigger unit is connected with the output end of the last-stage second inverter, and the output end of the previous-stage second inverter is connected with the input end of the next-stage second inverter; the output end of the first inverter is connected with a corresponding first capacitor, and the corresponding second capacitor is charged and discharged based on constant current to realize time delay.
In some embodiments, the second inverter is an inverter Guan Fanxiang, the inverter is an inverter with a comparison tube, the dimensions of PMOS and NMOS in the inverter are different from the W/L >1 in the common standard cell inverter, in the dimensions of PMOS and NMOS of an inverter, W/L is often much smaller than 1, which essentially uses MOS transistors as a nonlinear resistor. Then, when the corresponding PMOS or NMOS is turned on, the nonlinear resistor charges or discharges the following load capacitor, thereby generating a relatively considerable delay time. Meanwhile, the resistance of the inverted ratio tube is larger than that of a MOS tube of a normal ratio column, and the short-circuit current generated by the simultaneous conduction of the inverter is much smaller, so that the design of low power consumption is realized. And because the MOS tube has the characteristic that the resistance of the MOS tube is reduced along with the increase of the power supply voltage, R in the delay time constant RC of the circuit is equivalent to being reduced along with the increase of the power supply voltage, namely the delay of the inverted-ratio tube inverter is reduced along with the increase of the power supply voltage, so that the resistance of the second charge-discharge unit is reduced along with the increase of the power supply voltage, and the delay time is reduced.
In some embodiments, according to the delay requirement, the delay time can be adjusted by adjusting the size of the inverted MOS transistor resistor and the size of the load capacitor, or using 1 stage or multiple stages, so as to flexibly meet the delay requirement. Specifically, the delay time of the delay stage of the inverse ratio Guan Fanxiang device can be adjusted by adjusting the proportion of the inverse ratio tube inverter to adjust the resistance of the MOS tube, flexible to meet the delay requirement.
In some embodiments, the second charge-discharge unit includes a first stage second inverter, a second stage second inverter, and second capacitors respectively corresponding to the first stage second inverter, where the first stage second inverter includes an eighth PMOS pipe PM8 and an eighth NMOS pipe NM8, a gate of the eighth PMOS pipe PM8 and a gate of the eighth NMOS pipe NM8 are used as input ends of the first stage second inverter, a gate of the eighth PMOS pipe PM8 is connected to VDD, a gate of the eighth NMOS pipe NM8 is connected to VSS, a source of the eighth PMOS pipe PM8 is connected to a first current source end, a source of the eighth NMOS pipe NM8 is connected to a fourth current source end, a gate of the eighth PMOS pipe PM8 is connected to VDD, a gate of the eighth NMOS pipe NM8 is connected to VSS, a drain of the eighth PMOS pipe PM8 is connected to a drain of the eighth NMOS pipe PM8, one end of the corresponding first stage second capacitor C2 and an input end of the second stage second inverter, and another end of the second capacitor C2 is connected to VDD or VSS; the second-stage second inverter comprises a ninth PMOS tube PM9 and a ninth NMOS tube NM9, wherein a source electrode of the ninth PMOS tube PM9 is connected with a first power supply source end, a source electrode of the ninth NMOS tube NM9 is connected with a fourth power supply source end, a grid electrode of the ninth PMOS tube PM9 and a grid electrode of the ninth NMOS tube NM9 serve as input ends of the second-stage second inverter, a grid electrode of the ninth PMOS tube PM9 is connected with VDD, a grid electrode of the ninth NMOS tube NM9 is connected with VSS, a drain electrode of the ninth PMOS tube PM9 is connected with a drain electrode of the ninth NMOS tube NM9, one end of a second-stage second capacitor C3 and an output end of the second-stage second inverter, and the other end of the second-stage second capacitor C3 is connected with VSS or VDD.
In some embodiments, because the inverted tube has a relatively large resistance, the rising and falling speeds of the output point of the inverted tube inverter are relatively slow, and the output point is susceptible to noise and interference, and a first-stage second trigger unit is required to be added later to form hysteresis so as to resist the influence of noise and interference. In an embodiment, the second trigger unit may be a schmitt trigger. In some embodiments, the second trigger unit includes a tenth PMOS pipe PM10, an eleventh PMOS pipe PM11, a twelfth PMOS pipe PM12, a tenth NMOS pipe NM10, an eleventh NMOS pipe NM11, and a twelfth NMOS pipe NM12; the gate of the tenth PMOS PM10, the gate of the eleventh PMOS PM11, the gate of the fifth NMOS PM5, and the gate of the eleventh NMOS NM11 are connected to the input end of the second trigger unit 220, the source of the tenth PMOS PM10 and the gate of the tenth PMOS PM10 are connected to VDD, and the source of the tenth NMOS NM10 and the gate of the tenth NMOS NM10 are connected to VSS; the drain electrode of the tenth PMOS pipe PM10 is connected to the source electrode of the eleventh PMOS pipe PM11 and the source electrode of the twelfth PMOS pipe PM12, the gate electrode of the eleventh PMOS pipe PM11 and the gate electrode of the twelfth PMOS pipe PM12 are connected to VDD, the drain electrode of the twelfth PMOS pipe PM12 is connected to VSS, the drain electrode of the eleventh PMOS pipe PM11 is connected to the drain electrode of the eleventh NMOS pipe NM11, the source electrode of the eleventh NMOS pipe NM11 is connected to the drain electrode of the tenth NMOS pipe NM10 and the source electrode of the twelfth NMOS pipe NM12, the gate electrode of the eleventh NMOS pipe NM11 and the gate electrode of the twelfth NMOS pipe NM12 are connected to VSS, the drain electrode of the twelfth NMOS pipe NM12 is connected to VDD, and the drain electrode of the eleventh PMOS pipe PM11, the gate electrode of the twelfth PMOS pipe PM12 and the gate electrode of the twelfth NMOS pipe NM12 are all connected to the output end of the second trigger unit for outputting the third clock signal I3.
In some embodiments, the first capacitor C1 and the second capacitor C2 may use any form of capacitor in the process, which may be a metal capacitor, a poly capacitor, a mos capacitor, and the like, and the other end of which may be grounded and may be powered.
In some embodiments, referring to fig. 1, the delay circuit further includes a low current reference generating unit 100; the low current reference generating unit is used for generating a current source which is stable along with the change of the power supply voltage and outputting the current source to the first delay module and the second delay module. In some embodiments, the low current reference generating unit 100 includes a first PMOS tube PM1, a second PMOS tube PM2, a first NMOS tube NM1, a second NMOS tube NM2, and a first resistor R1, where a source of the first PMOS tube PM1 is connected to a source of the second PMOS tube PM2 and a first current source terminal for outputting a constant current, gates of the first PMOS tube PM1 and the second PMOS tube PM2 are both connected to VDD, a drain of the first PMOS tube PM1 is connected to a drain of the first NMOS tube NM1, a gate of the first PMOS tube PM1, a gate of the second PMOS tube PM2, and a second current source terminal for outputting a constant current, and a drain of the second PMOS tube PM2 is connected to a drain of the second NMOS tube NM 2; the grid electrode of the first NMOS tube NM1 and the grid electrode of the second NMOS tube NM2 are both connected with VSS, the drain electrode of the second NMOS tube NM2 is connected with a third power supply end for outputting a current source, the grid electrode of the first NMOS tube NM1 and the grid electrode of the second NMOS tube NM2, the source electrode of the first NMOS tube NM1 is connected with one end of a first resistor R1, and the other end of the first resistor R1 is connected with the source electrode of the second NMOS tube NM 2.
In some embodiments, the first resistor R1 may be any resistor type in a standard CMOS process, or even a MOS device as a resistor, but using poly resistors in the process, the variation with process, voltage, and temperature is much smaller.
In some embodiments, referring to fig. 1, the delay circuit further includes an output driving unit 400; the output driving unit is configured to receive the third clock signal I3 and increase driving capability of the third clock signal I3, so as to drive an external load. The specific driving may be a single-stage inverter or a multi-stage inverter, and the driving capability may also be determined according to the actual driving load, and the driving unit shown in fig. 1 includes, as only one example, a two-stage inverter, which is a third inverter and a fourth inverter, respectively, where the third inverter includes a thirteenth PMOS power transistor PM13 and a thirteenth NMOS power transistor NM13, and the fourth inverter includes a fourteenth PMOS power transistor PM14 and a fourteenth NMOS power transistor NM14, and is amplified by the two-stage inverter and used for driving an external load.
While the invention has been described in terms of preferred embodiments, it is not intended to be limiting, but rather, it will be apparent to those skilled in the art that variations and modifications can be made to the invention in light of the above teachings without departing from the spirit or scope of the invention, therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention fall within the protection scope of the technical solution of the present invention.

Claims (8)

1. The delay circuit is characterized by comprising a first delay module and a second delay module; the first delay module is used for receiving the first clock signal for delay, obtaining a second clock signal and outputting the second clock signal to the second delay module; the second delay module is used for receiving the second clock signal to delay, obtaining a third clock signal and outputting the third clock signal;
the delay time of the first delay module is increased along with the increase of the power supply voltage, the delay time of the second delay module is reduced along with the increase of the power supply voltage, and the delay increasing ratio of the first delay module is consistent with the delay decreasing ratio of the second delay module;
the first delay module comprises a first charge-discharge unit and a first trigger unit; the first charge and discharge unit is used for receiving the constant current output by the first clock signal and the current source, obtaining a low current reference after limiting the constant current, and realizing time delay of the first clock signal by charging and discharging based on the power supply voltage and the low current reference;
the first trigger unit is used for forming hysteresis, and when the voltage value achieved by charging and discharging reaches the trigger threshold value of the first trigger unit, the first trigger unit is started, and the first trigger unit outputs a second clock signal to the second delay module; wherein, as the power supply voltage increases, the trigger threshold of the first trigger unit becomes larger so as to increase the delay time;
the second delay module comprises a second charge-discharge unit and a second trigger unit;
the second charge-discharge unit is used for receiving the second clock signal and constant current output by the current source, and carrying out charge-discharge based on the power supply voltage and the constant current to realize delay of the second clock signal;
the second trigger unit is used for forming hysteresis, and when the voltage value achieved by charging and discharging reaches the trigger threshold value of the second trigger unit, the second trigger unit is started, and the second trigger unit outputs a third clock signal; wherein as the power supply voltage increases, the resistance of the second charge-discharge unit becomes smaller so as to reduce the delay time, the trigger threshold of the second trigger unit becomes larger so as to increase the delay time, and the delay time reduction ratio of the second charge-discharge unit is larger than the delay time increase ratio of the second trigger unit.
2. The delay circuit of claim 1 wherein the first charge-discharge unit comprises a first current limiting unit, a second current limiting unit, a first inverter and a first capacitor corresponding to the first inverter, a first clock signal input terminal connected to a first input terminal of the first inverter; the first current limiting unit and the second current limiting unit are used for limiting the input current source so as to respectively provide a low current reference for the second input end and the third input end of the corresponding first inverter, and the output end of the first inverter is connected with the corresponding first capacitor so as to realize time delay by charging and discharging the corresponding first capacitor based on the low current reference.
3. The delay circuit with stable power supply voltage variation according to claim 2, wherein the first current limiting unit comprises a third PMOS tube PM3, the second current limiting unit comprises a third NMOS tube NM3, the first inverter comprises a fourth PMOS tube PM4 and a fourth NMOS tube NM4, a source electrode of the third PMOS tube PM3 is connected to a first current source terminal, a gate electrode of the third PMOS tube PM3 is connected to a second current source terminal and VDD, a drain electrode of the third PMOS tube PM3 is connected to a source electrode of the fourth PMOS tube PM4, a gate electrode of the fourth PMOS tube PM4 and a gate electrode of the fourth NMOS tube NM4 are used as input terminals of the first inverter, a gate electrode of the fourth PMOS tube PM4 is connected to VDD, a gate electrode of the fourth NMOS tube NM4 is connected to VSS, a source electrode of the fourth PMOS tube PM4 is connected to a drain electrode of the third NMOS tube NM3, one end of the first capacitor C1 and an output terminal of the first inverter NMOS, and a gate electrode of the third PMOS tube PM4 is connected to a third current source terminal of the fourth NMOS tube NM 3; the other end of the first capacitor C1 is connected with VSS or VDD.
4. The delay circuit of claim 1 wherein the second charge-discharge unit comprises at least one stage of second inverter and a corresponding second capacitor in cascade; the input end of the second clock signal is connected with the input end of the first-stage second inverter, the input end of the second trigger unit is connected with the output end of the last-stage second inverter, and the output end of the previous-stage second inverter is connected with the input end of the next-stage second inverter; the output end of the second inverter is connected with the corresponding first capacitor, so that the corresponding second capacitor is charged and discharged based on constant current to realize time delay; wherein the second inverter is an inverted-ratio tube inverter.
5. The delay circuit of claim 4, wherein the second charge-discharge unit comprises a cascaded first-stage second inverter, a second-stage second inverter and second capacitors corresponding to the second-stage second inverter, the first-stage second inverter comprises an eighth PMOS pipe PM8 and an eighth NMOS pipe NM8, the gate of the eighth PMOS pipe PM8 and the gate of the eighth NMOS pipe NM8 are used as input ends of the first-stage second inverter, the gate of the eighth PMOS pipe PM8 is connected to VDD, the gate of the eighth NMOS pipe NM8 is connected to VSS, the source of the eighth PMOS pipe PM8 is connected to a first current source end, the source of the eighth NMOS pipe NM8 is connected to a fourth current source end, the gate of the eighth PMOS pipe PM8 is connected to VDD, the gate of the eighth NMOS pipe NM8 is connected to VSS, the drain of the eighth PMOS pipe PM8 is connected to the drain of the eighth NMOS pipe PM8, the corresponding first-stage second capacitor C2 and the second capacitor C2 of the second stage are connected to VSS or the other end of the second capacitor C2;
the second-stage second inverter comprises a ninth PMOS tube PM9 and a ninth NMOS tube NM9, wherein a source electrode of the ninth PMOS tube PM9 is connected with a first power supply source end, a source electrode of the ninth NMOS tube NM9 is connected with a fourth power supply source end, a grid electrode of the ninth PMOS tube PM9 and a grid electrode of the ninth NMOS tube NM9 serve as input ends of the second-stage second inverter, a grid electrode of the ninth PMOS tube PM9 is connected with VDD, a grid electrode of the ninth NMOS tube NM9 is connected with VSS, a drain electrode of the ninth PMOS tube PM9 is connected with a drain electrode of the ninth NMOS tube NM9, one end of a second-stage second capacitor C3 and an output end of the second-stage second inverter, and the other end of the second-stage second capacitor C3 is connected with VSS or VDD.
6. The delay circuit of claim 1, further comprising: a low current reference generating unit;
the low current reference generating unit is used for generating a current source which is stable along with the change of the power supply voltage and outputting the current source to the first delay module and the second delay module.
7. The delay circuit of claim 1, further comprising: an output driving unit;
the output driving unit is used for receiving the third clock signal and improving the driving capability of the third clock signal so as to drive an external load.
8. A chip comprising the delay circuit of any one of claims 1-7 that is stable with variations in supply voltage.
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