CN111669175B - Frequency division circuit and chip - Google Patents
Frequency division circuit and chip Download PDFInfo
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- CN111669175B CN111669175B CN202010579652.0A CN202010579652A CN111669175B CN 111669175 B CN111669175 B CN 111669175B CN 202010579652 A CN202010579652 A CN 202010579652A CN 111669175 B CN111669175 B CN 111669175B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses a frequency division circuit and a chip, wherein the frequency division circuit comprises a first inversion unit, a second inversion unit and a third inversion unit; the input of first inverting unit is connected with the signal source output, the output of first inverting unit is connected with the input of second inverting unit, the output of second inverting unit is connected with the input of third inverting unit, the output of third inverting unit is connected with the signal source output, first inverting unit, second inverting unit and third inverting unit are all supplied with power through a power supply, digital frequency division circuit can be realized through the three-stage inverting unit, compared with the prior art, the use quantity of electronic elements is reduced, thereby saving the chip area and reducing the overall power consumption.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a divide-by-two circuit and a chip.
Background
With the continuous progress of CMOS (Complementary Metal Oxide Semiconductor) integrated circuit technology, the circuit scale of a single chip is larger and larger, the circuit operating frequency is higher and the performance is better and better. In the field of integrated circuits, a digital divide-by-two circuit is a common circuit unit, and is used for dividing the frequency of an input high-low level square wave signal with a certain frequency by 2 to obtain an output signal with one half of the frequency of the input signal.
In the prior art, the most commonly used implementation manner of the digital divide-by-two circuit is to use a D flip-flop, and more transistors are needed in the transistor stage circuit, although the circuit structure is not complex, in consideration of the wide application of the digital divide-by-two circuit, thousands of such circuits are usually used in one integrated circuit chip, and then the divide-by-two circuit generally consumes a larger chip area and power consumption.
Disclosure of Invention
In order to solve the technical problems, the invention provides a frequency division circuit and a chip, which can reduce the number of electronic elements, save the area of the chip and reduce the overall power consumption.
The invention provides a frequency division circuit, which comprises a first inversion unit, a second inversion unit and a third inversion unit;
the input end of the first inverting unit is connected with the signal source output end, the output end of the first inverting unit is connected with the input end of the second inverting unit, the output end of the second inverting unit is connected with the input end of the third inverting unit, the output end of the third inverting unit is connected with the signal source output end, and the first inverting unit, the second inverting unit and the third inverting unit are powered by a power supply.
Preferably, the first inverting unit comprises a first PMOS tube, a first NMOS tube and a second PMOS tube;
the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and is used as the input end of the first inverting unit, the source electrode of the first PMOS tube is connected with the power supply, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube;
the source of the first NMOS tube is connected with the ground wire, and the drain of the first NMOS tube is connected with the drain of the second PMOS tube and is used as the output end of the first inverting unit;
and the grid electrode of the second PMOS tube is connected with an input clock signal.
Preferably, the second inverting unit comprises a second NMOS tube, a third NMOS tube and a third PMOS tube;
the grid electrode of the second NMOS tube is used as the input end of the second inverting unit, the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube and is used as the output end of the second inverting unit;
the grid electrode of the third NMOS tube is connected with the input clock signal, and the source stage of the third NMOS tube is connected with a ground wire;
and the grid electrode of the third PMOS tube is connected with the input clock signal, and the source stage of the third PMOS tube is connected with the power supply.
Preferably, the third inverting unit comprises a fourth NMOS tube, a fourth PMOS tube and a fifth NMOS tube;
the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fourth PMOS tube and is used as the input end of the third inverting unit, the source electrode of the fourth NMOS tube is connected with the ground wire, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the fifth NMOS tube;
the source stage of the fourth PMOS tube is connected with the power supply, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth NMOS tube and is used as the output end of the third inverting unit;
and the grid electrode of the fifth NMOS tube is connected with the input clock signal.
Preferably, the first inverting unit further includes a first resistor connected between the drain of the first PMOS transistor and the source of the second PMOS transistor.
Preferably, the second inverting unit further includes a second resistor connected between a source of the second NMOS transistor and a drain of the third NMOS transistor.
Preferably, the third inverting unit further includes a third resistor connected between the drain of the fourth PMOS transistor and the drain of the fifth NMOS transistor.
In another aspect, the present invention provides a chip comprising a divide-by-two circuit as described in any one of the above.
The invention has at least the following beneficial effects:
the invention is connected with the signal source output end through the input end of the first inverting unit, the output end of the first inverting unit is connected with the input end of the second inverting unit, the output end of the second inverting unit is connected with the input end of the third inverting unit, the output end of the third inverting unit is connected with the signal source output end, and the digital frequency division circuit can be realized through the three-stage inverting unit.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a prior art divide-by-two circuit;
FIG. 2 is a circuit diagram of a prior art divide-by-two circuit;
FIG. 3 is a circuit configuration diagram of a divide-by-two circuit according to an embodiment of the present invention;
fig. 4 is a circuit configuration diagram of another divide-by-two circuit according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a frequency division circuit and a chip, which can realize the digital frequency division circuit through three-stage reverse phase units, thereby reducing the use quantity of electronic elements, saving the area of the chip and reducing the overall power consumption.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 shows a block diagram of a prior art divide-by-two circuit, which is essentially a D flip-flop with positive and negative outputs, whose negative output terminal Qb is connected to its D terminal, the digital signal CLKIN to be divided is connected to its clock input terminal Clk, and whose Q terminal is connected to the divide-by-two signal output CLKOUT. The working principle is that when the rising edge of CLKIN comes, the Q end output of the D trigger is updated to the current Qb output, and the high and low levels of the Q end are inverted. Every two rising edges of CLKIN, Q completes a low-to-high (or high-to-low) cycle. I.e., every two rising edges of CLKIN correspond to one rising edge of CLKOUT, and thus CLKOUT completes the frequency division of CLKIN.
The transistor stage circuit corresponding to the divide-by-two circuit is shown in fig. 2, and it can be seen that the circuit uses 13 NMOS transistors, 13 PMOS transistors, and 26 MOS transistors in total. Although a 26-transistor circuit is not complex, given the wide range of applications for digital divide-by-two circuits, thousands of such circuits are typically used in an integrated circuit chip, and the divide-by-two circuit generally consumes a large chip area and power consumption.
In view of this, an aspect of the present invention provides a divide-by-two circuit, please refer to fig. 3, which includes: a first inverting unit, a second inverting unit, and a third inverting unit;
the input end of the first inverting unit is connected with the signal source output end Vout, the output end of the first inverting unit is connected with the input end of the second inverting unit, the output end of the second inverting unit is connected with the input end of the third inverting unit, the output end of the third inverting unit is connected with the signal source output end Vout, and the first inverting unit, the second inverting unit and the third inverting unit are powered by a power supply VDD.
In the embodiment of the invention, the input end of the first inverting unit is connected with the signal source output end Vout, the output end of the first inverting unit is connected with the input end of the second inverting unit, the output end of the second inverting unit is connected with the input end of the third inverting unit, the output end of the third inverting unit is connected with the signal source output end Vout, and the digital frequency division circuit can be realized through the three-stage inverting unit.
In specific implementation, the first inverting unit comprises a first PMOS tube M1, a first NMOS tube M2 and a second PMOS tube M3; the second inverting unit comprises a second NMOS tube M4, a third NMOS tube M5 and a third PMOS tube M6; the third inverting unit comprises a fourth NMOS tube M7, a fourth PMOS tube M8 and a fifth NMOS tube M9.
In the first inversion unit: the grid electrode of the first PMOS tube M1 is connected with the grid electrode of the first NMOS tube M2 and is used as the input end of the first inverting unit, the first inverting unit is connected with the signal source output end Vout, the source stage of the first PMOS tube M1 is connected with the power supply VDD, and the drain electrode of the first PMOS tube M1 is connected with the source electrode of the second PMOS tube M3; the source of the first NMOS tube M2 is connected with the ground wire, and the drain of the first NMOS tube M2 is connected with the drain of the second PMOS tube M3 and is used as the output end of the first inverting unit; the grid electrode of the second PMOS tube M3 is connected with an input clock signal Vin.
In the second inverting unit: the grid electrode of the second NMOS tube M4 is used as the input end of the second inverting unit, the source stage of the second NMOS tube M4 is connected with the drain electrode of the third NMOS tube M5, and the drain electrode of the second NMOS tube M4 is connected with the drain electrode of the third PMOS tube M6 and is used as the output end of the second inverting unit; the grid electrode of the third NMOS tube M5 is connected with an input clock signal Vin, and the source stage of the third NMOS tube M5 is connected with a ground wire; the grid electrode of the third PMOS tube M6 is connected with an input clock signal Vin, and the source stage of the third PMOS tube M6 is connected with a power supply VDD.
In the third inversion unit: the grid electrode of the fourth NMOS tube M7 is connected with the grid electrode of the fourth PMOS tube M8 and is used as the input end of the third inverting unit, the source stage of the fourth NMOS tube M7 is connected with the ground wire, and the drain electrode of the fourth NMOS tube M7 is connected with the source electrode of the fifth NMOS tube M9; the source stage of the fourth PMOS tube M8 is connected with a power supply VDD, the drain electrode of the fourth PMOS tube M8 is connected with the drain electrode of the fifth NMOS tube M9 and is used as the output end of the third inverting unit, and the output end of the third inverting unit is connected with the signal source output end Vout; the gate of the fifth NMOS transistor M9 is connected to the input clock signal Vin.
In the embodiment of the invention, the working principle of the frequency division circuit is as follows:
for convenience of description, an output terminal of the first inverting unit is defined as a node V1, an output terminal of the second inverting unit is defined as a node V2, and an output terminal of the third inverting unit is defined as a node Vout.
When the input clock signal Vin is at a low level, the third NMOS transistor M5 and the fifth NMOS transistor M9 are turned off, the second PMOS transistor M3 and the third PMOS transistor M6 are turned on, and the node V2 is connected to VDD and is at a high level. The fourth PMOS transistor M8 is turned off under the high level of the node V2, and the node Vout is in a high-resistance state no matter reaching ground or VDD, and at this time, the output signal Vout maintains a level state before the input clock signal Vin is low (i.e., before the falling edge of the input clock signal Vin). When the rising edge of the input clock signal Vin comes, the second PMOS transistor M3 and the third PMOS transistor M6 are turned off, and the third NMOS transistor M5 and the fifth NMOS transistor M9 are turned on. At this time (i.e., at the moment when the rising edge of the input clock signal Vin comes), if the output signal Vout is at a high level, the first PMOS transistor M1 is turned off, the first NMOS transistor M2 is turned on, the node V1 becomes at a low level, the second NMOS transistor M4 is turned off, and the node V2 is in a high-resistance state, and the level thereof is in a state before the rising edge of the input clock signal Vin comes, so that it is still at a high level. At this time, the fourth NMOS transistor M7 and the fifth NMOS transistor M9 are turned on, the fourth PMOS transistor M8 is turned off, and the output signal Vout is connected to ground through the fifth NMOS transistor M9 and the fourth NMOS transistor M7, and changes to a low level. If the rising edge of the input clock signal Vin comes, the output signal Vout is at a low level, the first NMOS transistor M2 is turned off, the first PMOS transistor M1 and the second PMOS transistor M3 are turned on, the node V1 is at a high level, the second NMOS transistor M4 is turned on, after the input clock signal Vin becomes at a high level, the third PMOS transistor M6 is turned off, the third NMOS transistor M5 is turned on, the node V2 is connected to the ground through the second NMOS transistor M4 and the third NMOS transistor M5, and is changed to a low level, the fourth PMOS transistor M8 is turned on, the fourth NMOS transistor M7 is turned off, and the output signal Vout becomes at a high level.
As can be seen from the above description, the state of the level of the output signal Vout is inverted once if and only if the rising edge of the input clock signal Vin comes. That is, one rising edge of the output signal Vout corresponds to two rising edges of the input clock signal Vin, and the output signal Vout is a binary signal of the input clock signal Vin. Therefore, the embodiment of the invention can realize the digital signal frequency division function as the prior art by using only 9 MOS tubes, and reduces the use quantity of the MOS tubes, thereby saving the chip area and reducing the overall power consumption.
As a preferred embodiment of the present invention, referring to fig. 4, the first inverting unit further includes a first resistor R1 connected between the drain of the first PMOS transistor M1 and the source of the second PMOS transistor M3; the second inverting unit further comprises a second resistor R2 connected between the source of the second NMOS tube M4 and the drain of the third NMOS tube M5; the third inverting unit further includes a third resistor R3 connected between the drain of the fourth NMOS transistor M7 and the source of the fifth NMOS transistor M9.
In the embodiment of the invention, the first resistor R1, the second resistor R2 and the third resistor R3 respectively have the function of reducing the leakage effect of the node V1, the node V2 and the node Vout, thereby reducing the possibility of failure of the frequency divider. The mechanism of reducing the leakage effect will be described below using the third resistor R3 as an example.
When the input clock signal Vin is at a low level, the node Vout is in a high-impedance state, so that the output signal Vout maintains its state immediately before the falling edge of the input clock signal Vin. However, since the gate of the fourth NMOS transistor M7 is at a high level and is in a conductive state, and since the fourth NMOS transistor M7 and the fifth NMOS transistor M9 are in a series state, the fourth NMOS transistor M7 and the fifth NMOS transistor M9 need to be made larger than the fourth PMOS transistor M8 in size to meet the speed, so that the possibility of leakage of the fourth NMOS transistor M7 and the fifth NMOS transistor M9 is high, especially at high temperature. If the fourth NMOS transistor M7 and the fifth NMOS transistor M9 leak, the output signal Vout will become low level, and if the output signal Vout should remain high level at this time, the output signal Vout will flip in advance when the input clock signal Vin is low level, so as to generate a logic error. By setting the third resistor R3, once the fourth NMOS transistor M7 and the fifth NMOS transistor M9 leak, the voltage at the upper end of the third resistor R3 will rise, so that the voltage at the gate-source electrode of the fifth NMOS transistor M9 becomes a negative value from 0, the channel resistance of the fifth NMOS transistor M9 is further increased, and the leakage current in the channel of the fifth NMOS transistor M9 is greatly reduced, thereby reducing the possibility of early inversion of the output signal Vout.
Besides the node Vout, the node V1 and the node V2 may leak electricity, so the first resistor R1 and the second resistor R2 are correspondingly disposed, and the mechanism for suppressing the leakage effect is similar to that of the third resistor R3, which is not described herein again.
It should be noted that, in the implementation of the present invention, the resistances of the first resistor R1, the second resistor R2 and the third resistor R3 generally only need to be of a hundred ohm magnitude, so that the sizes of the first resistor R1, the second resistor R2 and the third resistor R3 are almost the same as the sizes of the MOS transistors in the integrated circuit, and do not occupy too much chip area.
According to the frequency division circuit provided by the embodiment of the invention, through the circuit structure design, the digital frequency division circuit is realized only by using 9 MOS tubes and 3 resistors which are almost the same as the MOS tubes in size, and compared with the prior art, the frequency division circuit reduces the use quantity of electronic elements, thereby saving the area of a chip and reducing the overall power consumption; and by arranging the first resistor R1, the second resistor R2 and the third resistor R3, the leakage effect of the node V1, the node V2 and the node Vout can be obviously restrained, so that the possibility of failure of the frequency divider is reduced.
In another aspect, the embodiment of the present invention further provides a chip including the divide-by-two circuit according to any one of the embodiments above.
For details of the divide-by-two circuit, reference may be made to the description of the embodiments above.
It will be appreciated that the chip in this embodiment integrates the divide-by-two circuit of the above embodiment and therefore has the same benefits as the divide-by-two circuit of the above.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. The frequency division circuit is characterized by comprising a first inverting unit, a second inverting unit and a third inverting unit;
the input end of the first inverting unit is connected with the output end of the signal source, the output end of the first inverting unit is connected with the input end of the second inverting unit, the output end of the second inverting unit is connected with the input end of the third inverting unit, the output end of the third inverting unit is connected with the output end of the signal source, and the first inverting unit, the second inverting unit and the third inverting unit are powered by a power supply;
the first inverting unit comprises a first PMOS tube, a first NMOS tube and a second PMOS tube;
the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and is used as the input end of the first inverting unit, the source electrode of the first PMOS tube is connected with the power supply, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube;
the source of the first NMOS tube is connected with the ground wire, and the drain of the first NMOS tube is connected with the drain of the second PMOS tube and is used as the output end of the first inverting unit;
the grid electrode of the second PMOS tube is connected with an input clock signal;
the second inverting unit comprises a second NMOS tube, a third NMOS tube and a third PMOS tube;
the grid electrode of the second NMOS tube is used as the input end of the second inverting unit, the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube and is used as the output end of the second inverting unit;
the grid electrode of the third NMOS tube is connected with the input clock signal, and the source stage of the third NMOS tube is connected with a ground wire;
the grid electrode of the third PMOS tube is connected with the input clock signal, and the source stage of the third PMOS tube is connected with the power supply;
the third inverting unit comprises a fourth NMOS tube, a fourth PMOS tube and a fifth NMOS tube;
the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fourth PMOS tube and is used as the input end of the third inverting unit, the source electrode of the fourth NMOS tube is connected with the ground wire, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the fifth NMOS tube;
the source stage of the fourth PMOS tube is connected with the power supply, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth NMOS tube and is used as the output end of the third inverting unit;
and the grid electrode of the fifth NMOS tube is connected with the input clock signal.
2. The divide-by-two circuit of claim 1, wherein the first inverting unit further comprises a first resistor connected between a drain of the first PMOS transistor and a source of the second PMOS transistor.
3. The divide-by-two circuit of claim 1, wherein the second inverting unit further comprises a second resistor connected between a source of the second NMOS transistor and a drain of the third NMOS transistor.
4. The divide-by-two circuit of claim 1, wherein the third inverting unit further comprises a third resistor connected between the drain of the fourth NMOS transistor and the source of the fifth NMOS transistor.
5. A chip comprising a divide-by-two circuit as claimed in any one of claims 1 to 4.
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| CN202010579652.0A CN111669175B (en) | 2020-06-23 | 2020-06-23 | Frequency division circuit and chip |
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| CN202010579652.0A CN111669175B (en) | 2020-06-23 | 2020-06-23 | Frequency division circuit and chip |
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| CN111669175B true CN111669175B (en) | 2023-12-29 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355234A (en) * | 2010-05-26 | 2012-02-15 | 精工爱普生株式会社 | Division circuit, division device, and electronic apparatus |
| CN103873047A (en) * | 2014-03-18 | 2014-06-18 | 华为技术有限公司 | Two-divided-frequency device and high-speed multiplexer |
| CN110474635A (en) * | 2019-08-22 | 2019-11-19 | 河源广工大协同创新研究院 | A kind of frequency dividing circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE60209197T2 (en) * | 2002-04-04 | 2006-09-07 | Texas Instruments Inc., Dallas | Phase locked loop with a charge pump |
| US6963250B2 (en) * | 2003-11-20 | 2005-11-08 | International Business Machines Corporation | Voltage controlled oscillator with selectable frequency ranges |
| US10250269B2 (en) * | 2017-07-24 | 2019-04-02 | Nxp B.V. | Oscillator system |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355234A (en) * | 2010-05-26 | 2012-02-15 | 精工爱普生株式会社 | Division circuit, division device, and electronic apparatus |
| CN103873047A (en) * | 2014-03-18 | 2014-06-18 | 华为技术有限公司 | Two-divided-frequency device and high-speed multiplexer |
| CN110474635A (en) * | 2019-08-22 | 2019-11-19 | 河源广工大协同创新研究院 | A kind of frequency dividing circuit |
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