CN111769826A - TSPC trigger with setting and resetting functions - Google Patents
TSPC trigger with setting and resetting functions Download PDFInfo
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- H—ELECTRICITY
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- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
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Abstract
The invention discloses a TSPC trigger with a setting and resetting function, which consists of seven PMOS transistors, ten NMOS transistors, two inverters and a NAND gate, and has three modes by setting a setting signal and a resetting signal: normal mode, set mode, reset mode. Compared with the traditional static logic D trigger with a setting and resetting function, the TSPC trigger provided by the invention has high working frequency; compared with a TSPC trigger only having a setting function and a TSPC trigger only having a resetting function, the TSPC trigger has the setting and resetting functions at the same time, improves the use flexibility of the TSPC, and is simple in structure and low in implementation complexity.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a True Single Phase Clock (TSPC) trigger with a set reset function.
Background
D flip-flops are widely used in various designs as indispensable sequential logic structures in standard cells. A conventional static logic D flip-flop with a set-reset function is shown in fig. 1, and is composed of four MOS transistors, five inverters, and four nand gates. The trigger has the defects of large quantity of MOS transistors, large occupied layout area and low working frequency. The TSPC trigger adopts dynamic logic and has high working frequency. Based on this, the prior art appears to have a large number of TSPC flip-flops.
The invention patent application with publication number CN 109379061a discloses a TSPC flip-flop with set function, as shown in fig. 2, including: the drain electrode of the seventh NMOS transistor is connected with the node Z, the source electrode of the seventh NMOS transistor is grounded, the grid electrode of the seventh NMOS transistor is used for inputting a signal SET, the seventh NMOS transistor is used as a circuit setting functional device and plays a role in leakage compensation, and the seventh NMOS transistor plays an important role in enlarging the working frequency range of the circuit. However, the flip-flop has disadvantages in that: the device only has a setting function, does not have a resetting function and is limited in use flexibility.
The invention patent application with publication number CN 107528568A discloses a TSPC flip-flop with a data retention feedback loop, as shown in fig. 3, comprising 8 PMOS transistors, Pl, P2, P3, P4, P5, P6, P7, and P8; the NMOS transistors are composed of 7 NMOS transistors, namely Nl, N2, N3, N4, N5, N6 and N7, and 3 inverters INVl, INV2 and INV 3. This flip-flop has no set function, although it has a reset function. And the reset function structure is complex, and the processing cost is high.
Therefore, how to implement a flip-flop with a set-reset function and increase the operating frequency range of the flip-flop is a problem to be solved urgently in the field.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a TSPC trigger with a set reset function. Compared with the traditional static logic D trigger with the set reset function, the trigger has high working frequency; compared with a TSPC trigger only having a setting function and a TSPC trigger only having a resetting function, the TSPC trigger has the setting and resetting functions at the same time, improves the use flexibility of the TSPC, and is simple in structure and low in implementation complexity.
In order to achieve the purpose, the invention adopts the following technical scheme:
a TSPC trigger with a set reset function comprises:
seven PMOS transistors and ten NMOS transistors, wherein sources of the first PMOS transistor PM1, the third PMOS transistor PM3, the fifth PMOS transistor PM5, the sixth PMOS transistor and the seventh PMOS transistor PM7 are each electrically connected to a power supply direct current voltage terminal, the second PMOS transistor PM2 and the first NMOS transistor NM1 are sequentially connected in series between a drain of the first PMOS transistor PM1 and ground, wherein a node connected between a drain of the second PMOS transistor PM2 and a drain of the first NMOS transistor NM1 is a node X, wherein a reset signal C1 is input at a gate of the third PMOS transistor PM3, a set signal SETN is input at a gate of the fifth PMOS transistor PM5, a gate of the first NMOS transistor NM1 and a gate of the first PMOS transistor PM1 are input terminals D of the TSPC flip-flop, a gate of the second NMOS transistor NM2 is connected to the node X and a drain of the fourth PMOS transistor PM4 is electrically connected to a node PM 39y between the second NMOS transistor PM 35 2 and the fourth NMOS transistor PM4, a source of the fourth PMOS transistor PM4 is electrically connected to a drain of the third PMOS transistor PM3, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are sequentially connected in series between a source of the second NMOS transistor NM2 and ground, wherein a gate of the third NMOS transistor NM3 inputs the clock signal CLK, a gate of the fourth NMOS transistor NM4 inputs the reset signal C2, a drain of the fifth NMOS transistor NM5 and a drain of the fifth PMOS transistor PM5 are electrically connected to a node Y and a gate of the sixth PMOS transistor PM6 and a gate of the ninth NMOS transistor NM9 are electrically connected to a node Y, respectively, wherein a source of the fifth NMOS transistor NM5 is grounded and a gate of the set signal is input, a drain of the sixth PMOS transistor PM6 and a drain of the sixth NMOS transistor NM6 are connected and the connected node Z, a gate of the seventh PMOS transistor PM7 and a gate of the tenth NMOS transistor NM10 are electrically connected to the node Z7, and an NM drain of the seventh PMOS transistor PM6 and a drain 10 are connected as a tsq output terminal of the PMOS pc 10, the sixth NMOS transistor NM6 has a seventh NMOS transistor NM7, the drains of the sixth and seventh NMOS transistors NM6 and NM7 electrically connected in parallel, the sources of the sixth and seventh NMOS transistors NM6 and NM7 electrically connected to the drain of the ninth NMOS transistor NM9, and the gate of the seventh NMOS transistor NM7 receives the reset signal C1.
Further, when the input set signal SETN is at a high level, RSTN is at a high level, RST is at a high level, the reset signal C1 is at a low level, and C2 is at a high level, the third PMOS transistor PM3 and the fourth NMOS transistor NM4 are turned on, the fifth PMOS transistor PM5, the fifth NMOS transistor NM5, and the seventh NMOS transistor NM7 are turned off, and at this time, the TSPC flip-flop operates in a normal mode.
Further, when the input set signal SETN is low, RSTN is high, RST is low, the reset signal C1 is high, and C2 is low, the fifth PMOS transistor PM5 and the seventh NMOS transistor NM7 are turned on, the third PMOS transistor PM3, the fifth NMOS transistor NM5, and the fourth NMOS transistor NM4 are turned off, the node Y is high, the node Z is low, the output terminal Q is high, and the TSPC flip-flop operates in the set mode.
Further, when the input set signal SETN is at a high level, RSTN is at a low level, RST is at a high level, the reset signal C1 is at a high level, and C2 is at a low level, the fifth NMOS transistor NM5 and the seventh NMOS transistor NM7 are turned on, the third PMOS transistor PM3, the fifth PMOS transistor PM5, and the fourth NMOS transistor NM4 are turned off, the node Y is at a low level, the node Z is at a high level, the output terminal Q is at a low level, and at this time, the TSPC flip-flop operates in a reset mode.
Compared with the prior art, the TSPC trigger with the setting and resetting functions has the following advantages that:
(1) the TSPC trigger provided by the invention has a setting function and a resetting function, and improves the use flexibility of the TSPC compared with a TSPC trigger only having the setting function and a TSPC trigger only having the resetting function;
(2) compared with the traditional static logic D trigger with a setting and resetting function, the TSPC trigger has high working frequency and effectively improves the working frequency range of the trigger;
(3) compared with the traditional static logic D trigger with the set reset function, the static logic D trigger has the advantages that the number of the adopted MOS transistors is small, and compared with a single TSPC trigger with the set reset function or the reset function, excessive hardware structures are not required to be introduced, so that the occupied layout area is reduced, the realization structure is simple, the realization complexity is low, and the hardware cost is low.
Drawings
FIG. 1 is a circuit schematic of a prior art D flip-flop;
FIG. 2 is a circuit schematic of a prior art TSPC flip-flop with a set function;
FIG. 3 is a circuit schematic of a prior art TSPC flip-flop with reset function;
fig. 4 is a circuit schematic of a TSPC flip-flop with set-reset function of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
As shown in fig. 4, the present embodiment provides a TSPC flip-flop with a set-reset function, including:
seven PMOS transistors and ten NMOS transistors, wherein sources of the first PMOS transistor PM1, the third PMOS transistor PM3, the fifth PMOS transistor PM5, the sixth PMOS transistor and the seventh PMOS transistor PM7 are each electrically connected to a power supply direct current voltage terminal, the second PMOS transistor PM2 and the first NMOS transistor NM1 are sequentially connected in series between a drain of the first PMOS transistor PM1 and ground, wherein a node connected between a drain of the second PMOS transistor PM2 and a drain of the first NMOS transistor NM1 is a node X, wherein a reset signal C1 is input at a gate of the third PMOS transistor PM3 and a set signal SETN is input at a gate of the fifth PMOS transistor PM5, a gate of the first NMOS transistor NM1 and a gate of the first PMOS transistor PM1 are input terminals D of the TSPC flip-flop, a gate of the second NMOS transistor NM2 is connected to the node X and a drain of the fourth PMOS transistor PM4 is electrically connected to a node PM 39y between the second NMOS transistor PM 35 2 and the fourth NMOS transistor PM4, a source of the fourth PMOS transistor PM4 is electrically connected to a drain of the third PMOS transistor PM3, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are sequentially connected in series between a source of the second NMOS transistor NM2 and ground, wherein a gate of the third NMOS transistor NM3 inputs the clock signal CLK, a gate of the fourth NMOS transistor NM4 inputs the reset signal C2, a drain of the fifth NMOS transistor NM5 and a drain of the fifth PMOS transistor PM5 are electrically connected to a node Y and a gate of the sixth PMOS transistor PM6 and a gate of the ninth NMOS transistor NM9 are electrically connected to a node Y, respectively, wherein a source of the fifth NMOS transistor NM5 is grounded and a gate of the set signal is input, a drain of the sixth PMOS transistor PM6 and a drain of the sixth NMOS transistor NM6 are connected and the connected node Z, a gate of the seventh PMOS transistor PM7 and a gate of the tenth NMOS transistor NM10 are electrically connected to the node Z7, and an NM drain of the seventh PMOS transistor PM6 and a drain 10 are connected as a tsq output terminal of the PMOS pc 10, the sixth NMOS transistor NM6 has a seventh NMOS transistor NM7, the drains of the sixth and seventh NMOS transistors NM6 and NM7 electrically connected in parallel, the sources of the sixth and seventh NMOS transistors NM6 and NM7 electrically connected to the drain of the ninth NMOS transistor NM9, and the gate of the seventh NMOS transistor NM7 receives the reset signal C1.
The basic principle of the TSPC trigger with the setting and resetting functions provided by the invention is as follows:
when the input set signal SETN is at a high level, RSTN is at a high level, RST is at a high level, the reset signal C1 is at a low level, and C2 is at a high level, the third PMOS transistor PM3 and the fourth NMOS transistor NM4 are turned on, the fifth PMOS transistor PM5, the fifth NMOS transistor NM5, and the seventh NMOS transistor NM7 are turned off, and at this time, the TSPC flip-flop operates in a normal mode.
When the input set signal SETN is at a low level, RSTN is at a high level, RST is at a low level, the reset signal C1 is at a high level, and C2 is at a low level, the fifth PMOS transistor PM5 and the seventh NMOS transistor NM7 are turned on, the third PMOS transistor PM3, the fifth NMOS transistor NM5, and the fourth NMOS transistor NM4 are turned off, the node Y is at a high level, the node Z is at a low level, the output terminal Q is at a high level, and at this time, the TSPC flip-flop operates in a set mode.
When the input set signal SETN is at a high level, RSTN is at a low level, RST is at a high level, the reset signal C1 is at a high level, and C2 is at a low level, the fifth NMOS transistor NM5 and the seventh NMOS transistor NM7 are turned on, the third PMOS transistor PM3, the fifth PMOS transistor PM5, and the fourth NMOS transistor NM4 are turned off, the node Y is at a low level, the node Z is at a high level, the output terminal Q is at a low level, and at this time, the TSPC flip-flop operates in a reset mode.
That is, the TSPC flip-flop of the present invention can be divided into three modes, i.e. a normal mode, a set mode, and a reset mode:
a normal mode: SETN 1, RSTN 1, RST 1, C1 0, C2 1, PM3 and NM4 are on, PM5, NM5 and NM7 are off, and the functions of SETN and RSTN are consistent with those of ordinary TSPC;
setting mode: SETN is 0, RSTN is 1, RST is 0, C1 is 1, C2 is 0, PM3, NM4, NM5 are off, PM5, NM7 are on, Y is 1, Z is 0, Q is 1, DFF output is set;
resetting mode: SETN is 1, RSTN is 0, RST is 1, C1 is 1, C2 is 0, PM3, NM4, and PM5 are off, NM5 and NM7 are on, Y is 0, Z is 1, Q is 0, and the DFF output is reset.
Therefore, the TSPC trigger with the setting and resetting functions provided by the invention has the setting function and the resetting function, and compared with the TSPC trigger with only the setting function and the TSPC trigger with only the resetting function, the TSPC trigger with the setting and resetting functions improves the use flexibility of the TSPC; compared with the traditional static logic D trigger with a set reset function, the TSPC trigger has high working frequency and effectively improves the working frequency range of the trigger by fully utilizing the advantages of the TSPC; compared with the traditional static logic D trigger with the set reset function, the number of the adopted MOS transistors is small, and the static logic D trigger is compared with a single set or reset function TSPC trigger, excessive hardware structures do not need to be introduced, occupied layout area is reduced, the structure is simple, the complexity is low, and hardware cost is low.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (4)
1. The utility model provides a take TSPC flip-flop of set reset function which characterized in that includes:
seven PMOS transistors and ten NMOS transistors, wherein sources of the first PMOS transistor PM1, the third PMOS transistor PM3, the fifth PMOS transistor PM5, the sixth PMOS transistor and the seventh PMOS transistor PM7 are each electrically connected to a power supply direct current voltage terminal, the second PMOS transistor PM2 and the first NMOS transistor NM1 are sequentially connected in series between a drain of the first PMOS transistor PM1 and ground, wherein a node connected between a drain of the second PMOS transistor PM2 and a drain of the first NMOS transistor NM1 is a node X, wherein a reset signal C1 is input at a gate of the third PMOS transistor PM3, a set signal SETN is input at a gate of the fifth PMOS transistor PM5, a gate of the first NMOS transistor NM1 and a gate of the first PMOS transistor PM1 are input terminals D of the TSPC flip-flop, a gate of the second NMOS transistor NM2 is connected to the node X and a drain of the fourth PMOS transistor PM4 is electrically connected to a node PM 39y between the second NMOS transistor PM 35 2 and the fourth NMOS transistor PM4, a source of the fourth PMOS transistor PM4 is electrically connected to a drain of the third PMOS transistor PM3, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are sequentially connected in series between a source of the second NMOS transistor NM2 and ground, wherein a gate of the third NMOS transistor NM3 inputs the clock signal CLK, a gate of the fourth NMOS transistor NM4 inputs the reset signal C2, a drain of the fifth NMOS transistor NM5 and a drain of the fifth PMOS transistor PM5 are electrically connected to a node Y and a gate of the sixth PMOS transistor PM6 and a gate of the ninth NMOS transistor NM9 are electrically connected to a node Y, respectively, wherein a source of the fifth NMOS transistor NM5 is grounded and a gate of the set signal is input, a drain of the sixth PMOS transistor PM6 and a drain of the sixth NMOS transistor NM6 are connected and the connected node Z, a gate of the seventh PMOS transistor PM7 and a gate of the tenth NMOS transistor NM10 are electrically connected to the node Z7, and an NM drain of the seventh PMOS transistor PM6 and a drain 10 are connected as a tsq output terminal of the PMOS pc 10, the sixth NMOS transistor NM6 has a seventh NMOS transistor NM7, the drains of the sixth and seventh NMOS transistors NM6 and NM7 electrically connected in parallel, the sources of the sixth and seventh NMOS transistors NM6 and NM7 electrically connected to the drain of the ninth NMOS transistor NM9, and the gate of the seventh NMOS transistor NM7 receives the reset signal C1.
2. The TSPC flip-flop according to claim 1, wherein when the input set signal SETN is high, RSTN is high, RST is high, the reset signal C1 is low, and C2 is high, the third PMOS transistor PM3 and the fourth NMOS transistor NM4 are turned on, the fifth PMOS transistor PM5, the fifth NMOS transistor NM5, and the seventh NMOS transistor NM7 are turned off, and the TSPC flip-flop operates in a normal mode.
3. The TSPC flip-flop according to claim 1, wherein when the input set signal SETN is low, RSTN is high, RST is low, the reset signal C1 is high, and C2 is low, the fifth PMOS transistor PM5 and the seventh NMOS transistor NM7 are turned on, the third PMOS transistor PM3, the fifth NMOS transistor NM5, and the fourth NMOS transistor NM4 are turned off, the node Y is high, the node Z is low, and the output Q is high, when the TSPC flip-flop is operated in the set mode.
4. The TSPC flip-flop of claim 1, wherein when the input set signal SETN is high, RSTN is low, RST is high, the reset signal C1 is high, and C2 is low, the fifth and seventh NMOS transistors NM5 and NM7 are turned on, the third, fifth and fourth PMOS transistors PM3 and PM5 and NM4 are turned off, the node Y is low, the node Z is high, the output Q is low, and the TSPC flip-flop operates in the reset mode.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112532231A (en) * | 2020-12-08 | 2021-03-19 | 珠海市杰理科技股份有限公司 | TSPC trigger, sequential logic circuit and radio frequency circuit |
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| CN112532231A (en) * | 2020-12-08 | 2021-03-19 | 珠海市杰理科技股份有限公司 | TSPC trigger, sequential logic circuit and radio frequency circuit |
| CN112532231B (en) * | 2020-12-08 | 2023-11-03 | 珠海市杰理科技股份有限公司 | TSPC flip-flop, sequential logic circuit and radio frequency circuit |
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| CN111769826B (en) | 2023-11-07 |
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