CN111224644A - D trigger of low-power consumption - Google Patents

D trigger of low-power consumption Download PDF

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CN111224644A
CN111224644A CN201911132074.XA CN201911132074A CN111224644A CN 111224644 A CN111224644 A CN 111224644A CN 201911132074 A CN201911132074 A CN 201911132074A CN 111224644 A CN111224644 A CN 111224644A
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gate
transistor
complementary
pair
source
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CN111224644B (en
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吴为敬
翁树锋
林奕圳
徐苗
王磊
彭俊彪
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South China University of Technology SCUT
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a D trigger with low power consumption, which comprises: two not gates for generating a true input signal and a complementary input signal of the D flip-flop; six NOR gates for realizing complementary work of a pull-up network and a pull-down network of the logic gate; the signal of the D trigger comprises a clock signal end, a data signal end, a power supply end, a grounding end and an output end. The invention realizes the complementary work of the pull-up network and the pull-down network of the logic gate, greatly reduces the power consumption of the unipolar circuit and realizes the full-swing output voltage.

Description

D trigger of low-power consumption
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a low power consumption D flip-flop.
Background
The D flip-flop is a memory cell of a general sequential circuit, and can memorize the current state of a digital circuit and store the current operation result. Edge-triggered D flip-flops are less affected by glitches at the input and operate in a stable state, and are therefore often used as basic units to form more complex modules such as ring oscillators, data registers, and counters.
Since metal oxide thin film transistors often exhibit n-type conductivity and it is difficult to produce p-type metal oxide thin film transistors with matching properties, in digital logic circuits formed of thin film transistors, unipolar circuits formed of only n-type thin film transistors are often used. The monopole circuit cannot form a complementary push-pull structure, and the power consumption problem caused by a static direct current path exists.
When an input signal is low level, if there is no high level signal from external input, how to turn on the pull-up network is a problem to be solved.
Disclosure of Invention
In order to solve the problem that a unipolar D flip-flop in the prior art is large in static power consumption, the invention provides a D flip-flop with low power consumption.
The invention adopts the following technical scheme:
a low power D flip-flop comprising:
two not gates for generating a true input signal and a complementary input signal of the D flip-flop;
six NOR gates for realizing complementary work of a pull-up network and a pull-down network of the logic gate;
the D flip-flop comprises a clock signal terminal CLK, a data signal terminal D and a power supply terminal VDDA ground terminal GND and an output terminal OUT.
Further, the two not gates include a no-zero not gate X0 and a no-seven not gate X7;
the six nor gates include a first nor gate X1, a second nor gate X2, a third nor gate X3, a fourth nor gate X4, a fifth nor gate X5, and a sixth nor gate X6;
the specific connection mode is as follows:
the input of the zero-not gate X0 is connected to the data signal D, the output thereof is connected to the data signal D and to one pair of complementary inputs of the first nor gate X1, the other pair of complementary inputs of the first nor gate X1 is connected to the complementary output of the second nor gate X2, the complementary output thereof is connected to one pair of complementary inputs of the fourth nor gate X4;
the input terminal of the seventh nor gate X7 is connected to the clock signal CLK, the output terminal thereof is connected to the clock signal CLK and both are connected to a pair of complementary input terminals of the second nor gate X2 and a pair of complementary input terminals of the third nor gate X3, the other pair of complementary input terminals of the second nor gate X2 is connected to the complementary output terminal of the third nor gate X3,
the other pair of complementary inputs of the third nor gate X3 is connected to the complementary output of the fourth nor gate X4;
the other pair of complementary inputs of the fourth nor gate X4 is connected to the complementary output of the third nor gate X3;
a pair of complementary inputs of the fifth nor gate X5 is connected to the complementary outputs of the second nor gate X2, another pair of complementary inputs is connected to the complementary outputs of the sixth nor gate X6, and a complementary output of the fifth nor gate X5 is connected to a pair of complementary inputs of the sixth nor gate X6;
one pair of complementary inputs of the sixth nor gate X6 is connected to the complementary output of the third nor gate X3, the other pair of complementary inputs is connected to the complementary output of the fifth nor gate X5, and its complementary output is connected to a pair of complementary inputs of the fifth nor gate X5.
Further, the NOT gate is of a pseudo CMOS structure.
Further, the nor gate is in a differential circuit structure.
Further, the not gate of the dummy CMOS structure includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a capacitor C;
the first transistor M1 has its drain and gate both connected to the power supply terminal VDDA source thereof is connected to the drain of the second transistor M2 and the gate of the third transistor M3; the gate of the second transistor M2 is connected to the input signal terminal IN, and the source thereof is connected to the ground terminal GND;
drain of the third transistor M3 and a power source terminal VDDA source connected to the drain of the fourth transistor M4;
the gate of the fourth transistor M4 is connected to the input signal terminal IN, the source thereof is connected to the ground terminal GND, one end of the capacitor C is connected to the source of the first transistor M1, and the other end thereof is connected to the source of the third transistor M3 as the output terminal OUT.
Further, the nor gate having the differential circuit structure includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10;
the drain of the fifth transistor M5 and the power supply terminal VDDA gate connected to the input signal A, a source connected to the source of the sixth transistor M6, the drain of the seventh transistor M7, and the gate of the tenth transistor M10,
the drain of the sixth transistor M6 and the power supply terminal VDDThe grid of the input signal B is connected with the grid of the input signal B;
the gate of the seventh transistor M7 is connected to the source of the ninth transistor M9, and the source thereof is connected to the ground GND;
drain and power supply terminal V of eighth transistor M8DDA gate thereof connected to the input signal a', and a source thereof connected to a drain of the ninth transistor M9;
the gate of the ninth transistor M9 is connected to the input signal B';
the drain of the tenth transistor M10 is connected to the source of the ninth transistor M9, and the source thereof is connected to the ground GND.
Further, the transistor mentioned in the present invention is n-type.
The invention has the beneficial effects that:
(1) according to the D trigger, the number of the diode-connected transistors is greatly reduced, so that the static power consumption of a single-pole D trigger is greatly reduced;
(2) the NOR gate of the invention adopts a differential circuit structure, which not only realizes the complementary work of the pull-up network and the pull-down network of the logic gate, improves the noise tolerance and the conversion speed of the logic gate, but also effectively improves the swing of the output voltage by utilizing positive feedback.
Drawings
FIG. 1 is a circuit schematic of the NOT gate of the pseudo CMOS structure of the present invention;
FIG. 2 is a circuit schematic of the NOR gate of the present invention;
FIG. 3 is a diagram of a prior art D flip-flop configuration;
fig. 4 is a schematic diagram of a low power consumption D flip-flop according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited to these examples.
Examples
As shown in fig. 1, fig. 2 and fig. 4, the invention modifies the gate circuit into a logic gate with complementary input and complementary output (differential signal) to cut off the potential direct current path.
The circuit consists of two NOT gates with a pseudo CMOS structure and six NOR gates with a differential circuit structure, wherein signals of the D trigger circuit comprise a clock signal end CLK, a data signal end D and a power supply end VDDA ground terminal GND and an output terminal OUT.
In the nor gate of fig. 2, the inputs A, B, A 'and B' are input signals of a logic gate, and when the logic gate is used as a subsequent circuit, the inputs of the logic gate can be obtained from the output signal of the previous gate or from external input signals of the circuit (such as the clock input signal CLK and the data input signal D of the D flip-flop). In the D flip-flop of FIG. 4, Q and QBIs the output signal of the D flip-flop and represents the current circuit state of the D flip-flop. The output node will be brought out to the outside of the D flip-flop circuit.
The two NOT gates include NOT gate number zero X0 and NOT gate number seven X7;
the six nor gates include a first nor gate X1, a second nor gate X2, a third nor gate X3, a fourth nor gate X4, a fifth nor gate X5, and a sixth nor gate X6;
the specific connection mode is as follows:
the input terminal of the zero-sign not gate X0 is connected to the data signal terminal D, the output terminal thereof and the data signal terminal D are connected to a pair of complementary input terminals of the first nor gate X1, the other pair of complementary input terminals of the first nor gate X1 is connected to a complementary output terminal of the second nor gate X2, and the complementary output terminal of the first nor gate X1 is connected to a pair of complementary input terminals of the fourth nor gate X4;
the input terminal of the seventh nor gate X7 is connected to the clock signal terminal CLK, the output terminal thereof and the clock signal terminal CLK are both connected to a pair of complementary input terminals of the second nor gate X2 and a pair of complementary input terminals of the third nor gate X3, the other pair of complementary input terminals of the second nor gate is connected to a complementary output terminal of the third nor gate X3,
the other pair of complementary input ends of the third NOR gate is connected with the complementary output end of the fourth NOR gate;
the other pair of complementary input ends of the fourth NOR gate is connected with the complementary output end of the third NOR gate;
a pair of complementary inputs of the fifth nor gate X5 is connected to the complementary output of the second nor gate X2, another pair of complementary inputs is connected to the complementary output of the sixth nor gate X6, and a complementary output of the fifth nor gate is connected to a pair of complementary inputs of the sixth nor gate X6;
the other pair of complementary inputs of the sixth nor gate X6 is connected to the complementary output of the third nor gate X3, the other pair of complementary inputs of the sixth nor gate X6 is connected to the complementary output of the fifth nor gate X5, and the complementary output of the sixth nor gate X6 is connected to the pair of complementary inputs of the fifth nor gate X5.
The invention adopts two NOT gates with a pseudo-CMOS structure for generating a true input signal and a complementary input signal of a D trigger. The six NOR gates adopt a differential circuit structure, and complementary work of a pull-up network and a pull-down network of the logic gate is realized. For the NOR gate, a direct current path inside the logic gate is cut off through a differential circuit structure, and the static power consumption of the circuit is greatly reduced.
All transistors of the gate driving unit in this embodiment are n-type transistors.
The not gate of the dummy CMOS structure includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a capacitor C;
the first transistor M1 has its drain and gate both connected to the power supply terminal VDDA source thereof is connected to the drain of the second transistor M2 and the gate of the third transistor M3; the gate of the second transistor M2 is connected to the input signal terminal IN, and the source thereof is connected to the ground terminal GND;
of the third transistor M3Drain electrode and power supply terminal VDDA source connected to the drain of the fourth transistor M4;
the gate of the fourth transistor M4 is connected to the input signal terminal IN, the source thereof is connected to the ground terminal GND, one end of the capacitor C is connected to the source of the first transistor M1 at the point N, and the other end thereof is connected to the source of the third transistor M3 as the output terminal OUT.
The nor gate having a differential circuit structure includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10;
the drain of the fifth transistor M5 and the power supply terminal VDDA gate connected to the input signal a, a source connected to the source of the sixth transistor M6, the drain of the seventh transistor M7, and the gate of the tenth transistor M10 to the input signal Y';
the drain of the sixth transistor M6 and the power supply terminal VDDThe grid of the input signal B is connected with the grid of the input signal B;
the gate of the seventh transistor M7 and the source of the ninth transistor M9 are connected to the input signal Y, and the source is connected to the ground GND;
drain and power supply terminal V of eighth transistor M8DDA gate thereof connected to the input signal a', and a source thereof connected to a drain of the ninth transistor M9;
the gate of the ninth transistor M9 is connected to the input signal B';
the drain of the tenth transistor M10 is connected to the source of the ninth transistor M9, and the source thereof is connected to the ground GND.
As shown in fig. 3, the conventional D flip-flop based on only a single-polarity transistor mostly adopts a logic gate with a pseudo-CMOS structure, and has a drawback in that a diode-connected transistor is used as a pull-up network, which is at the expense of unconditional turn-on of the pull-up network, which may cause excessive quiescent current of a circuit, resulting in problems of sharply increased quiescent power consumption, severely reduced noise margin, and the like, and is not favorable for improving the circuit integration level and the operating performance.
The logic gate adopting the differential circuit structure can effectively reduce the use of diode-connected transistors, and utilizes the internal part of the gateThe cross feedback of the signals realizes logic control, realizes the complementary work of the pull-up network and the pull-down network, and greatly reduces the static power consumption of the circuit. The principle is as follows: taking the nor gate of fig. 2 as an example, the input signals a and B are both external input signals to the logic gate, and the input signals a 'and B' are inverted signals of the inputs a and B, respectively; when one or both of the inputs A and B are high, at least one of the inputs A ' and B ' is low, so that the pull-up network formed by the transistors M5 and M6 is turned on, the pull-up network formed by the transistors M8 and M9 is turned off, and the output node Y ' and the power supply V are turned onDDConnected to output node Y and power supply VDDAnd when the voltage is disconnected, the output Y 'is pulled high to turn on the transistor M10, so that the output node Y is connected with the ground of the circuit, the output Y is pulled low to low level, the transistor M7 is turned off by the output low-level Y in the level conversion process, the pull-down network of the output Y' is turned off by positive feedback, and the pull-down network of the output Y is turned on. Therefore, complementary work of the pull-up network and the pull-down network of the circuits on the two sides is realized, and a potential direct current path is cut off.
The invention completely adopts an n-type transistor as a switch element, forms a NOT gate of a pseudo CMOS structure and a NOR gate of a differential circuit structure as basic logic units, and realizes the characteristic of edge triggering. The input stage circuit adopts a NOT gate with a pseudo CMOS structure to generate complementary input signals, the intermediate stage circuit and the output stage circuit adopt a NOR gate with a differential circuit structure to realize complementary work of a pull-up network and a pull-down network of a logic gate, the power consumption of a single-pole circuit is greatly reduced, and the full-swing output voltage is realized.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.

Claims (7)

1. A low power D flip-flop, comprising:
two not gates for generating a true input signal and a complementary input signal of the D flip-flop;
six NOR gates for realizing complementary work of a pull-up network and a pull-down network of the logic gate;
the signal of the D flip-flop comprises a clock signal terminal (CLK), a data signal terminal (D) and a power supply terminal (V)DD) A ground terminal (GND) and an output terminal (OUT).
2. The D flip-flop of claim 1,
the two NOT gates comprise a NOT zero gate (X0) and a NOT seven gate (X7);
the six NOR gates include a first NOR gate (X1), a second NOR gate (X2), a third NOR gate (X3), a fourth NOR gate (X4), a fifth NOR gate (X5), and a sixth NOR gate (X6);
the specific connection mode is as follows:
the input of the zero-sign not gate (X0) is connected to the data signal (D), the output thereof and the data signal (D) are connected to a complementary pair of inputs of a first nor gate X1, the other complementary pair of inputs of the first nor gate X1 is connected to the complementary output of a second nor gate X2, the complementary output thereof is connected to a complementary pair of inputs of a fourth nor gate X4;
the input terminal of the seventh NOR gate (X7) is connected with the clock signal (CLK), the output terminal thereof is connected with the clock signal (CLK) and is connected with a pair of complementary input terminals of the second NOR gate (X2) and a pair of complementary input terminals of the third NOR gate (X3), the other pair of complementary input terminals of the second NOR gate (X2) is connected with the complementary output terminal of the third NOR gate (X3),
the other pair of complementary inputs of the third nor gate (X3) is connected to the complementary output of the fourth nor gate (X4);
the other pair of complementary inputs of the fourth nor gate (X4) is connected to the complementary output of the third nor gate (X3);
a pair of complementary inputs of a fifth nor gate (X5) is connected to a complementary output of the second nor gate (X2), another pair of complementary inputs is connected to a complementary output of the sixth nor gate (X6), and a complementary output of the fifth nor gate (X5) is connected to a pair of complementary inputs of the sixth nor gate (X6);
one pair of complementary inputs of the sixth nor gate (X6) is connected to the complementary output of the third nor gate (X3), the other pair of complementary inputs is connected to the complementary output of the fifth nor gate (X5), and its complementary output is connected to one pair of complementary inputs of the fifth nor gate (X5).
3. The D flip-flop according to claim 1, wherein said not-gate is a pseudo-CMOS structure.
4. The D flip-flop according to claim 1, wherein said nor gate is a differential circuit structure.
5. The D flip-flop according to claim 3, wherein the NOT gate comprises a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4) and a capacitor (C);
the drain and the gate of the first transistor (M1) are both connected to a power supply terminal (V)DD) A source thereof is connected to the drain of the second transistor (M2) and the gate of the third transistor (M3); the gate of the second transistor (M2) is connected to the input signal terminal (IN), and the source thereof is connected to the ground terminal (GND);
drain and power supply terminal (V) of third transistor (M3)DD) A source connected to the drain of the fourth transistor (M4);
the gate of the fourth transistor (M4) is connected to the input signal terminal (IN), the source thereof is connected to the ground terminal (GND), one end of the capacitor (C) is connected to the source of the first transistor (M1), and the other end thereof is connected to the source of the third transistor (M3) as the output terminal (OUT).
6. The D flip-flop according to claim 4, wherein the NOR gate comprises a fifth transistor (M5), a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9) and a tenth transistor (M10);
drain and power supply terminal (V) of the fifth transistor (M5)DD) A gate connected to the input signal (A), a source connected to the source of the sixth transistor (M6), and a seventh transistorThe drain of the transistor (M7) and the gate of the tenth transistor (M10) are connected,
drain and power supply terminal (V) of the sixth transistor (M6)DD) A gate connected to an input signal (B);
a gate of the seventh transistor (M7) is connected to a source of the ninth transistor (M9), and a source thereof is connected to the ground terminal (GND);
a drain electrode and a power source terminal (V) of the eighth transistor (M8)DD) A gate connected to the input signal (a'), and a source connected to a drain of the ninth transistor (M9);
the gate of the ninth transistor (M9) is connected to the input signal (B');
the drain of the tenth transistor (M10) is connected to the source of the ninth transistor (M9), and the source thereof is connected to the ground GND.
7. The D flip-flop of claim 1, wherein the transistor is n-type.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111917397A (en) * 2020-06-18 2020-11-10 华南理工大学 Trigger circuit and chip based on unipolar transistor

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CN104796132A (en) * 2014-01-22 2015-07-22 陈祺琦 Flip-flop circuit
JP2017175633A (en) * 2017-04-26 2017-09-28 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Flip-flop for reducing dynamic power
CN108233896A (en) * 2018-01-31 2018-06-29 电子科技大学 A kind of low-power consumption sense amplifier type d type flip flop

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CN104796132A (en) * 2014-01-22 2015-07-22 陈祺琦 Flip-flop circuit
JP2017175633A (en) * 2017-04-26 2017-09-28 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Flip-flop for reducing dynamic power
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Publication number Priority date Publication date Assignee Title
CN111917397A (en) * 2020-06-18 2020-11-10 华南理工大学 Trigger circuit and chip based on unipolar transistor
CN111917397B (en) * 2020-06-18 2021-08-10 华南理工大学 Trigger circuit and chip based on unipolar transistor

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