JP2002064366A - Conditional capture flip-flop for power saving - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flip-flop capable of minimizing power consumption by preventing unwanted discharge without affecting an operating speed. SOLUTION: This flip-flop for a semiconductor integrated circuit is provided with a delay/inverter means 410 for inputting a clock, delaying/inverting it, inputting first and second output signals and inverting these signals, differential circuit means 400 and 420 for detecting and amplifying the signal level difference of positive and negative data signals being controlled by the clock and the output signal of the delaying/inverting means, and an S-R latch means 430 for inputting the output signals of the differential circuit means, latching these signals and outputting the first and second output signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a flip-flop capable of minimizing power consumption without affecting operation speed.

[0002]

2. Description of the Related Art In general, a flip-flop is a semiconductor element used in an internal circuit of a semiconductor integrated device which needs to store and output a state input as one type of register or to maintain a state before the state. is there. There are various types of flip-flops, and they should be selected according to the required application.

[0003] Conventional flip-flops include a hybrid latch-flip-flip (HLFF).
lop), semi-dynamic flip-flop (SDFF: semi-
dynamic flip-flop) and sense amplifier-based flip-flop (SAFF).

The above-mentioned hybrid latch flip-flop was developed in February 1996 by the International Solid State Circuit (ISSCC).
cuit Conference), "Flow-Through La
tchand Edge-Triggered Flip-flop Hybrid Element ".

FIG. 1 is a circuit diagram showing a conventional hybrid latch flip-flop (HLFF).

Referring to FIG. 1, in a hybrid latch flip-flop (HLFF), a clock CLK is input at a gate terminal and a source / drain path is connected to a power supply voltage terminal Vcc and a first node.
First pull-up transistor 100 formed between X and X
And a delay / inversion unit 110 that receives and receives the clock CLK and delays and inverts it for a predetermined time, and a clock CLK, data D, and an output signal of the delay / inversion unit 110, each of which is input at a gate end and
First to third NMOS transistors 120, 121, and 122 connected in series between a node X and a ground terminal GND, a data D input source and a drain path are connected to the first node X and a power supply voltage terminal Vcc.
The first precharge transistor 130 formed between
A second precharge transistor 140 in which an output signal of the delay / inversion unit 110 is input at a gate terminal and a source / drain path is formed between the first node X and a power supply voltage terminal Vcc;
The signal of the node X is input at the gate terminal, and the source / drain path is formed between the power supply voltage terminal Vcc and the second node Y.
A pull-up transistor 150, a clock CLK, a signal of the first node X, and an output signal of the delay / inverting unit 110 are respectively input at a gate terminal and connected in series between a second node Y and a ground terminal GND. Or sixth NMOS transistors 160, 161, 162
And a latch section for latching and outputting the output signal Q of the second node
Consists of 170.

A hybrid latch flip-flop (HLF)
In operation F), when the clock CLK is logic low, the first pull-up transistor 100, the third NMOS transistor 122, and the sixth NMOS transistor 162 are turned on, and the first NMOS transistor 120 and the fourth NMOS transistor 160 are turned on.
Is turned off. As a result, the first node X is precharged to the power supply voltage level, and the output signal Q has the previous data value held in the latch unit 170.

At the rising edge of the clock CLK, the third NMOS transistor 122 and the sixth NMOS transistor 162 are connected to the delay / inversion unit.
While waiting for the clock signal delayed and inverted by 110, the first NMOS transistor 120 and the fourth NMOS transistor 160
Are turned on. In this case, the data D is held in the latch unit 170 during the above period. If the output signal of the delay / inversion unit 110 transitions from a logic high to a logic low,
One node X is precharged to the power supply voltage level by the second precharge transistor 140 and is precharged to the power supply voltage level by the first precharge transistor 130 when the data D is logic low.

At the falling edge of the clock CLK, the first node X is connected to the clock CL by the first pull-up transistor 100.
It is fully precharged to the supply voltage level as long as K is at a logic low.

Secondly, a semi-dynamic flip-flop (SDFF) is disclosed in "Symposium on VLSI" published in 1998.
Circuit Digest of Technical Papers "to" Semi-Dynamic
andDynamic Flip-Flops with Embeded Logic ".

FIG. 2 is a circuit diagram showing a conventional semi-dynamic flip-flop (SDFF).

Referring to FIG. 2, a semi-dynamic flip-flop (SDFF) receives a clock CLK at a gate terminal and a source / drain path between a power supply voltage terminal Vcc and a first node X.
A precharge transistor 200 formed between
A delay / inversion unit 210 for receiving and delaying and inverting the clock CLK and the signal of the first node X, and an output signal of the delay / inversion unit 210, data D, and a clock CLK, each of which is input at a gate terminal to receive the first signal. First to third NMOS transistors 220, 221, and 222 connected in series between the node X and the ground terminal GND; a first latch unit 230 for latching the signal of the first node X;
A signal of one node is input at a gate terminal, and a source-drain path is a pull-up transistor 240 formed between a power supply voltage terminal Vcc and an output node Q, and a clock CLK and a signal of the first node X are respectively connected at a gate terminal. Fourth and fifth NMOS transistors 250 and 251 are connected in series between the output node Q and the ground terminal GND, and a second latch unit 260 latches and inverts the signal of the output node Q.

A semi-dynamic flip-flop (SDF)
In operation F), the flip-flop enters the precharge mode at the falling edge of the clock CLK. In this case, the precharge transistor 200, which receives the clock CLK at the gate terminal, is turned on to precharge the first node X to the power supply voltage level. When the first node X is precharged to a logic high, the signal at the output node Q is separated from the input terminal and retains the value previously latched by the second latch unit 260. If the clock CLK is at a logic low during the precharge, the output signal of the delay / inversion unit 210 becomes a logic high, turning on the first NMOS transistor 220.

At the rising edge of the clock, the flip-flop enters an evaluation mode. When the data D is logic low, the first node X remains at logic high by the first latch unit 230. Then, the fourth and fifth NMOS transistors 250 and 251 are turned on to discharge the signal of the output node Q, and set the output node Q to logic low and the second latch unit 260 to change the output signal QB to logic high. . After the clock CLK rises, the output signal of the delay / inversion unit 210 changes from logic high to logic low, and the first NMOS transistor 220 is turned off.
When the data D is logic high, the first node X is connected to the pull-down of the first to third NMOS transistors 220, 221 and 222.
l down) through a path. Even if the data D falls to a logic low, the first node X continues to latch the logic low value by the first latch unit 230. Then, the pull-up transistor 240 is turned on, and the signal at the output node Q is set to a logic high.

Third, a conventional sense amplifier based flip-flop (SAFF) was developed in February 1999 by ISSCC (International
l Solid State Circuit Conference) has been published in a paper titled "Sense Amplifier-Based Flip-Flop".

FIG. 3 is a circuit diagram showing a conventional sense amplifier-based flip-flop (SAFF).

Referring to FIG. 3, a sense amplifier-based flip-flop (SAFF) receives a data D and DB, and is controlled by a clock CLK and receives an output signal of the sense amplifier 300. SR to be latched
A latch 310 is provided.

The sense amplifier section 300 has the structure of a normal sense amplifier, and includes a large number of PMOS transistors 301.
Through 304 and NMOS transistors 305 through 310. The sense amplifier unit 300 senses and amplifies a signal level difference between the data D and DB. When the clock CLK is logic low, the output node of the sense amplifier unit 300 is precharged to the power supply voltage level, and when the clock CLK is logic high, the sense amplifier unit 300 is driven to accept a differential input.

Two output signals from the sense amplifier unit 300 are input to the SR latch unit 310 and latched. The first input SB of the SR latch unit 310 is a set input, and the second input RB is a reset input. Sense amplifier section 3
00, the first input S
If both B and the second input RB are logic low, it is not allowed. If the first input SB is logic low, the SR latch
The first output signal Q of 310 is set to a logic high and the second
If the input RB is logic low, the second
Set output signal QB to logic high.

The above-described hybrid latch flip-flop (HLFF) and semi-dynamic flip-flop (SDFF)
And sense amplifier based flip-flops (SAFF)
In terms of operating speed, transmission gate master slave flip-flops (TGFF: transmission ga
Better than flip-flops like te master-slave flip-flop). On the other hand, the internal nodes are precharged and discharged every clock cycle, which causes unnecessary power consumption.

[0021]

SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned problems of the prior art, and prevents unnecessary discharge without affecting the operation speed. It is an object of the present invention to provide a flip-flop capable of minimizing power consumption.

[0022]

In order to achieve the above object, a flip-flop according to the present invention is a flip-flop of a semiconductor integrated circuit which receives a clock and receives a delay / delay.
A delay / inverting means for inverting and inputting and inverting the first and second output signals, and a signal level difference between positive data and a negative data signal controlled by the clock and the output signal of the delay / inverting means. Differential circuit means for inputting and amplifying the output signal, and SR latch means for receiving and latching the output signal of the differential circuit means and outputting the first and second output signals.

Further, the flip-flop of the present invention is a flip-flop of a semiconductor integrated circuit, wherein a clock is inputted at a gate terminal, and a source / drain path is formed between a power supply voltage terminal and a precharge node. Delay / inverting means for receiving and delaying the signal of the output node by inputting and delaying the signal of the output node, and the clock, data, and the output signal of the delay / inverting means being input at the respective gate terminals to ground the precharge node and ground. A first to a third NMOS transistor connected in series between the first and third terminals, a first precharge transistor having the data input at the gate terminal and a source / drain path formed between the power supply voltage terminal and the precharge node. The output signal of the delay / inversion means is input at the gate terminal, and the source / drain path is A second precharge transistor formed between the power supply voltage terminal and the output node; a second precharge transistor formed between the power supply voltage terminal and the output node; An inverter to which data is input, the clock, the output signal of the inverter, and the output signal of the delay / inversion means are input at respective gates and connected in series between the output node and a ground terminal.
A fourth to a sixth NMOS transistors; and a latch unit that receives and latches and inverts the signal of the output node.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 4 shows a conditional-capture flip-flop (CCFF) according to the present invention.
Differential version of (differential versio
It is a circuit diagram which shows n).

Referring to FIG. 4, the conditional capture flip-flop (CCFF) according to the present invention receives and delays / inverts the clock CLK to receive the first and second output signals Q and QB of the SR latch unit 430. Delay / inverting section 410
And differential circuits 400 and 420, which are controlled by the clock CLK and the output signal of the delay / inverting unit 410, receive data A and negative data AB, detect the difference between them, and operate. And an SR latch unit 430 that receives and latches the output signal of the first stage.

More specifically, the delay / inversion unit 410 outputs the clock CL
First and second inverters 411 and 41 for receiving and delaying K
2, a first NOR gate 413 to which the output signal of the second inverter 412 and the first output signal Q of the SR latch unit 430 are input, and an output signal of the second inverter 412 and the second output signal QB of the SR latch unit 430.
And a second NOR gate 414 for receiving the input.

Specifically, the differential circuit section 400 receives the clock CLK
Input at the gate end and the source / drain path
The first precharge transistor 401 formed between Vcc and the first output node SB, and the output signal and data A of the delay / inverting unit 410 are input at the respective gate terminals, and the first output node SB and the common node NC A first latch unit 404 that inverts and latches the first output node SB and generates a first final output signal S,
The clock CLK is input at the gate, and the source / drain path includes a third NMOS transistor 409 formed between the common node NC and the ground terminal GND.

The differential circuit 420 includes a second precharge transistor 405 having a clock CLK input at a gate terminal and a source / drain path formed between a power supply voltage terminal Vcc and a second output node RB, and a delay / inversion circuit. Output signal of section 410 and negative data AB
The fourth and fifth NMOS transistors 406 and 407 connected in series between the second output node RB and the common node NC, each of which is input at the gate terminal, and the second output node RB are inverted and latched to obtain the second
The second latch unit 408 generates the final output signal R.

The SR latch unit 430 receives the signal of the first output node SB at the gate terminal, and has a source / drain path formed between the power supply voltage terminal Vcc and the first node Q as its own output node. Transistor 421 and second final output signal R
Is input at the gate end and the source / drain path is
1st NMOS transistor 42 formed between
2, a second PMOS transistor 423 in which the first node Q is input at the gate end and the source / drain path is formed between the first output node SB and the second node QB which is its own output node;
The signal of the first node Q is input at the gate terminal, the source / drain path is formed between the second final output signal R and the second node QB, the second NMOS transistor 424, and the signal of the second node QB is input at the gate terminal. A third PMOS transistor 425 having an input and a source / drain path formed between the second output node RB and the first node Q, and a signal at the second node QB input at the gate end and having a source / drain path at the first final output node A third NMOS transistor 426 formed between S and the first node Q, and a signal at the second output node RB are input at the gate terminal and a source / drain path is formed between the power supply voltage terminal Vcc and the second node QB. The first
4PMOS transistor 427, the signal of the first final output node S is input at the gate terminal, and the source / drain path is the second node QB
4th NMOS transistor 42 formed between
8 is provided.

The SR latch unit 420 performs a high-speed operation as a normal cross connection circuit.

In operation, when the clock CLK is at logic low, the set negative signal SB, which is the signal of the first output node SB, and the reset negative signal RB, which is the signal of the second output node, are output from the differential circuit section. A transition from a logic low to a logic high by the first and second precharge transistors 401 and 405 of the SR and the SR
The latch unit 430 is disabled. First and second signals Q,
When QB is logic low and logic high, respectively,
30 second PMOS transistors 423 and third NMOS transistors 426
Is turned on to save the output state. Also, the first and second signals Q and QB turn on the first NMOS transistor 402 of the differential circuit unit 400 via the first and second NOR gates 413 and 414 of the delay / inverting unit 410 to turn on the first and second signals of the differential circuit unit 420. 4 Turn off the NMOS transistor 406. The operation of the flip-flop after the clock CLK rises will be described. The operation is determined according to the states of the input data A and the negative data AB.

When the data A is logic high, the set negative signal SB is pulled down and the SR latch 43
0 first PMOS transistor 421 and fourth NMOS transistor 428
Is activated to change the output state. During this time, the second PMOS transistor 423 of the SR latch unit 420 and the third NMO
S-transistor 426 is turned off, and signal fighting between the previous state and the current state signal value (signal
fighting). When the input of data A is logic low, the third NMOS transistor 406 of the differential circuit unit 400
Is turned off, the reset negative signal RB is not pulled down. This is data A whose output is already input
This is because it has the same value as the value. When the clock CLK transitions from logic high to logic low, the set negative signal SB is precharged if it has been discharged. First and second inverters 411 and 4 of delay / inversion unit 410
The 12 output signals are sent to the differential circuit according to the pull-down output value.
400 first NMOS transistor 402 and fourth NMOS transistor
Turn on 406.

As can be seen, the SR latch 430
1 When the output signal Q and the input data A signal are all logic high, by turning off the first NMOS transistor 402, the flip-flop does not discharge,
The original state will be maintained. If the first output signal Q and the input data A signal are all logic low, the second NM
By turning off the OS transistor 403, unnecessary discharge is prevented.

FIG. 5 is a circuit diagram showing a single-ended version of a conditional capture flip-flop (CCFF) according to another embodiment of the present invention.

Referring to FIG. 5, a single-ended version of the conditional capture flip-flop (CCFF) has a clock CLK input at a gate terminal and a source / drain path connected to a power supply voltage terminal Vcc and a precharge node X.
And a clock transistor C
A delay / inverting unit 540 that receives and delays LK to receive and inverts an output signal Q, and a precharge node in which a clock CLK, data D, and an output signal NB of the delay / inverting unit 540 are each input at a gate end and are input. First to third NMOS transistors 510, 511, and 512 connected in series between X and the ground terminal GND, and data D is input at the gate terminal and the source / drain path is between the power supply voltage terminal Vcc and the precharge node X. The first formed
(1) a precharge transistor 530, and a second precharge transistor 550 in which the output signal CKDB of the delay / inversion unit 540 is input at the gate terminal and the source / drain path is formed between the power supply voltage terminal Vcc and the precharge node X. A pull-up transistor 560 having a gate terminal receiving the signal of the precharge node X and having a source / drain path formed between the power supply voltage terminal Vcc and the output node Q, an inverter 520 receiving data D, and a clock CLK. The fourth to sixth NMOS transistors 570, 571, and 572, each having an output signal of the inverter 520 and an output signal of the delay / inversion unit 540 input at a gate terminal and connected in series between an output node Q and a ground terminal GND, , A latch unit 580 that receives and latches and inverts the signal of the output node Q.

Referring to FIG. 5, a single-end version of the conditional capture flip-flop (CCFF)
ed version), the delay / inversion unit 540
It is used for the same purpose as the delay / inversion unit 410 of the flip-flop in FIG. The precharge node X is discharged at the rising edge of the clock when the signal at the output node Q is logic low and the data D is logic high.

When the clock CLK is logic low, the second and third NMOS transistors 511 and 512 are connected to the precharge node X
Maintain a logic high to prevent discharging of When the data D is logic low, the fifth NMOS transistor 571 is turned on and the signal at the output node Q is
Keep current state or pull down to ground level. When the signal input to the third NMOS transistor 510 from the delay / inversion unit 540 becomes logic low, the precharge node X is separated from the data D. Delay / inverter 540 to
When the signal input to the 6NMOS transistor 572 is a logic low, the output node Q is also separated from the data D and operates. As long as the clock CLK keeps a logic low level from the falling edge of the clock CLK, the precharge node X is precharged to the power supply voltage level.

FIG. 6 is a timing chart showing the waveform of the result of a simulation experiment performed on each signal of the flip-flop of FIG. 4, and FIG. 7 is a timing chart showing the waveform of the flip-flop of FIG. FIG.

The simulated waveforms of the flip-flops shown in FIGS. 6 and 7 are typical devices using a power supply voltage of 2.5 V, a temperature of 25 degrees Celsius, and an output load of 400 fF. , 0.35 μm CMOS technology.

FIG. 8 is a diagram comparing the power consumption of the conditional capture flip-flop (CCFF) of the present invention and the conventional sense amplifier-based flip-flop (SAFF) according to the data patterns.

Referring to FIG. 8, when there is no change in adjacent data, for example, as in the data pattern (11001100), a conventional sense amplifier based flip-flop (SAFF) is used.
When the conditional capture flip-flop (CCFF) of the present invention has a power saving effect of about 20% and there is no data change for each clock as in the data pattern of (11111111),
It can be seen that there is a power saving effect of about 60%.

FIG. 9 shows a conditional flip-flop (CCFF) of the present invention and a conventional hybrid latch flip-flop.
(HLFF), semi-dynamic flip-flop (SDFF), extremely low power consumption transmission gate master-slave flip-flop (TGFF: Transmission gat
FIG. 9 is a diagram comparing power consumption according to a data pattern with e master-slave flip-flop).

Referring to FIG. 9, similarly to FIG. 8, the conditional capture flip-flop (CCFF) of the present invention is used not only when there is a change in data in the data pattern but also when there is no change in data every clock. It is understood that the power saving effect is superior to other flip-flops.

FIG. 10 is a graph comparing the power consumption when a counter is implemented using the conditional capture flip-flop (CCFF) of the present invention and a conventional sense amplifier-based flip-flop (SAFF). In the figure, "FLIP-FLOP" is
Indicates the power consumed inside the counter, "clock (C
"LOCK)" indicates the power consumed when the clock is toggled, and "GATE" indicates the logic gates, such as AND gates and NOR gates, used to logically combine the output signals of the counter. The respective powers are shown.

Referring to FIG. 10, the counter using the conditional capture flip-flop (CCFF) of the present invention and the counter using the conventional sense amplifier-based flip-flop (SAFF) have a "clock" power consumption and "clock". Although there is no significant difference in the power consumption of the gate, a comparison of the power consumed inside the counter shows that the power is reduced by about 51%. In the case of the counter using the conditional capture flip-flop (CCFF) according to the present invention as a whole, the power consumption can be reduced by about 30% as compared with the related art.

FIG. 11 shows a setup time and a hold time for comparing the operation speed of the conventional sense amplifier based flip-flop (SAFF) with the conditional capture flip-flop (CCFF) of the present invention. 4) is a table comparing the above. As can be seen from the table, it can be seen that the operation speed of the conditional capture flip-flop (CCFF) of the present invention does not decrease as compared with the conventional flip-flop.

Although the technical idea of the present invention has been specifically described by the above preferred embodiments, it is to be noted that the above embodiments are for the purpose of explanation, not for limitation. Should be. In addition, it should be understood that various modifications can be made by a person of ordinary skill in the technical field of the present invention within the scope of the technical idea of the present invention.

[0049]

As described above, the present invention prevents unnecessary discharge when the state of the input data is the same as the previous state in the delay / inversion unit while using the differential input. This has the effect of reducing power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic circuit of the above-described hybrid latch flip-flop according to the related art.

FIG. 2 is a circuit diagram illustrating a detailed circuit of the semi-dynamic flip-flop according to the related art.

FIG. 3 is a detailed circuit diagram of the conventional sense amplifier-based flip-flop.

FIG. 4 shows a conditional capture flip-flop (Condit) of the present invention.
FIG. 3 is a detailed circuit diagram illustrating ional-Capture Flip-Flop).

FIG. 5 is a circuit diagram of a single-ended version showing another embodiment of the present invention.

6 is a timing chart showing waveforms obtained by performing a simulation experiment on the flip-flop of FIG. 4;

7 is a timing chart showing waveforms obtained by performing a simulation experiment on the flip-flop of FIG. 5;

FIG. 8 is a diagram comparing the power consumption according to the data patterns of the flip-flop (CCFF) of the present invention and the flip-flop (SAFF) based on the sense amplifier of the related art.

FIG. 9 shows a flip-flop (CCFF) according to the present invention, a hybrid latch flip-flop (HLFF), a semi-dynamic flip-flop (SDFF), and a transmission gate master-slave flip-flop (TGFF: Tran) according to the related art.
FIG. 9 is a diagram comparing power consumption according to a data pattern with a transmission gate master-slave flip-flop).

FIG. 10 is a diagram comparing power consumption when a counter using a flip-flop (CCFF) of the present invention and a counter using a flip-flop (SAFF) of the related art are driven.

FIG. 11 shows a conventional sense amplifier-based flip-flop (S
AFF) and the conditional capture flip-flop (CCFF) of the present invention
5 is a table comparing the operation speeds of the above.

[Explanation of symbols]

 400, 420 Differential circuit section 410 Delay / inversion section 420 S-R latch section

Claims (6)

[Claims] 1. A flip-flop of a semiconductor integrated circuit, comprising: delay / inversion means for receiving and delaying / inverting a clock and receiving and inverting first and second output signals; A differential circuit controlled by an output signal of the inverting means to detect and amplify a signal level difference between the positive data and the negative data signal; an output signal of the differential circuit being input and latched; And an SR latch means for outputting a second output signal. 2. The delay / inverting means receives first and second inverters which receive and delay the clock, an output signal of the second inverter, and a first output signal from the SR latch means. 2. The flip-flop according to claim 1, further comprising a first NOR gate, and a second NOR gate to which an output signal of the second inverter and a second output signal of the SR latch are input. 3. The differential circuit means, comprising: a first precharge transistor having the gate inputted to the clock and having a source / drain path formed between a power supply voltage end and a first output node; First and second NMOS transistors each having an output signal and data of the means input at a gate terminal and serially connected between the first output node and a common node; and inverting and latching the signal of the first output node. A first latch section for generating a first final output signal, a second precharge transistor having the clock input at a gate terminal and a source / drain path formed between a power supply voltage terminal and a second output node, Third and fourth NMOS transistors, which receive the output signal of the delay / inversion means and the negative data signal at a gate terminal and are connected in series between the second output node and a common node; and the second output node The 5NMOS a second latch unit configured to generate a second final output signal by latching the inverted signal, a source drain path is input to the clock at the gate end is formed between the ground terminal and the common node
And a transistor.
4. The flip-flop according to claim 1. 4. The SR latch section, wherein a signal of the first output node is inputted at a gate terminal, and a source / drain path is a power supply voltage terminal and its own output node.
A first PMOS transistor formed between the first node and a first node; a first NMOS transistor having a source / drain path formed between the first node and a ground terminal by receiving the second final output signal at a gate terminal; A second PMOS transistor in which a signal of the first node is input at a gate terminal and a source / drain path is formed between the first output node and a second node that is an output node of the second PMOS transistor; A second NMOS transistor input at a gate terminal and having a source / drain path formed between the second final output signal and the second node; and a source / drain path receiving the signal of the second node at a gate terminal and receiving the signal at the gate terminal. A third PMOS transistor formed between the second output node and the first node; a signal from the second node input at a gate end; a source / drain path connected to the first final output node and the first A third NMOS transistor formed between the power supply voltage terminal and the second node; a third NMOS transistor formed between the power supply voltage terminal and the second node; The signal of the first final output node is input at a gate terminal, and a source / drain path includes a fourth NMOS transistor formed between the second node and a ground terminal. 3. The flip-flop according to 3. 5. A flip-flop of a semiconductor integrated circuit, wherein a clock is input at a gate terminal and a source / drain path is formed between a power supply voltage terminal and a precharge node.
A transistor; delay / inverting means for receiving and delaying a clock to input and invert a signal at an output node; and receiving the clock, data, and an output signal of the delay / inverting means at a gate end, respectively, and A first to third NMOS transistors connected in series between a charge node and a ground terminal, a first and a third NMOS transistor having the data input at a gate terminal and a source / drain path formed between a power supply voltage terminal and the precharge node; A precharge transistor, a second precharge transistor having an output signal of the delay / inversion means input at a gate terminal and a source / drain path formed between a power supply voltage terminal and the precharge node, A signal is input at the gate terminal, and a source-drain path is formed between the power supply voltage terminal and the output node. A transistor, an inverter to which the data is input, the clock,
Fourth to sixth NMOS transistors, each of which receives the output signal of the inverter and the output signal of the delay / inversion means at a gate and is connected in series between the output node and a ground terminal; A flip-flop comprising: a latch section which is inputted, latched and inverted. 6. The delay / inverting means receives first and second inverters for receiving and delaying the clock, an output signal of the second inverter, and a first output signal from the SR latch means. 6. The flip-flop according to claim 5, comprising: a first NOR gate; and a third inverter for inverting an output signal of the second inverter.