JP2000209074A - D-type flip-flop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To add functions required for forming a semiconductor integrated circuit, especially a reset function and a set function or a preferable function of coping with scan test, to the D-type flip-flop of differential-RS latch constitution. SOLUTION: As a NAND circuit for connecting input to a set input terminal connected to an output terminal D' for outputting the same value as the data input terminal D of a differential inverter 1, a 3-input NAND circuit NAND3 is used. A reset signal input terminal RSTN is connected to one of the input of the 3-input NAND circuit NAND3. A Pch transistor TP101 inserted between the set input terminal S and a high potential side power source and an Nch transistor TN101 inserted between a reset input terminal R and a low potential side power source are controlled by a set signal input terminal SETN.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a D-type flip-flop in which a master latch is constituted by a differential inverter and a slave latch is constituted by an RS latch, and more particularly to a D-type flip-flop used in a semiconductor integrated circuit. Is about.

[0002]

2. Description of the Related Art A D-type flip-flop comprises a master latch of a differential inverter and a slave latch of an RS latch, and has a function of holding input data and outputting the held data in synchronization with a clock input signal. Having.
The function of the D-type flip-flop is that data input to the data input terminal D during the evaluation period of the clock input signal directly appears at the data output terminal Q. The D-type flip-flop is a basic element for a synchronous semiconductor integrated circuit.

Hereinafter, a conventional flip-flop circuit will be described with reference to the drawings.

[0006] First, a D-type flip-flop having a general differential-RS latch configuration, which has been well known, will be described with reference to FIG. This description is a basic description of the circuit configuration and operation, and is not intended to point out a problem, and will be described later with reference to a D-type differential-RS latch configuration with a reset / set function shown in FIG. It is the basis for understanding flip-flops.

In a D-type flip-flop having a differential-RS latch configuration shown in FIG. 6, a master latch is composed of a differential inverter, and a slave latch is composed of an RS latch. In FIG. 6, reference numeral 1 denotes a differential inverter forming a master latch, and reference numeral 2 denotes an R forming a slave latch.
S latch, TP1, TP2, TP3 and TP4 are Pc
h-type MOS transistor, TN1, TN2, TN3, T
N6, TN7 and TN9 are N-channel MOS transistors, NAND1 and NAND2 are two-input NAND circuits, INV1 is an inverter circuit, CLK is a clock input terminal, D is a data input terminal, Q is a non-inverted data output terminal, and QN is inverted data. Output terminals, S and R are internal nodes of the D-type flip-flop, which are a set input terminal and a reset input terminal of the RS latch 2, and n1 and n2 are drain terminals or source terminals of the transistor TN9.

The operation of the D-type flip-flop having the differential-RS latch configuration shown in FIG. 6 will be described. Since the gate of the transistor TN9 is connected to the DC power supply and is fixed at the VDD potential which is the higher potential power supply potential, it is always in a conductive state.

First, the operation during the charging period will be described. When the clock input signal input to the clock input terminal CLK is at the VSS potential which is the lower potential power supply potential, the two Pch transistors TP1 and TP2 for charging are turned on, and the Nch transistor TN1 is turned off. Therefore, the set input terminal S of the RS latch 2 is charged to the VDD potential via the Pch transistor TP2,
The reset input terminal R is charged to the VDD potential via the Pch transistor TP1. Since the Nch transistors TN6 and TN7 are also turned on, the connection points n1 and n2 are charged to a potential obtained by subtracting the threshold voltage of the Nch transistor from the VDD potential. Even if the Nch transistors TN6 and TN7 are conductive, the source is connected to the ground and the Nch transistor T fixed at the VSS potential.
Since N1 is non-conductive, the set input terminal S
No discharge occurs from the reset input terminal R. At this time, since both the set input terminal S and the reset input terminal R of the RS latch 2 have the VDD potential, the RS latch 2
Is in the hold state, and keeps holding the data currently held. Regardless of the state of the data input terminal D, in other words, regardless of which of the Nch transistors TN2 and TN3 is conducting and which is non-conducting, N
Since the channel transistor TN1 keeps the non-conductive state, the VD of the set input terminal S and the reset input terminal R
The state of the D potential does not change. Driving Pch transistors TP3 and TP4 remain non-conductive. Such a state is called a charging period.

Next, the operation during the evaluation period will be described. When the clock input signal input to the clock input terminal CLK is VS
The period from the S potential to the VDD potential is the evaluation period. In the evaluation period, the charging Pch transistor T
P1 and TP2 are turned off, and Nch transistor TN1 is turned on. In this state, a difference in the output state of the D-type flip-flop due to a difference in data input to the data input terminal D will be described below.

When the data input terminal D is at the VSS potential, the Nch transistor TN2 is off, and the output of the inverter circuit INV1 is at the VDD potential.
Nch transistor TN3 is conductive. Connection point n
2 is connected to the ground of the VSS potential through the transistor TN3 and the transistor TN1, and as a result, the connection point n2 becomes the VSS potential faster than the connection point n1, so that the set input terminal S becomes the conductive transistor T
Discharge occurs through N7, and the set input terminal S becomes the VSS potential. Then, the Nch transistor TN6 whose gate has dropped to the VSS potential is inverted to the non-conductive state, and the gate is switched to the VS.
The driving Pch transistor TP3 that has dropped to the S potential is inverted to the conductive state, and as a result, the reset input terminal R is charged from the DC power supply via the driving Pch transistor TP3 to the VDD potential. Since the set input terminal S is at the VSS potential, the VDD potential is output to the inverted data output terminal QN, and the reset input terminal R is at the VDD potential.
Since this is a potential, the VSS potential is output to the data output terminal Q.

Contrary to the above, the data input terminal D is connected to VDD
When the potential is at the potential, the Nch transistor TN2 is conductive, and the output of the inverter circuit INV1 is at the VSS potential, so that the Nch transistor TN3 is nonconductive. The connection point n1 is connected to the ground of the VSS potential via the transistor TN2 and the transistor TN1,
As a result, the connection point n1 becomes faster than the connection point n2 by VS.
Since the potential becomes the S potential, the reset input terminal R is discharged via the transistor TN6 in a conductive state, and the reset input terminal R becomes the VSS potential. Then, the Nch transistor TN7 whose gate has dropped to the VSS potential is inverted to a non-conductive state, and the driving Pch transistor TP4 whose gate has dropped to the VSS potential is inverted to a conductive state. The set input terminal S is charged via the Pch transistor TP4 to have the VDD potential. Since the set input terminal S is at the VDD potential, the VSS potential is output to the inverted data output terminal QN. Since the reset input terminal R is at the VSS potential, the VDD potential is output to the data output terminal Q.

An output terminal D 'connected to the set input terminal S of the RS latch 2 as an output terminal of the differential inverter 1 outputs the same value as the data input to the data input terminal D. An output terminal DN 'connected to the reset input terminal R of the RS latch 2 as an output terminal of the differential inverter 1 outputs an inverted value of the data input to the data input terminal D.

The D-type flip-flop having the differential-RS latch configuration has a feature that the setup time is short, and is an effective D-type flip-flop for operating the semiconductor integrated circuit with a high frequency clock input signal.

When a D-type flip-flop is actually used in a semiconductor integrated circuit, in addition to a function of latching and outputting data in synchronization with a clock input signal, a reset function, a set function, and a test of the semiconductor integrated circuit are performed. Therefore, a function corresponding to the scan test is required to facilitate the test.

Next, these functions will be described in order with reference to the drawings.

First, the addition of the reset function will be described. This description is a basic description of the circuit configuration and operation, and is not intended to point out a problem, and will be described later with reference to a D-type differential-RS latch configuration with a reset / set function shown in FIG. It is the basis for understanding flip-flops.

FIG. 7 is a circuit diagram of a D-type flip-flop having a differential-RS latch configuration with a reset function. In FIG. 9, TP5, TP6 and TP100 are Pch
A MOS transistor, TN100 is an Nch MOS transistor, INV5 is an inverter circuit, RSTN is a reset signal input terminal, and other symbols are the same as those in FIG.

The operation of the D-type flip-flop having the differential-RS latch configuration with the reset function will be described. Regardless of the state of the set input terminal S and the reset input terminal R of the RS latch 2, when the reset signal input terminal RSTN is switched to the VSS potential of the low potential side power supply potential, it is inverted via the inverter circuit INV5. The Nch transistor TN100 is inverted to the conductive state by the VDD potential of the higher potential power supply potential, and the Pch transistor TP100 is inverted to the conductive state by the direct VSS potential from the reset signal input terminal RSTN. As a result, the set input terminal S goes to the VSS potential and the reset input terminal R goes to the VDD potential. At this time, the charging P
The channel transistors TP5 and TP6 are inverted to a non-conductive state. Further, since the set input terminal S becomes the VSS potential, the Nch transistor TN6 is turned off,
The reset input terminal R is insulated from the ground of the VSS potential, while the Pch transistor TP3 is in a conductive state, and VDD is supplied through the transistor TP3.
Since the reset input terminal R is charged from the DC power source of the potential, the reset input terminal R keeps its VDD potential. Further, since the reset input terminal R is set at the VDD potential, the Pch transistor TP4 is turned off, and
Since the channel transistor TP6 is also in a non-conductive state, charging of the set input terminal S does not occur, and the set input terminal S maintains its VSS potential.

As described above, since the reset input terminal R is at the VDD potential, the data output terminal Q
Since the S potential is output and the set input terminal S becomes the VSS potential, the VDD potential is output from the inverted data output terminal QN. That is, a reset function is realized. Since this operation is performed irrespective of the state of the clock input signal input to the clock input terminal CLK, the reset function can be realized asynchronously.

Next, the set function will be described. Here, illustration is omitted. In order to realize the reset function in the case of FIG. 7, the Nch transistor TN100 is connected to the set input terminal S, and the transistor TN100 is turned on by the reset signal to set the set input terminal S to VS.
The potential is fixed to the S potential and the Pch transistor TP1
00 is connected to a reset input terminal R, and the transistor TP100 is turned on by a reset signal to fix the reset input terminal R to the VDD potential.
The set function can be realized by the same concept. This can be easily understood by referring to FIG. 8 used in the following description. That is, a Pch transistor TP101 is connected to the set input terminal S, and the transistor TP101 is turned on by a set signal to set the set input terminal S to VD.
D potential and the Nch transistor TN1
01 may be connected to the reset input terminal R, and the transistor TN101 may be made conductive by a set signal to fix the reset input terminal R to the VSS potential. Since the reset input terminal R has the VSS potential, the VDD potential is output from the data output terminal Q, and since the set input terminal S has the VDD potential, the VSS potential is output from the inverted data output terminal QN. . That is, the set function is realized. Since this operation is performed irrespective of the state of the clock input signal input to the clock input terminal CLK, the set function can be realized asynchronously.

Next, as a conventional technique, a D-type flip-flop having a differential-RS latch configuration having both a reset function and a set function will be described with reference to FIG. FIG.
FIG. 3 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration with a reset / set function.

In FIG. 8, TP7, TP8 and TP
101 is a Pch type MOS transistor, TN101 is N
A ch-type MOS transistor, INV6 is an inverter circuit, SETN is a set signal input terminal, and others are the same as those in FIG.

Next, the operation will be described. When the reset function is not operated, the reset signal input terminal RSTN is connected to VDD.
The potential is set. Similarly, when the set function is not operated, the set signal input terminal SETN is set to the VDD potential.

To operate the reset function, the reset signal input terminal RSTN is switched to the VSS potential. As a result, as described with reference to FIG. 7, both the Nch transistor TN100 and the Pch transistor TP100 become conductive, the set input terminal S is fixed at the VSS potential, and the reset input terminal R is fixed at the VDD potential. , The VSS potential is output from the data output terminal Q, and the VDD potential is output from the inverted data output terminal QN, so that the reset function is realized asynchronously.

Next, the set function will be described. RS
Set input terminal S and reset input terminal R of latch 2
In any state, when the reset signal input terminal RSTN is at the VDD potential and the set signal input terminal SETN is switched to the VSS potential of the lower potential power supply potential, the signal is inverted via the inverter circuit INV6. The Nch transistor TN101 is inverted to the conductive state by the VDD potential of the high potential power supply potential, and the Pch transistor TP101 is inverted to the conductive state by the direct VSS potential from the set signal input terminal SETN. As a result, the set input terminal S goes to the VDD potential and the reset input terminal R goes to the VSS potential. At this time, the charging Pc
The h transistors TP7 and TP8 are inverted to a non-conductive state. Further, since the reset input terminal R becomes the VSS potential, the Nch transistor TN7 becomes non-conductive,
The set input terminal S is insulated from the ground of the VSS potential, while the Pch transistor TP4 is turned on, and the set input terminal S is charged from the DC power supply of the VDD potential via the transistor TP4. Therefore, the set input terminal S keeps its VDD potential. Further, since the set input terminal S becomes the VDD potential, Pc
Since the h transistor TP3 is turned off and the Pch transistor TP7 is also turned off, no charge is applied to the reset input terminal R, and the reset input terminal R maintains its VSS potential.

As described above, since the reset input terminal R becomes the VSS potential, the data output terminal Q
Since the D potential is output and the set input terminal S becomes the VDD potential, the VSS potential is output from the inverted data output terminal QN. That is, the set function is realized. Since this operation is performed irrespective of the state of the clock input signal input to the clock input terminal CLK, the set function can be realized asynchronously.

Here, if the reset signal input terminal RS
Consider an operation in the case where TN is switched to the VSS potential and the set input terminal S is also switched to the VSS potential.
Pch transistors TP5, TP7, TP6 for charging
TP8 is turned off. And the set input terminal S
Nch transistor TN100 connected to Pc and Pc
The h-transistor TP101 and the N-channel transistor TN101 are simultaneously turned on, and the P-channel transistor TP100 and the N-channel transistor TN101 connected to the reset input terminal R.
Are simultaneously brought into conduction.

On the set input terminal S side, the source of the Pch transistor TP101 is connected to a DC power supply of the VDD potential, and the source of the Nch transistor TN100 is connected to the ground of the VSS potential. A path occurs. Similarly,
On the reset input terminal R side, a Pch transistor T
The source of P100 is connected to a DC power supply of VDD potential, and the source of Nch transistor TN101 is VS
Since it is connected to the S potential ground,
A short-circuit path occurs between the grounds.

Here, the issue will be changed. In order to perform a scan test on a synchronous logic circuit, a large number of D-type flip-flops are all constituted by “D-type flip-flops for“ scan test ”, and they are all FFs separately from the connection with the logic circuit. Were connected serially to form a scan chain. However, in recent years, computer technology has been remarkably advanced, and it has become possible to calculate an effective test pattern without connecting all the D-type flip-flops by scan chains. The technique is called "partial scan test". As a result, only the D-type flip-flops necessary for the scan chain need to be configured with the “for scan test” D-type flip-flops.

FIG. 9 shows an example of the concept of the circuit configuration of the partial scan test. In FIG. 9, reference numeral 20 denotes a synchronous logic circuit, FF1, FF2, FF3, FF4, FF5,
FF6, FF7, and FF8 are D-type flip-flops for “scan test”, FF100, FF101, and FF10
2 and FF103 are “normal” D-type flip-flops, w1, w2, w3, w4, w5, w6, w7, w8
And w9 are wirings for forming a scan chain,
IN is a scan test input terminal, and OUT is a scan test output terminal.

Here, instead of all possible “scan test” D-type flip-flops being connected in a scan chain, the “scan test” D-type flip-flops are prepared as necessary as necessary. And they are wired scan chains. This allows
The area occupied by the entire group of “for scan test” D-type flip-flops can be reduced.

However, as the D-type flip-flop itself for "scan test", a flip-flop having a large area is still used. FIG. 10 shows the configuration of a conventional "scan test" D-type flip-flop 30 compatible with a partial scan test. This corresponds to the “for scan test” D-type flip-flops FF1 to FF1 in FIG.
FF8 is shown as a representative. In FIG. 10, 10 is a selector circuit, 11 is a "normal" D-type flip-flop, D is a data input terminal, DT is a test data input terminal, and T is input data of the data input terminal D and input of the test data input terminal DT. An input terminal of a selection signal for determining which of the data is input, CLK is a clock input terminal, Q is a non-inverted data output terminal, QN
Is an inverted data output terminal.

The test data input terminal DT is indispensable for inputting test data for performing a scan test. As shown in FIG. 9, a test data input terminal D of a D-type flip-flop for "scan test" is used.
Test data is input to T from the data output terminal Q of the preceding D-type flip-flop for “scan test” in such a manner that the test data is scanned at one clock cycle.

Referring back to FIG. 10, when the scan test is not performed, normal data is input to the data input terminal D, and the output terminal Y of the selector circuit 10 outputs the next "normal" data.
Is output to the D-type flip-flop 11. When performing a scan test, test data is input to the test data input terminal DT, and is output from the output terminal Y of the selector circuit 10 to the D-type flip-flop 11. Selector circuit 1 for alternative selection of normal data and test data
0 is required, and a selection signal input terminal T is required for the selection. The clock input signal input to the clock input terminal CLK is commonly used in the normal operation mode and the scan test mode.

[0034]

In the conventional D-type flip-flop having a differential-RS latch configuration with a reset / set function shown in FIG. In order to extract output data from both the inverted data output terminal QN and the inverted data output terminal QN, two-input NAND circuits NAND1, NAND1
It is necessary to increase the gate widths of all the transistors constituting each of the two. However, when these transistors do not operate, they load other transistors. Therefore, there is a problem that it is difficult to optimize the gate width size of the transistor.

As described above, the reset /
In a D-type flip-flop having a differential-RS latch configuration with a set function, when both the reset signal input terminal RSTN and the set signal input terminal SETN are set to the VSS potential of the low potential side power supply potential, the set input terminal S
Simultaneous conduction between the Pch transistor TP101 and the Nch transistor TN100 on the reset input terminal R side and simultaneous conduction between the Pch transistor TP100 and the Nch transistor TN101 on the reset input terminal R side generate a short-circuit path between the power supply and the ground. However, there is a problem that neither the reset function nor the set function works.

Further, in the case of the "scan test" D-type flip-flop shown in FIG. 10, there is a problem that the setup time is longer than that of the "normal" D-type flip-flop. Normally, in designing a semiconductor integrated circuit, a scan chain for a partial scan test is designed without considering a scan chain for a partial scan test, and a scan chain for a partial scan test is automatically generated by a computer in a final stage. . By generating the scan chains, some “normal” D-type flip-flops are replaced with “scan test” D-type flip-flops. The D-type flip-flop for “scan test” latches the data inside the “normal” D-type flip-flop 11 because the selector circuit 10 is provided at the input part as compared with the “normal” D-type flip-flop. The path to the part is longer, which increases setup time. Therefore, it may be necessary to redo the design related to the timing of the semiconductor integrated circuit, which is a problem. Further, the D-type flip-flop for "scan test" has a problem that the number of elements and the layout area are larger than those of the "normal" D-type flip-flop, so that the chip area is increased.

In view of the above-mentioned problems, the present invention provides a D-type flip-flop having a differential-RS latch configuration, which is a function necessary for manufacturing a semiconductor integrated circuit, particularly a reset function, a set function, or a preferable function. The task is to add a scan test function.

[0038]

Means for Solving the Problems A D-type flip-flop according to the present invention has the following configuration to solve the above-mentioned problems. The RS latch is composed of two NAND circuits, one of which is a three-input NAND circuit,
An input terminal of a low active reset signal or a set signal is connected to one of the input terminals. As long as the reset signal and the set signal are kept at the inactive high-potential-side power supply potential (VDD potential), the three-input NAN
The operation of the D circuit is substantially the same as that of the two-input NAND circuit, and performs the intended flip-flop operation. When the reset signal or the set signal is active, the low potential side power supply potential (V
SS potential), the low-potential-side power supply potential (VSS potential) is input to one input terminal of the three-input NAND circuit, and the state of the other two input terminals is in any combination. The high-potential-side power supply potential (VDD potential) is output from the output terminal of the three-input NAND circuit. Therefore, if this three-input NAND circuit is provided on the inverted output side, a reset function with a priority can be realized by the reset signal even if the set signal is input simultaneously. If a three-input NAND circuit is provided on the non-inverting output side, a priority set function is realized by the set signal even when the reset signal is input simultaneously.

Further, when both the non-inverted data output terminal and the inverted data output terminal are connected to the output terminal of the three-input NAND circuit by using an inverter circuit,
With respect to the plurality of transistors constituting each of the two NAND circuits in the RS latch, it is easy to optimize the design of how to set the gate width.

Further, a test clock input terminal is provided in addition to the normal operation clock input terminal, a test data input terminal is provided in addition to the normal operation data input terminal, and mutual interference occurs between the normal operation state and the test operation state. With no state, the test for the D-type flip-flop is realized without using the selector circuit.

[0041]

In the D-type flip-flop according to the first aspect of the present invention, the master latch is constituted by a differential inverter, the slave latch is constituted by an RS latch,
The RS latch includes a first NAND circuit having a set input terminal connected to an output terminal that outputs the same value as a data input terminal of the differential inverter, and an output terminal that outputs an inverted value opposite to the data input terminal. A D-type flip-flop having at least a reset function, wherein the first NAND circuit comprises a three-input NAND circuit. The reset signal input terminal is connected to one input terminal of the three-input NAND circuit. As long as the reset signal is kept at the inactive high-potential-side power supply potential (VDD potential), three inputs N
The operation of the AND circuit is substantially the same as that of the two-input NAND circuit, and the intended flip-flop operation is performed. When the reset signal is set to the active low potential power supply potential (VSS potential), the low potential power supply potential (VSS potential) is input to one input terminal of the three-input NAND circuit.
Regardless of the combination of the states of the other two input terminals, a high-potential power supply potential (VDD potential) is output from the output terminal of the three-input NAND circuit. Therefore, if this three-input NAND circuit is provided on the inverted output side, a reset function with a priority can be realized by the reset signal even if the set signal is input simultaneously.

A D-type flip-flop according to a second aspect of the present invention is the D-type flip-flop according to the first aspect, wherein the switching element sets the set input terminal to the high-potential power supply potential by the set signal, and sets the reset input terminal to the low potential by the set signal. And a switching element for setting the side power supply potential. A set function is also realized in addition to the reset function.

According to the third aspect of the present invention, there is provided the D-type flip-flop according to the first and second aspects, wherein the three-input NAN is provided.
An inverted data output terminal is connected to the output terminal of the D circuit, and a non-inverted data output terminal is connected to the same output terminal via an inverter circuit. With respect to the plurality of transistors constituting each of the two NAND circuits in the RS latch, it is easy to optimize the design of how to set the gate width.

According to a fourth aspect of the present invention, in the D-type flip-flop, the master latch is constituted by a differential inverter, the slave latch is constituted by an RS latch,
The latch has a first NAND circuit having a set input terminal connected to an output terminal that outputs the same value as a data input terminal of the differential inverter, and a latch connected to an output terminal that outputs an inverted value opposite to the data input terminal. A D-type flip-flop having at least a set function and a second NAND circuit to which a reset input terminal is connected, wherein the second NAND circuit is a three-input NAND circuit.
This is a configuration in which a set signal input terminal is connected to one input terminal of the three-input NAND circuit. The set signal is supplied to the inactive high-potential-side power supply potential (VDD
As long as the potential is kept at (potential), the operation of the three-input NAND circuit is substantially the same as that of the two-input NAND circuit, and the intended flip-flop operation is performed. When the set signal is set to the active low potential power supply potential (VSS potential), the low potential power supply potential (VSS potential) is input to one input terminal of the three-input NAND circuit, and the other two Regardless of the combination of the states of the input terminals, the high-potential-side power supply potential (VD
D potential) is output. Therefore, this 3
If the input NAND circuit is provided on the non-inverting output side, a priority set function is realized by the set signal even when the reset signal is input simultaneously.

A D-type flip-flop according to a fifth aspect of the present invention is the D-type flip-flop according to the fourth aspect, wherein the switching element sets the set input terminal to the lower power supply potential by the reset signal, and sets the reset input terminal to the higher potential by the reset signal. And a switching element for setting the side power supply potential. A reset function is realized in addition to the set function.

According to a sixth aspect of the present invention, there is provided the D-type flip-flop according to the fourth and fifth aspects, wherein the three-input NAN is provided.
A non-inverted data output terminal is connected to the output terminal of the D circuit, and an inverted data output terminal is connected to the same output terminal via an inverter circuit. With respect to the plurality of transistors constituting each of the two NAND circuits in the RS latch, it is easy to optimize the design of how to set the gate width.

In a D-type flip-flop according to a seventh aspect of the present invention, the master latch comprises a differential inverter, the slave latch comprises an RS latch, and the RS latch comprises
The latch has a first NAND circuit having a set input terminal connected to an output terminal that outputs the same value as a data input terminal of the differential inverter, and a latch connected to an output terminal that outputs an inverted value opposite to the data input terminal. A D-type flip-flop having a configuration having a second NAND circuit to which a reset input terminal is connected and having a reset function and a set function, wherein the first NAND circuit and the second NAND circuit are Both are constituted by a three-input NAND circuit, a reset signal input terminal is connected to one input terminal of the first three-input NAND circuit, and a set signal input terminal is connected to one input terminal of the second three-input NAND circuit. A switching element for setting a reset input terminal to a high potential side power supply potential by a reset signal from the reset signal input terminal; There a set input terminal by a set signal from the terminal as a configuration including a switching element, a high potential side power supply potential. Even when the reset signal and the set signal are output simultaneously, two three-input NA
The outputs of the ND circuits are all set to the high-potential-side power supply potential (VDD potential), and the non-inverted data output terminal outputs the high-potential-side power supply potential (VDD potential) to realize the set function and output the inverted data. The terminal is also connected to the high potential side power supply potential (V
DD potential) to realize a reset function.

The D-type flip-flop according to the eighth aspect of the present invention is a D-type flip-flop in which a master latch is constituted by a differential inverter and a slave latch is constituted by an RS latch, and which normally operates as a clock input terminal. In addition to a clock input terminal for testing, a test clock input terminal is provided, and in addition to a data input terminal for normal operation, a test data input terminal is provided as a data input terminal.
In the normal operation state, the test clock input terminal and the test data input terminal are fixed to a state that does not affect the state of the clock input terminal and the data input terminal in the normal operation. The data input terminal is fixed so as not to affect the states of the test clock input terminal and the test data input terminal. It is not necessary to use a selector circuit such as a "scan test" D-type flip-flop in the case of the conventional technology, and the setup time for performing a scan test in a scan chain configuration is the "normal" D-type flip-flop setup time. Therefore, there is no need to redesign the timing of the semiconductor integrated circuit after the scan chain occurs.

Hereinafter, specific embodiments of the D-type flip-flop according to the present invention will be described in detail with reference to the drawings.

[First Embodiment] The first embodiment is a reset function priority type. FIG. 1 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration with a reset / set function according to the first embodiment. In FIG. 1, reference numeral 1 denotes a differential inverter forming a master latch, and reference numeral 2 denotes an RS latch forming a slave latch. TP1, TP2, TP3, T
P4, TP7 and TP101 are Pch type MOS transistors, TN1, TN2, TN3, TN6, TN7, T
N9 and TN101 are N-channel MOS transistors,
NAND2 is a two-input NAND circuit, NAND3 is a three-input NAND circuit, INV1, INV6, INV10, IN
V20 and INV21 are inverter circuits, S and R
Is a set input terminal and a reset input terminal of the RS latch 2; n1 and n2 are drain or source terminals of the transistor TN9;
K is a clock input terminal, D is a data input terminal, RSTN
Is a reset signal input terminal, SETN is a set signal input terminal, Q is a data output terminal, and QN is an inverted data output terminal. These components are connected as shown. The three-input NAND circuit NAND3 corresponds to the first NAND circuit in claim 1, and the two-input NAND circuit NAN
D2 corresponds to a second NAND circuit. Each of the Pch transistor TP101 and the Nch transistor TN101 corresponds to a switching element according to claim 2.

The circuit configuration of FIG. 1 is different from that of FIG. 6 of the prior art in the following point. Reset signal input terminal RS
A TN and a set signal input terminal SETN are provided. A Pch transistor TP101 is connected between a set input terminal S of the RS latch 2 and a DC power supply having a VDD potential which is a high potential side power supply potential.
One gate is connected to the set signal input terminal SETN. A Pch transistor TP7 is connected between the Pch transistor TP1 for charging and a DC power supply having a VDD potential which is a high potential side power supply potential, and a gate of the transistor TP7 is connected to a set signal input terminal SETN via an inverter circuit INV6. ing. An Nch transistor TN101 is connected between the reset input terminal R of the RS latch 2 and the ground of the VSS potential which is the low potential side power supply potential, and the gate of the transistor TN101 is connected to the set signal input terminal SETN via the inverter circuit INV6. Have been.

DN 'is an output terminal connected to the reset input terminal R of the RS latch 2 among the output terminals of the differential inverter 1, and this output terminal DN' is the inverted value of the data input to the data input terminal D. , But R
This output terminal D as a NAND circuit in S latch 2
The NAND circuit NAND2 connected to N 'is a two-input NAND circuit as in the prior art shown in FIG.
D ′ is the RS latch 2 of the output terminals of the differential inverter 1
The output terminal D 'outputs the same value as the data input to the data input terminal D. However, this output terminal is used as a NAND circuit in the RS latch 2. The NAND circuit NAND3 connected to D 'is a three-input NAND circuit unlike the prior art shown in FIG.

The three-input NAND circuit NAND3 has one input terminal connected to the output terminal D 'which outputs the same value as the data input terminal D of the differential inverter 1, and
Another input terminal is another two-input NAND circuit N
The other input terminal is connected to the output terminal of AND2, and the other input terminal is connected to the reset signal input terminal RSTN. The two-input NAND circuit NAND2 has one input terminal connected to an output terminal DN 'that outputs an inverted value opposite to the data input terminal D of the differential inverter 1, and
Another input terminal is connected to the output terminal of the three-input NAND circuit NAND3.

In the case of FIG. 6 of the prior art, the lower 2
The output terminal of the input NAND circuit NAND2 is a Q output terminal connected to the data output terminal Q, and the output terminal of the upper two-input NAND circuit NAND1 is a QN output terminal connected to the inverted data output terminal QN. However, in the case of the first embodiment, the upper three-input NAND circuit NA
The QN output terminal that is the output terminal of ND3 is used, but the Q output terminal that is the output terminal of the lower two-input NAND circuit NAND2 is not used. Upper 3-input NAND circuit NAND
3 is connected to a non-inverted data output terminal Q via an inverter circuit INV10.
The inverted data output terminal QN is connected to the QN output terminal of the ND circuit NAND3 via two inverter circuits INV20 and INV21.

This differential-R with reset / set function
In the D-type flip-flop having the S-latch configuration, the reset signal input terminal RSTN is set to the VSS potential which is the lower potential power supply potential when the reset function is performed, and the VDD potential which is the higher potential power supply potential otherwise. It is said. The set signal input terminal SETN is set to the VSS potential when the set function is executed, and is set to VDD otherwise.
Potential.

Next, the operation of the above-configured D-type flip-flop having a differential-RS latch configuration with a reset / set function will be described. Since the gate of the transistor TN9 is connected to the DC power supply and is fixed at the VDD potential which is the higher potential power supply potential, it is always in a conductive state.

In the normal operation mode and when the set function is not executed, the set signal input terminal SET
N is the VDD potential, and the inverter circuit INV6
, The Pch transistor TP7 becomes conductive,
Nch transistor TN101 is off. In a state where the reset function is not executed, the reset signal input terminal RSTN is at the VDD potential,
One input terminal of the three-input NAND circuit NAND3 is always supplied with the VDD potential. Therefore, as long as reset signal input terminal RSTN is fixed to the VDD potential, three-input NAND circuit NAN
The operation of D3 is controlled only by the state of the output terminal D 'of the differential inverter 1 and the state of the output of the two-input NAND circuit NAND2, which means that the reset signal input terminal RSTN is fixed to the VDD potential. This means that the three-input NAND circuit NAND3 is substantially the same as the two-input NAND circuit NAND1 of FIG. As a result, the normal operation is similar to that of the prior art shown in FIG. Although the configuration is different in that the non-inverted data output terminal Q is connected to the three-input NAND circuit NAND3 via the inverter circuit INV10, the outputs from the non-inverted data output terminal Q and the inverted data output terminal QN are different. The state is exactly the same as in FIG. 6 of the prior art.

Next, consider the case where the set function is activated. Set signal input terminal SETN is changed from VDD potential to VS
When the reset signal input terminal RSTN is set to the inactive VDD potential at this time, the Pch connected to the set input terminal S
The transistor TP101 is inverted to the conductive state. Also,
The output of the inverter circuit INV6 becomes VDD potential, and P
The channel transistor TP7 is turned off and the Nch transistor TN101 is turned on. As a result, the set input terminal S is connected to the VDD power supply via the Pch transistor TP101 to be at the VDD potential, and the reset input terminal R is connected to the VSS potential ground via the Nch transistor TN101 to be at the VSS potential. Become. At this time, the charging Pch transistor TP7 is inverted to a non-conductive state. Also,
Since the reset input terminal R becomes VSS potential, Nch
The transistor TN7 becomes non-conductive, the set input terminal S becomes insulated from the ground of the VSS potential, while the Pch transistor TP4 becomes conductive,
Since the set input terminal S is charged from the DC power supply of the VDD potential via the transistor TP4, the set input terminal S maintains the VDD potential. Further, since the set input terminal S is set to the VDD potential, the Pch transistor TP3 is turned off, and the Pch transistor TP
7 is also in a non-conductive state, so that the reset input terminal R is not charged, and the reset input terminal R maintains its VSS potential.

As described above, when the set input terminal S is fixed at the VDD potential and the reset input terminal R is fixed at the VSS potential, the two-input NAND circuit NAND2 is connected regardless of the other input of the two-input NAND circuit NAND2. The output becomes the VDD potential. As for the three input terminals of the three-input NAND circuit NAND3, the VDD potential of the output of the two-input NAND circuit NAND2 is input to one input terminal, and the VDD potential of the set input terminal S is input to the other input terminal. Since the VDD potential from the reset signal input terminal RSTN is input to the other input terminal, the NAND condition is satisfied and the three-input NAND
VN is output from the QN output terminal, which is the output terminal of the circuit NAND3.
The SS potential is output.

As described above, the set input terminal S is
Since it becomes DD potential, the 3-input NAND of the RS latch 2
VN is output from the QN output terminal, which is the output terminal of the circuit NAND3.
The SS potential is output. As a result, the VDD potential is output from the data output terminal Q via one inverter circuit INV10, and the two inverter circuits INV2
0, the VSS potential is output from the inverted data output terminal QN via INV21. That is, the set function is realized. This operation is performed regardless of the value of the data input from the data input terminal D,
Further, since the setting is performed irrespective of the state of the clock input signal input to the clock input terminal CLK, the set function is realized asynchronously.

Next, consider the case where the reset function is activated. When the reset signal input terminal RSTN is switched from the VDD potential to the active VSS potential, at this time, the set signal input terminal SETN becomes the inactive VD
Assuming that the potential is D, the reset signal input terminal R
The VSS potential is input to one input terminal of the three-input NAND circuit NAND3 connected to STN. Therefore, regardless of the state of the other two input terminals of the three-input NAND circuit NAND3 in any combination, the VDD potential is output from the QN output terminal which is the output terminal of the three-input NAND circuit NAND3. As a result, the VSS potential is output from the data output terminal Q via one inverter circuit INV10, and the VDD potential is output from the inverted data output terminal QN via two inverter circuits INV20 and INV21. become. That is, a reset function is realized. This operation is performed regardless of the value of the data input from the data input terminal D and regardless of the state of the clock input signal input to the clock input terminal CLK. Is done.

Finally, when the reset function is activated,
When the reset signal input terminal RSTN was switched from the VDD potential to the active VSS potential, the set signal input terminal SETN was also at the active VSS potential.
Alternatively, consider the case where the potentials simultaneously reach the VSS potential. As described above, the reset function utilizes the logic of the NAND circuit by directly inputting the reset signal from the reset signal input terminal RSTN to the three-input NAND circuit NAND3. That is, the three-input NAND connected to the reset signal input terminal RSTN
When the VSS potential is input to one input terminal of the circuit NAND3, the three-input N input is performed by the NAND logic regardless of the state of the other two input terminals in any combination.
The VDD potential is output from the QN output terminal which is the output terminal of the AND circuit NAND3. This operation is a priority operation which is not affected by whether the output of the set signal input terminal SETN is at the VDD potential or the VSS potential. Therefore, the reset signal input terminal RSTN and the set signal input terminal SETN are both active VSS
Even if the potential is reached, the intended reset function will work. That is, VS is output from the non-inverted data output terminal Q.
S potential is output, and VD is output from the inverted data output terminal QN.
The D potential is output.

As described above, the slave latch RS
The logic of the latch and the logic of the NAND circuit are used well. Further, instead of using both outputs of the two NAND circuits as outputs of the flip-flop, one of the NANs is used.
By generating two outputs of the flip-flop from the output of the D circuit, that is, the output of the three-input NAND circuit NAND3, a reset function with a reset function with a higher priority is provided.
A D-type flip-flop having a differential-RS latch configuration with a set function can be realized with a small number of elements.

Since both the non-inverted data output terminal Q and the inverted data output terminal QN are connected to the common NAND circuit NAND3, it is easy to adjust the transistor size. This will be described with reference to FIG.

FIG. 2 shows data from the slave latch to the output terminal of a D-type flip-flop having a differential-RS latch configuration. In FIG. 2, NAND1 and NA1
ND2 is a NAND circuit, S is a set input terminal, R is a reset input terminal, Q is a data output terminal, QN is an inverted data output terminal, TP200, TP201, TP202 and TP203 are Pch type MOS transistors, TN20
0, TN201, TN202 and TN203 are Nch
The type MOS transistors INV10, INV20 and INV21 are inverter circuits.

Assume that both the set input terminal S and the reset input terminal R are in the charging period of the VDD potential, and the VDD potential is output to the data output terminal Q. In this state, when the VSS potential is output to the data output terminal Q, the set input terminal S becomes the VSS potential, the Pch transistor TP201 quickly becomes conductive, and the inverter circuit INV10 sets the data output terminal Q to the VSS potential. Until it becomes.

Assume that both the set input terminal S and the reset input terminal R are in the charging period of the VDD potential, and the VSS potential is output to the data output terminal Q. In this state, when the VDD potential is output to the data output terminal Q, the reset input terminal R becomes the VSS potential, the Pch transistor TP202 quickly becomes conductive, the Nch transistor TN200 becomes conductive, and the output of the NAND circuit NAND1 Becomes the VSS potential, and the VDD potential is transmitted to the data output terminal Q by INV10.

From the above, the transistor TP20
1, it can be seen that the driving capability of TN201, TP202 and TN200 determines the operating speed of the RS latch. Since other transistors become loads, it is desirable to make the transistor size as small as possible. Based on this knowledge, it is only necessary to increase the gate width size of some transistors, and the adjustment becomes easy.

[Second Embodiment] The second embodiment is a set function priority type. FIG.
FIG. 4 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration with a set function. The components will be described. In FIG. 3, reference numeral 1 denotes a differential inverter constituting a master latch, and reference numeral 2 denotes an R which constitutes a slave latch.
This is an S latch. TP1, TP2, TP3, TP
4, TP6 and TP100 are Pch type MOS transistors, TN1, TN2, TN3, TN6, TN7, TN
9 and TN100 are Nch MOS transistors, N
AND1 is a 2-input NAND circuit, NAND4 is a 3-input N
AND circuit, INV1, INV5, INV30, INV
31 and INV40 are inverter circuits; S and R are internal nodes of flip-flops; set input terminal and reset input terminal of RS latch 2; n1 and n2 are drain or source terminals of transistor TN9;
Is a clock input terminal, D is a data input terminal, RSTN is a reset signal input terminal, SETN is a set signal input terminal, Q is a non-inverted data output terminal, and QN is an inverted data output terminal. It is connected as follows. The two-input NAND circuit NAND1 corresponds to the first NAND circuit in claim 4, and the three-input NAND circuit NAND4 corresponds to the second NAND circuit. Nc
h transistor TN100 and Pch transistor TP1
00 corresponds to the switching element according to claim 5.

The circuit configuration of FIG. 3 is different from that of FIG. 6 of the prior art in the following point. Reset signal input terminal RS
A TN and a set signal input terminal SETN are provided. An Nch transistor TN100 is connected between the set input terminal S of the RS latch 2 and the ground of the VSS potential which is the lower potential power supply potential.
The gate of 0 is connected to the reset signal input terminal RSTN via the inverter circuit INV5. Pc for charging
h transistor TP2 and VDD which is a high potential side power supply potential
A Pch transistor TP6 is connected between the power supply and a DC power supply having a potential, and the gate of the transistor TP6 is connected to a reset signal input terminal RSTN via an inverter circuit INV5. A Pch transistor TP100 is connected between the reset input terminal R of the RS latch 2 and the DC power supply, and the gate of the transistor TP100 is directly connected to the reset signal input terminal RSTN.

D 'is an output terminal of the differential inverter 1 connected to the set input terminal S of the RS latch 2, and the output terminal D' has the same value as the data input to the data input terminal D. The NAND circuit NAND1 connected to the output terminal D 'as a NAND circuit in the RS latch 2 is a two-input NAND circuit as in the prior art shown in FIG. DN 'is an output terminal connected to the reset input terminal R of the RS latch 2 among the output terminals of the differential inverter 1, and this output terminal DN' outputs an inverted value of the data input to the data input terminal D. However, N in the RS latch 2
The NAND circuit NAND4 connected to the output terminal DN 'as an AND circuit is a three-input NAND circuit unlike the prior art shown in FIG.

The three-input NAND circuit NAND4 has one input terminal connected to the output terminal DN 'that outputs an inverted value opposite to the data input terminal D of the differential inverter 1, and the other input terminal connected to the other input terminal. Another two-input NAN
The output terminal of the D circuit NAND1 is connected, and another input terminal is connected to the set signal input terminal SETN. One input terminal of the two-input NAND circuit NAND1 is a data input terminal D of the differential inverter 1.
And the other input terminal is connected to the output terminal of a three-input NAND circuit NAND4.

In the case of FIG. 6 of the prior art, the lower 2
The output terminal of the input NAND circuit NAND2 is a Q output terminal connected to the data output terminal Q, and the output terminal of the upper two-input NAND circuit NAND1 is a QN output terminal connected to the inverted data output terminal QN. However, in the case of the second embodiment, the lower three-input NAND circuit NA
The Q output terminal that is the output terminal of ND4 is used, but the QN output terminal that is the output terminal of the upper two-input NAND circuit NAND1 is not used. Lower 3-input NAND circuit NAND
4 Q output terminals are connected to two inverter circuits INV30 and INV30.
A non-inverted data output terminal Q is connected via NV31, and an inverted data output terminal QN is connected via an inverter circuit INV40 to the Q output terminal of the same three-input NAND circuit NAND4.

This differential-R with reset / set function
In the D-type flip-flop having the S-latch configuration, the reset signal input terminal RSTN is set to the VSS potential which is the lower potential power supply potential when the reset function is performed, and the VDD potential which is the higher potential power supply potential otherwise. It is said. The set signal input terminal SETN is set to the VSS potential when the set function is executed, and is set to VDD otherwise.
Potential.

Next, the operation of the D-type flip-flop having a differential-RS latch configuration with a reset / set function having the above configuration will be described. Since the gate of the transistor TN9 is connected to the DC power supply and is fixed at the VDD potential which is the higher potential power supply potential, it is always in a conductive state.

In the normal operation mode and when the reset function is not executed, the reset signal input terminal R
STN is at the VDD potential, the Pch transistor TP100 is turned off, and the inverter circuit INV
5, the Pch transistor TP6 is turned on, and the Nch transistor TN100 is turned off. In a state where the set function is not executed, the set signal input terminal SETN is at the VDD potential,
One input terminal of the three-input NAND circuit NAND4 is always supplied with the VDD potential. Therefore, as long as set signal input terminal SETN is fixed at the VDD potential, three-input NAND circuit NAND
4 is controlled only by the state of the output terminal DN 'of the differential inverter 1 and the state of the output of the two-input NAND circuit NAND1, which means that the set signal input terminal SETN is fixed to the VDD potential. This means that the three-input NAND circuit NAND4 is substantially the same as the two-input NAND circuit NAND2 of FIG. As a result, the normal operation is similar to that of the prior art shown in FIG. Although the configuration is different in that the inverted data output terminal QN is connected to the three-input NAND circuit NAND4 via the inverter circuit INV40, the output states from the inverted data output terminal QN and the data output terminal Q are the same as those of the conventional one. It is exactly the same as the case of FIG. 6 of the technology.

Next, consider the case where the reset function is activated. The reset signal input terminal RSTN is changed from VDD potential to V
When the potential is switched to the SS potential, and at this time, the set signal input terminal SETN is at the inactive VDD potential, the Pc connected to the reset input terminal R
The h transistor TP100 is inverted to the conductive state. Further, the output of the inverter circuit INV5 becomes VDD potential, the Pch transistor TP6 is inverted to a non-conductive state, and the Nch transistor TN100 is inverted to a conductive state. As a result, the set input terminal S is connected to the ground of the VSS potential via the Nch transistor TN100 and becomes the VSS potential, and the reset input terminal R is connected to the Pch transistor
The transistor is connected to the DC power supply of the VDD potential via the transistor TP100 and becomes the VDD potential. At this time, the charging P
The channel transistor TP6 is inverted to a non-conductive state.
Further, since the set input terminal S is at the VSS potential, N
The channel transistor TN6 is turned off, and the reset input terminal R is insulated from the ground of the VSS potential, while the Pch transistor TP3 is turned on and reset from the DC power supply of the VDD potential via the transistor TP3. Since the input terminal R is charged, the reset input terminal R keeps its VDD potential. Further, since the reset input terminal R becomes the VDD potential, P
Since the channel transistor TP4 is turned off and the Pch transistor TP6 is also turned off, the charging of the set input terminal S does not occur, and the set input terminal S maintains its VSS potential.

As described above, when the set input terminal S is fixed at the VSS potential and the reset input terminal R is fixed at the VDD potential, the two-input NAND circuit NAND1 is connected regardless of the other input of the two-input NAND circuit NAND1. The output becomes the VDD potential. As for the three input terminals of the three-input NAND circuit NAND4, the VDD potential of the output of the two-input NAND circuit NAND1 is input to one input terminal, and the reset input terminal R is input to the other input terminal.
And the other input terminal is supplied with the VDD potential from the set signal input terminal SETN, so that the NAND condition is satisfied and the three-input NAND
VS is output from the Q output terminal, which is the output terminal of the circuit NAND4.
The S potential is output.

As described above, since the reset input terminal R is at the VDD potential, the three-input NAN of the RS latch 2 is
From the Q output terminal which is the output terminal of the D circuit NAND4, V
The SS potential is output. As a result, the VSS potential is output from the data output terminal Q via the two inverter circuits INV30 and INV31, and the VDD potential is output from the inverted data output terminal QN via the one inverter circuit INV40. become. That is, a reset function is realized. This operation is performed regardless of the value of the data input from the data input terminal D and regardless of the state of the clock input signal input to the clock input terminal CLK. Is done.

Next, consider the case where the set function is activated. When the set signal input terminal SETN is switched from the VDD potential to the active VSS potential, then the reset signal input terminal RSTN is set to the inactive VDD
Assuming that the potential is D, the set signal input terminal SE
The VSS potential is input to one input terminal of the three-input NAND circuit NAND4 connected to TN. Therefore, regardless of the state of the other two input terminals of the three-input NAND circuit NAND4 in any combination, the VDD potential is output from the Q output terminal which is the output terminal of the three-input NAND circuit NAND4. As a result, the VDD potential is output from the non-inverted data output terminal Q via the two inverter circuits INV30 and INV31, and the VSS potential is output from the inverted data output terminal QN via the one inverter circuit INV40. Will be done. That is, the set function is realized. This operation is performed regardless of the value of the data input from the data input terminal D, and the clock input terminal CLK
Since the setting is performed irrespective of the state of the clock input signal input to the clock signal, the set function is realized asynchronously.

Finally, in order to operate the set function, when the set signal input terminal SETN is switched from the VDD potential to the active VSS potential, the reset signal input terminal RSTN is also at the active VSS potential, or at the same time, the VSS potential is attained. Consider the case where As described above, the set function is such that the set signal from the set signal input terminal SETN is transmitted to the three-input NAND circuit NAN.
By directly inputting to D4, the logic of the NAND circuit is used. That is, the three-input NAND circuit NAN connected to the set signal input terminal SETN
When the VSS potential is input to one input terminal of D4, regardless of the state of the other two input terminals in any combination, from the Q output terminal, which is the output terminal of the three-input NAND circuit NAND4, by the NAND logic. The VDD potential is output. This operation is preferentially performed regardless of whether the output of the reset signal input terminal RSTN is at the VDD potential or the VSS potential. Therefore, even if both the set signal input terminal SETN and the reset signal input terminal RSTN become active VSS potentials, the set function as intended works. That is, the VDD potential is output from the non-inverted data output terminal Q, and the VSS potential is output from the inverted data output terminal QN.

As described above, the slave latch RS
The logic of the latch and the logic of the NAND circuit are used well. Further, instead of using both outputs of the two NAND circuits as outputs of the flip-flop, one of the NANs is used.
By making the output of the flip-flop from the output of the D circuit, that is, the three-input NAND circuit NAND4, the number of the D-type flip-flops of the differential-RS latch configuration with the reset / set function with the priority of the set function that ensures the set function works is reduced. Can be realized by number.

Since both the non-inverted data output terminal Q and the inverted data output terminal QN are connected to the common NAND circuit NAND4, the transistor size can be easily adjusted as in the first embodiment. Become.

[Third Embodiment] In the third embodiment, the set operation exhibits the original set function of setting the non-inverted data output terminal Q to the VDD potential regardless of the presence or absence of the reset operation. It is devised to exhibit the original reset function of setting the inverted data output terminal QN to the VDD potential regardless of the operation. FIG. 4 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration with a reset / set function according to the CMOS logic standard of the third embodiment.

The main components will be described. In FIG. 3, reference numerals TP110 and TP111 denote Pc
h-type MOS transistors, TN20 and TN21 are N
ch-type MOS transistor, NAND3 and NAND
4 is a 3-input NAND circuit, INV20, INV21, I
NV30 and INV31 are inverter circuits, SETN
Is a set signal input terminal, a reset signal input terminal RSTN
Is a reset signal input terminal, and other symbols are the same as those in FIG. Inverter circuits INV6 and Pc of FIG.
There is no h transistor TP7.

The characteristic circuit configuration of the third embodiment is as follows. A Pch transistor TP111 is connected between the set input terminal S of the RS latch 2 and a DC power supply having a VDD potential which is a high potential power supply potential.
The gate of 111 is connected to the set signal input terminal SETN. Reset input terminal R of RS latch 2 and VDD
Pch transistor TP110 between the DC power supply of the potential
And the gate of the transistor TP110 is connected to the reset signal input terminal RSTN.

The three-input NAND circuit NAND3 has one input terminal connected to the output terminal D 'which outputs the same value as the data input terminal D of the differential inverter 1, and
Another input terminal is the other three-input NAND circuit NAN
The other input terminal is connected to the reset signal input terminal RSTN. Another three-input NAND circuit NAND4 has one input terminal connected to the data input terminal D in the differential inverter 1.
The other input terminal is connected to an output terminal DN 'for outputting an inverted value opposite to that of the other three-input NAND circuit N.
The other input terminal is connected to the output terminal of AND3, and the other input terminal is connected to the set signal input terminal SETN.

The upper three-input NAND circuit NAND3 corresponds to the first NAND circuit according to claim 7, the lower three-input NAND circuit NAND4 corresponds to the second NAND circuit, and the Pch transistors TP111 and TP110 switch. It corresponds to the element.

Two inverter circuits IN are connected to a QN output terminal which is an output terminal of the upper three-input NAND circuit NAND3.
The inverted data output terminal QN is connected via V20 and INV21, and two inverter circuits INV3 are connected to the Q output terminal which is the output terminal of the lower three-input NAND circuit NAND4.
0, a non-inverted data output terminal Q is connected via INV31.

Two Nch transistors TN20 and TN21 are connected between the source of the Nch transistor TN1 to be connected to the ground and the ground, and the gate of one of the transistors TN20 is connected to the reset signal input terminal RS.
TN, and the gate of the other transistor TN21 is connected to the set signal input terminal SETN.

Next, the operation of the D-type flip-flop having a differential-RS latch configuration with a reset / set function having the above configuration will be described. The operation in the normal operation mode is the same as that in the first and second embodiments, and the description is omitted.

In the normal operation mode and when the set function is not executed, the set signal input terminal SET
Since N is the VDD potential, the Pch transistor TP1
11 is in a non-conductive state, and one input terminal of the lower three-input NAND circuit NAND4 is always connected to V
This means that the DD potential has been input. In the state where the reset function is not executed, the reset signal input terminal R
Since STN is at the VDD potential, the Pch transistor T
P110 is in a non-conductive state, and the upper 3
One input terminal of the input NAND circuit NAND3 is always supplied with the VDD potential. Therefore, as long as reset signal input terminal RSTN and set signal input terminal SETN are fixed to the VDD potential, the operation of upper three-input NAND circuit NAND3 depends on the state of output terminal D 'of differential inverter 1 and the other terminal. It is controlled only by the state of the output of the lower three-input NAND circuit NAND4, which means that the upper three-input NAND circuit NAND3 is substantially the same as the conventional two-input NAND circuit NAND1 of FIG. That's what it means. In addition, as long as the reset signal input terminal RSTN and the set signal input terminal SETN are fixed to the VDD potential, the operation of the lower three-input NAND circuit NAND4 depends on the output terminal DN ′ of the differential inverter 1 and the other upper terminal. Is controlled only by the output state of the three-input NAND circuit NAND3, which means that the lower three-input NAND circuit NAND4 is substantially the same as the two-input NAND circuit NAND2 of FIG. That is. As a result, the normal operation is the same as that of FIG. 6 of the related art, and the output states from the data output terminal Q and the inverted data output terminal QN are exactly the same as those of FIG. 6 of the related art. .

Next, consider the case where the set function is activated. Set signal input terminal SETN is changed from VDD potential to VS
When the reset signal input terminal RSTN is set to the inactive VDD potential at this time, the Pch connected to the set input terminal S
The transistor TP111 is inverted to the conductive state, and one input terminal of the lower three-input NAND circuit NAND4 becomes the VSS potential. 3 input NAND circuit NAND
When at least one of the four input terminals is at the VSS potential, its output terminal is at the VDD potential. Upper 3-input NAND circuit N
Looking at the input state of AND3, the reset signal input terminal R
STN is the VDD potential and the Pch transistor TP1
11 becomes conductive, so that the set input terminal S is also VDD.
And the VDD potential from the output of the three-input NAND circuit NAND4.
The output terminal 3 is at the VSS potential. Lower 3-input NAN
Since the output of the D circuit NAND4 is at the VDD potential, the non-inverted data output terminal Q is at the VDD potential, and since the output of the upper three-input NAND circuit NAND3 is at the VSS potential, the inverted data output terminal QN is at the VSS potential. Becomes That is, the set function is realized. This operation is performed regardless of the value of the data input from the data input terminal D and regardless of the state of the clock input signal input to the clock input terminal CLK, so that the set function is realized asynchronously. Is done.

Next, a case where the reset function is activated will be considered. The reset signal input terminal RSTN is changed from VDD potential to V
When the potential is switched to the SS potential, and at this time, the set signal input terminal SETN is at the inactive VDD potential, the Pc connected to the reset input terminal R
The h-transistor TP110 is inverted to the conductive state, and one input terminal of the upper three-input NAND circuit NAND3 becomes the VSS potential. 3 input NAND circuit NAND
When at least one of the input terminals 3 has the VSS potential, its output terminal has the VDD potential. Lower 3-input NAND circuit N
Looking at the input state of AND4, the set signal input terminal SE
TN is the VDD potential and the Pch transistor TP11
0 is turned on, so that the reset input terminal R is also connected to VDD.
And the output from the three-input NAND circuit NAND3 is also the VDD potential.
The output terminal 4 is at the VSS potential. Lower 3-input NAN
Since the output of the D circuit NAND4 is at the VSS potential, the non-inverted data output terminal Q is at the VSS potential, and since the output of the upper three-input NAND circuit NAND3 is at the VDD potential, the inverted data output terminal QN is at the VDD potential. Becomes That is, a reset function is realized. This operation is performed regardless of the value of the data input from the data input terminal D and regardless of the state of the clock input signal input to the clock input terminal CLK. Is done.

Lastly, the set signal input terminal SETN is set to the VSS potential to activate the set function, and the reset signal input terminal RST is activated to activate the reset function.
Consider the case where N is set to the VSS potential. Both the Pch transistor TP111 and the Pch transistor TP110 are turned on. One input of the upper three-input NAND circuit NAND3 is connected to VSS by the reset signal input terminal RSTN.
Since the potential becomes the potential, the output becomes the VDD potential, which is applied to the input of the lower three-input NAND circuit NAND4. Further, since one input of the lower three-input NAND circuit NAND4 is set to the VSS potential by the set signal input terminal SETN, its output is set to the VDD potential, which is given to the input of the upper three-input NAND circuit NAND4. Therefore, the lower three-input NAND circuit NAND4
, The reset input terminal R and the upper three-input NAN
Even if two inputs from the output of the D circuit NAND4 have the VDD potential, the set signal input terminal SETN has the VSS potential, so that the output has the VDD potential and the data output terminal Q also has the VDD potential. That is, the set function is realized. On the other hand, the upper three-input NAND circuit NA
In ND3, the set input terminal S and the lower three inputs N
Two inputs from the output of the AND circuit NAND3 are VD
The reset signal input terminal RSTN becomes V
Since the potential becomes the SS potential, the output thereof becomes the VDD potential, and the inverted data output terminal QN also becomes the VDD potential. That is, a reset function is realized.

As described above, according to the third embodiment,
D of differential-RS latch configuration conforming to CMOS logic standards
Type flip-flops have been implemented.

Fourth Embodiment A fourth embodiment provides a scan-test-compatible D-type flip-flop whose setup time is not much different from that of a normal D-type flip-flop. FIG. 5 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration corresponding to a scan test according to the fourth embodiment. Explaining only the main components, two systems of clocks, a normal operation clock and a test operation clock, are prepared. That is, a test clock input terminal CKT is provided in addition to the clock input terminal CLK. In addition to the data input terminal D, a test data input terminal DT is provided. TP10 and TP11 are Pch type MOS transistors, TN4, T
N5 and TN10 are Nch type MOS transistors, INV
2 is an inverter circuit. The RS latch 2 has two two-input NAND circuits NAN as in the case of FIG.
D1 and NAND2. Pch for charging
A Pch transistor TP10 is connected between the transistor TP1 and the DC power supply, and a Pch transistor TP11 is connected between the charging Pch transistor TP2 and the DC power supply.
Are connected, and both Pch transistors TP10, TP11
Is connected to the test clock input terminal CKT. The drain of the Nch transistor TN4 is connected to the connection point n1, and the Nch transistor TN is connected to the connection point n2.
5 are connected, and both transistors TN4, TN
5 are connected to each other, the drain of the Nch transistor TN10 is connected to the connection point, and the source is connected to the ground. Nch transistor TN1
The gate of 0 is connected to the test clock input terminal CKT.

Next, the operation of the above-configured D-type flip-flop having the differential-RS latch configuration corresponding to the scan test will be described. Since the gate of the transistor TN9 is connected to the DC power supply and is fixed at the VDD potential which is the higher potential power supply potential, it is always in a conductive state. In the normal operation state, the test clock input terminal CKT is always fixed to the VSS potential in the normal operation state, and the Pch transistors TP10 and TP11 are always in a conductive state. Further, since the Nch transistor TN10 is always in a non-conductive state in the normal operation state, the Nch transistors TN4 and TN10 are independent of the state of the test data input terminal DT.
The line N5 is irrelevant. Therefore, the normal operation is performed in the case of FIG.
3 to 3. That is, in the normal operation state, when the test clock input terminal CKT is fixed at the VSS potential, both the set input terminal S and the reset input terminal R are at the VDD potential during the charging period in which the clock input terminal CLK is at the VSS potential. , RS latch 2 enters the hold state and continues to hold the data currently held. Also, during the evaluation period when the clock input terminal CLK has become the VDD potential, the data input terminal D is at the VS level.
At the S potential, the non-inverted data output terminal Q is at the VSS potential and the inverted data output terminal QN is at the VDD potential, while when the data input terminal D is at the VDD potential, the non-inverted data output terminal Q is at the VDD potential. And the inverted data output terminal QN becomes the VSS potential.

In the scan test state, the clock input terminal CLK is fixed at the VSS potential, and the Pch transistors TP1 and TP2 are always conducting in the scan test state. Further, since the Nch transistor TN1 is turned off, the Nch transistors TN2, TN1
Instead of invalidating the line N3, the Nch transistor TN is changed according to the state of the test clock input terminal CKT.
10 will work. Therefore, in the scan test state, the relationship between the state change of the test clock input terminal CKT and the state change of the test data input terminal DT is the state change of the clock input terminal CLK and the state change of the data input terminal D in the normal operation state. And the operation is completely the same.

In the D-type flip-flop having the differential-RS latch configuration corresponding to the scan test according to the fourth embodiment, the "scan test" shown in FIG.
Since the selector circuit 10 such as the D-type flip-flop is not used, the path length from the data input terminal D to the RS latch 2 is not different from the path of the “normal” D-type flip-flop. Therefore, when performing a scan test with the scan chain configuration as shown in FIG. 9, the setup time of the D-type flip-flop of this embodiment for scan test is larger than the setup time of the “normal” D-type flip-flop. Since there is no change, it is not necessary to redesign the timing of the semiconductor integrated circuit after the occurrence of the scan chain.

[0101]

According to the present invention with respect to the D-type flip-flop having the differential-RS latch configuration, the set function or the reset function can be realized as expected even if the reset signal and the set signal are input simultaneously. it can. Also, NA
Regarding a plurality of transistors constituting the ND circuit,
It is easy to optimize the design of the gate width. Furthermore, a test for a D-type flip-flop can be realized without using a selector circuit, which is advantageous in reducing the occupied area.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration with a reset / set function according to a first embodiment of the present invention;

FIG. 2 is a circuit configuration diagram of an RS latch according to the first embodiment;

FIG. 3 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration with a reset / set function according to a second embodiment;

FIG. 4 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration with a reset / set function according to a third embodiment;

FIG. 5 is a diagram showing a differential signal corresponding to a scan test according to the fourth embodiment.
Circuit configuration diagram of a D-type flip-flop having an RS latch configuration

FIG. 6 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration according to a conventional technique.

FIG. 7 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration with a reset function according to a conventional technique.

FIG. 8 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration with a reset / set function according to a conventional technique.

FIG. 9 is a conceptual explanatory view of a conventional partial scan.

FIG. 10 is a conceptual explanatory diagram of a D-type flip-flop for “scan test” according to the related art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Differential inverter 2 ... RS latch 10 ... Selector circuit 11 ... "Normal" D-type flip-flop 20 ... Logic block 30 ... "D-type flip-flop" for scan test "TP1, TP2, TP3 , TP4, TP5, TP6, T
P7, TP10, TP11, TP100, TP101,
TP110, TP111, TP200, TP201, T
P202, TP203 ... Pch type MOS transistors TN1, TN2, TN3, TN4, TN5, TN6, T
N7, TN9, TN10, TN20, TN21, TN1
00, TN101, TN200, TN201, TN20
2, TN203 Nch MOS transistor INV1, INV2, INV5, INV6, INV1
0, INV20, INV21, INV30, INV3
1, INV40 ... Inverter circuit NAND1, NAND2 ... 2 input NAND circuit NAND3, NAND4 ... 3 input NAND circuit D ... Data input terminal DT ... Test data input terminal CLK ... Clock input terminal CKT ... Test clock Input terminal RSTN: Reset signal input terminal SETN: Set signal input terminal Q: Non-inverted data output terminal QN: Inverted data output terminal S: Set input terminal R: Reset input terminal w1, w2, w3 w4, w5, w6, w7, w8, w
9 ... Scan chain wiring

Claims (8)

[Claims] The master latch comprises a differential inverter; the slave latch comprises an RS latch;
The S-latch has a first NAND circuit whose set input terminal is connected to an output terminal that outputs the same value as the data input terminal of the differential inverter, and an output terminal that outputs an inverted value opposite to the data input terminal. A D-type flip-flop having at least a reset function and a second NAND circuit to which the reset input terminal is connected, wherein the first NAND circuit is a three-input NAN.
A D-type flip-flop comprising a D circuit, wherein a reset signal input terminal is connected to one input terminal of the three-input NAND circuit. 2. The switching device according to claim 1, further comprising: a switching element for setting a set input terminal to a high-potential power supply potential by a set signal; and a switching element for setting a reset input terminal to a low-potential power supply potential by the set signal. D-type flip-flop. 3. An inverting data output terminal is connected to an output terminal of the three-input NAND circuit, and a non-inverting data output terminal is connected to the same output terminal via an inverter circuit. D-type flip-flop. 4. The master latch comprises a differential inverter; the slave latch comprises an RS latch;
The S-latch has a first NAND circuit whose set input terminal is connected to an output terminal that outputs the same value as the data input terminal of the differential inverter, and an output terminal that outputs an inverted value opposite to the data input terminal. A D-type flip-flop having at least a set function and a second NAND circuit to which the reset input terminal is connected, wherein the second NAND circuit is a three-input NAND circuit.
A D-type flip-flop comprising a circuit and a set signal input terminal connected to one input terminal of the three-input NAND circuit. 5. The switching device according to claim 4, further comprising: a switching element for setting a set input terminal to a lower power supply potential by a reset signal; and a switching element for setting a reset input terminal to a higher power supply potential by a reset signal. D-type flip-flop. 6. The non-inverted data output terminal is connected to the output terminal of the three-input NAND circuit, and the inverted data output terminal is connected to the same output terminal via an inverter circuit. D-type flip-flop. 7. A master latch is constituted by a differential inverter, a slave latch is constituted by an RS latch,
The S-latch has a first NAND circuit whose set input terminal is connected to an output terminal that outputs the same value as the data input terminal of the differential inverter, and an output terminal that outputs an inverted value opposite to the data input terminal. A D-type flip-flop having a reset function and a set function, the circuit including a second NAND circuit to which the reset input terminal is connected, wherein the first NAND circuit and the second NAND circuit Are both constituted by a three-input NAND circuit, a reset signal input terminal is connected to one input terminal of the first three-input NAND circuit, and a set signal input terminal is connected to one input terminal of the second three-input NAND circuit. A switching element which is connected to set a reset input terminal to a high-potential-side power supply potential in response to a reset signal from the reset signal input terminal; D-type flip-flop with a configuration in which a switching element for a set input terminal and a high potential side power supply potential by the set signal from the force terminal. 8. A D-type flip-flop in which a master latch is constituted by a differential inverter and a slave latch is constituted by an RS latch, wherein a clock input terminal for a test is used as a clock input terminal in addition to a clock input terminal for a normal operation. In addition to the normal operation data input terminal as the data input terminal, the test data input terminal is provided.In the normal operation state, the test clock input terminal and the test data input terminal are connected to the normal operation clock input terminal and the data input terminal. In the test operation state, the clock input terminal and the data input terminal in the normal operation are fixed to a state that does not affect the states of the test clock input terminal and the test data input terminal. D-type flip-flop configured as described above.